OV - exec - Loop 102

	Loop Id: 102	Module: exec	Source: timestep.c:110-116	Coverage: 0.02%

0x40ee30 MOVSXD	(%R9),%RCX

0x40ee33 TEST	%ECX,%ECX

0x40ee35 JLE	40f003

0x40ee3b MOV	0x20(%RBX),%R14

0x40ee3f ADD	%R8,%RCX

0x40ee42 MOVSXD	%R8D,%RAX

0x40ee45 MOV	0x28(%RBX),%RDI

0x40ee49 MOV	0x10(%R14),%RSI

0x40ee4d LEA	(%RSI,%RCX,4),%R11

0x40ee51 LEA	(%RSI,%RAX,4),%RDX

0x40ee55 MOV	0x20(%R14),%RAX

0x40ee59 MOV	%R11,%RCX

0x40ee5c SUB	%RDX,%RCX

0x40ee5f SUB	$0x4,%RCX

0x40ee63 SHR	$0x2,%RCX

0x40ee67 INC	%RCX

0x40ee6a ADD	%R13,%RAX

0x40ee6d AND	$0x3,%ECX

0x40ee70 JE	40ef30

0x40ee76 CMP	$0x1,%RCX

0x40ee7a JE	40eef0

0x40ee7c CMP	$0x2,%RCX

0x40ee80 JE	40eeb9

0x40ee82 VMOVSD	(%RAX),%XMM1

0x40ee86 VMOVSD	0x8(%RAX),%XMM2

0x40ee8b VMULSD	%XMM2,%XMM2,%XMM4

0x40ee8f VFMADD231SD	%XMM1,%XMM1,%XMM4

0x40ee94 MOVSXD	(%RDX),%R14

0x40ee97 VMOVSD	0x10(%RAX),%XMM5

0x40ee9c ADD	$0x4,%RDX

0x40eea0 ADD	$0x18,%RAX

0x40eea4 VFMADD132SD	%XMM5,%XMM4,%XMM5

0x40eea9 SAL	$0x4,%R14

0x40eead VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM6

0x40eeb4 VFMADD231SD	%XMM5,%XMM6,%XMM0

0x40eeb9 VMOVSD	(%RAX),%XMM7

0x40eebd VMOVSD	0x8(%RAX),%XMM8

0x40eec2 VMULSD	%XMM8,%XMM8,%XMM9

0x40eec7 VFMADD231SD	%XMM7,%XMM7,%XMM9

0x40eecc MOVSXD	(%RDX),%RSI

0x40eecf VMOVSD	0x10(%RAX),%XMM10

0x40eed4 ADD	$0x4,%RDX

0x40eed8 ADD	$0x18,%RAX

0x40eedc VFMADD132SD	%XMM10,%XMM9,%XMM10

0x40eee1 SAL	$0x4,%RSI

0x40eee5 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM11

0x40eeeb VFMADD231SD	%XMM10,%XMM11,%XMM0

0x40eef0 VMOVSD	(%RAX),%XMM12

0x40eef4 VMOVSD	0x8(%RAX),%XMM13

0x40eef9 VMULSD	%XMM13,%XMM13,%XMM14

0x40eefe VFMADD231SD	%XMM12,%XMM12,%XMM14

0x40ef03 MOVSXD	(%RDX),%RCX

0x40ef06 VMOVSD	0x10(%RAX),%XMM15

0x40ef0b ADD	$0x4,%RDX

0x40ef0f ADD	$0x18,%RAX

0x40ef13 VFMADD132SD	%XMM15,%XMM14,%XMM15

0x40ef18 SAL	$0x4,%RCX

0x40ef1c VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM1

0x40ef22 VFMADD231SD	%XMM15,%XMM1,%XMM0

0x40ef27 CMP	%RDX,%R11

0x40ef2a JE	40f003

  (103) 0x40ef30 VMOVSD	(%RAX),%XMM4

  (103) 0x40ef34 VMOVSD	0x8(%RAX),%XMM2

  (103) 0x40ef39 VMULSD	%XMM2,%XMM2,%XMM5

  (103) 0x40ef3d VFMADD231SD	%XMM4,%XMM4,%XMM5

  (103) 0x40ef42 MOVSXD	(%RDX),%R14

  (103) 0x40ef45 VMOVSD	0x10(%RAX),%XMM6

  (103) 0x40ef4a VMOVSD	0x20(%RAX),%XMM8

  (103) 0x40ef4f VMULSD	%XMM8,%XMM8,%XMM9

  (103) 0x40ef54 MOVSXD	0x4(%RDX),%RSI

  (103) 0x40ef58 VMOVSD	0x28(%RAX),%XMM10

  (103) 0x40ef5d VMOVSD	0x30(%RAX),%XMM12

  (103) 0x40ef62 VMOVSD	0x38(%RAX),%XMM13

  (103) 0x40ef67 VMULSD	%XMM13,%XMM13,%XMM14

  (103) 0x40ef6c VFMADD231SD	%XMM12,%XMM12,%XMM14

  (103) 0x40ef71 MOVSXD	0x8(%RDX),%RCX

  (103) 0x40ef75 VMOVSD	0x40(%RAX),%XMM15

  (103) 0x40ef7a VFMADD132SD	%XMM6,%XMM5,%XMM6

  (103) 0x40ef7f VMOVSD	0x48(%RAX),%XMM2

  (103) 0x40ef84 VMOVSD	0x50(%RAX),%XMM1

  (103) 0x40ef89 VMULSD	%XMM1,%XMM1,%XMM5

  (103) 0x40ef8d VFMADD231SD	%XMM2,%XMM2,%XMM5

  (103) 0x40ef92 ADD	$0x10,%RDX

  (103) 0x40ef96 ADD	$0x60,%RAX

  (103) 0x40ef9a SAL	$0x4,%R14

  (103) 0x40ef9e VFMADD132SD	%XMM15,%XMM14,%XMM15

  (103) 0x40efa3 VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM7

  (103) 0x40efaa VFMADD132SD	%XMM6,%XMM0,%XMM7

  (103) 0x40efaf VMOVSD	-0x48(%RAX),%XMM0

  (103) 0x40efb4 VFMADD231SD	%XMM0,%XMM0,%XMM9

  (103) 0x40efb9 SAL	$0x4,%RSI

  (103) 0x40efbd VMOVSD	-0x8(%RAX),%XMM0

  (103) 0x40efc2 VFMADD132SD	%XMM0,%XMM5,%XMM0

  (103) 0x40efc7 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM11

  (103) 0x40efcd MOVSXD	-0x4(%RDX),%R14

  (103) 0x40efd1 VFMADD132SD	%XMM10,%XMM9,%XMM10

  (103) 0x40efd6 SAL	$0x4,%RCX

  (103) 0x40efda VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM4

  (103) 0x40efe0 VFMADD132SD	%XMM10,%XMM7,%XMM11

  (103) 0x40efe5 SAL	$0x4,%R14

  (103) 0x40efe9 VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM6

  (103) 0x40eff0 VFMADD132SD	%XMM15,%XMM11,%XMM4

  (103) 0x40eff5 VFMADD132SD	%XMM6,%XMM4,%XMM0

  (103) 0x40effa CMP	%RDX,%R11

  (103) 0x40effd JNE	40ef30

0x40f003 ADD	$0x600,%R13

0x40f00a ADD	$0x4,%R9

0x40f00e ADD	$0x40,%R8

0x40f012 CMP	%R13,%R10

0x40f015 JNE	40ee30

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Coverage (%)	Name	Source Location	Module
►98.66+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.34+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	kineticEnergy	timestep.c:123	exec
○	timestep	timestep.c:60	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.69
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P10, P11,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	1.50
Front-end cycles	8.13
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	65.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.28
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	10.94

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.69
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P10, P11,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	1.50
Front-end cycles	8.13
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	65.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.28
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	10.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.13 cycles (1.48x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 8.13 cycles (1.48x speedup).

FMA

Detected 9 FMA (fused multiply-add) operations.

Type of elements and instruction set

15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
12: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	66
nb uops	65
loop length	280
used x86 registers	12
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	5.00	7.50	7.50	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	5.00	7.50	7.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.13
Dispatch	7.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

4% of peak load performance is reached (12.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ee30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD (%R9),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40f003 <kineticEnergy._omp_fn.0+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x10(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%RSI,%RCX,4),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RAX,4),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV 0x20(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 40ef30 <kineticEnergy._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eef0 <kineticEnergy._omp_fn.0+0x140>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eeb9 <kineticEnergy._omp_fn.0+0x109>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM5,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%R14,1),%XMM3,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM5,%XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM7,%XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM10,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RSI,1),%XMM3,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM10,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM15,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RCX,1),%XMM3,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM15,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40f003 <kineticEnergy._omp_fn.0+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x600,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R13,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 40ee30 <kineticEnergy._omp_fn.0+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 8.13 cycles (1.48x speedup).

FMA

Detected 9 FMA (fused multiply-add) operations.

Type of elements and instruction set

15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
12: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	66
nb uops	65
loop length	280
used x86 registers	12
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	5.00	7.50	7.50	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	5.00	7.50	7.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.13
Dispatch	7.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

4% of peak load performance is reached (12.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40ee30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD (%R9),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40f003 <kineticEnergy._omp_fn.0+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x10(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%RSI,%RCX,4),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RAX,4),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV 0x20(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 40ef30 <kineticEnergy._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eef0 <kineticEnergy._omp_fn.0+0x140>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40eeb9 <kineticEnergy._omp_fn.0+0x109>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM5,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%R14,1),%XMM3,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM5,%XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM7,%XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM10,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RSI,1),%XMM3,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM10,%XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM13,%XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM12,%XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM15,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RCX,1),%XMM3,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM15,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 40f003 <kineticEnergy._omp_fn.0+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x600,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R13,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 40ee30 <kineticEnergy._omp_fn.0+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code