OV - exec - Function advancePosition._omp

	Function: advancePosition._omp_fn.0	Module: exec	Source: timestep.c:85-94	Coverage (incl. loops): 1.96% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

0x40e640 PUSH	%RBP

0x40e641 MOV	%RSP,%RBP

0x40e644 PUSH	%R13

0x40e646 PUSH	%R12

0x40e648 PUSH	%RBX

0x40e649 SUB	$0x8,%RSP

0x40e64d MOV	%RDI,%RBX

0x40e650 CALL	403060 <omp_get_num_threads@plt>

0x40e655 MOV	%EAX,%R12D

0x40e658 CALL	403160 <omp_get_thread_num@plt>

0x40e65d MOV	%EAX,%ECX

0x40e65f MOV	0x10(%RBX),%EAX

0x40e662 CLTD

0x40e663 IDIV	%R12D

0x40e666 CMP	%EDX,%ECX

0x40e668 JL	40e933

0x40e66e IMUL	%EAX,%ECX

0x40e671 ADD	%ECX,%EDX

0x40e673 LEA	(%RAX,%RDX,1),%ESI

0x40e676 CMP	%ESI,%EDX

0x40e678 JGE	40e928

0x40e67e MOV	(%RBX),%R13

0x40e681 MOVSXD	%EDX,%R8

0x40e684 MOV	%EAX,%R11D

0x40e687 VMOVSD	0x8(%RBX),%XMM0

0x40e68c ADD	%R8,%R11

0x40e68f VMOVSD	0x2099(%RIP),%XMM2

0x40e697 LEA	(%R11,%R11,2),%R11

0x40e69b SAL	$0x9,%R11

0x40e69f MOV	0x18(%R13),%RDI

0x40e6a3 MOV	0x78(%RDI),%R9

0x40e6a7 LEA	(%R8,%R8,2),%RDI

0x40e6ab SAL	$0x9,%RDI

0x40e6af LEA	(%R9,%R8,4),%R10

0x40e6b3 MOV	%R8,%R9

0x40e6b6 SAL	$0x6,%R9

0x40e6ba NOPW	(%RAX,%RAX,1)

(97) 0x40e6c0 MOVSXD	(%R10),%RSI

(97) 0x40e6c3 TEST	%ESI,%ESI

(97) 0x40e6c5 JLE	40e910

(97) 0x40e6cb MOV	0x20(%R13),%R12

(97) 0x40e6cf ADD	%R9,%RSI

(97) 0x40e6d2 MOVSXD	%R9D,%RCX

(97) 0x40e6d5 MOV	0x28(%R13),%RBX

(97) 0x40e6d9 MOV	0x10(%R12),%R8

(97) 0x40e6de MOV	0x18(%R12),%RAX

(97) 0x40e6e3 MOV	0x20(%R12),%RDX

(97) 0x40e6e8 LEA	(%R8,%RCX,4),%RCX

(97) 0x40e6ec LEA	(%R8,%RSI,4),%R8

(97) 0x40e6f0 ADD	%RDI,%RAX

(97) 0x40e6f3 ADD	%RDI,%RDX

(97) 0x40e6f6 MOV	%R8,%RSI

(97) 0x40e6f9 SUB	%RCX,%RSI

(97) 0x40e6fc SUB	$0x4,%RSI

(97) 0x40e700 SHR	$0x2,%RSI

(97) 0x40e704 INC	%RSI

(97) 0x40e707 AND	$0x3,%ESI

(97) 0x40e70a JE	40e803

(97) 0x40e710 CMP	$0x1,%RSI

(97) 0x40e714 JE	40e7b1

(97) 0x40e71a CMP	$0x2,%RSI

(97) 0x40e71e JE	40e769

(97) 0x40e720 MOVSXD	(%RCX),%R12

(97) 0x40e723 VMULSD	(%RDX),%XMM0,%XMM3

(97) 0x40e727 ADD	$0x4,%RCX

(97) 0x40e72b ADD	$0x18,%RAX

(97) 0x40e72f ADD	$0x18,%RDX

(97) 0x40e733 SAL	$0x4,%R12

(97) 0x40e737 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM1

(97) 0x40e73e VFMADD213SD	-0x18(%RAX),%XMM1,%XMM3

(97) 0x40e744 VMOVSD	%XMM3,-0x18(%RAX)

(97) 0x40e749 VMULSD	-0x10(%RDX),%XMM0,%XMM4

(97) 0x40e74e VFMADD213SD	-0x10(%RAX),%XMM1,%XMM4

(97) 0x40e754 VMOVSD	%XMM4,-0x10(%RAX)

(97) 0x40e759 VMULSD	-0x8(%RDX),%XMM0,%XMM5

(97) 0x40e75e VFMADD213SD	-0x8(%RAX),%XMM5,%XMM1

(97) 0x40e764 VMOVSD	%XMM1,-0x8(%RAX)

(97) 0x40e769 MOVSXD	(%RCX),%RSI

(97) 0x40e76c VMULSD	(%RDX),%XMM0,%XMM7

(97) 0x40e770 ADD	$0x4,%RCX

(97) 0x40e774 ADD	$0x18,%RAX

(97) 0x40e778 ADD	$0x18,%RDX

(97) 0x40e77c SAL	$0x4,%RSI

(97) 0x40e780 VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM6

(97) 0x40e786 VFMADD213SD	-0x18(%RAX),%XMM6,%XMM7

(97) 0x40e78c VMOVSD	%XMM7,-0x18(%RAX)

(97) 0x40e791 VMULSD	-0x10(%RDX),%XMM0,%XMM8

(97) 0x40e796 VFMADD213SD	-0x10(%RAX),%XMM6,%XMM8

(97) 0x40e79c VMOVSD	%XMM8,-0x10(%RAX)

(97) 0x40e7a1 VMULSD	-0x8(%RDX),%XMM0,%XMM9

(97) 0x40e7a6 VFMADD213SD	-0x8(%RAX),%XMM9,%XMM6

(97) 0x40e7ac VMOVSD	%XMM6,-0x8(%RAX)

(97) 0x40e7b1 MOVSXD	(%RCX),%R12

(97) 0x40e7b4 ADD	$0x4,%RCX

(97) 0x40e7b8 VMULSD	(%RDX),%XMM0,%XMM11

(97) 0x40e7bc ADD	$0x18,%RAX

(97) 0x40e7c0 ADD	$0x18,%RDX

(97) 0x40e7c4 SAL	$0x4,%R12

(97) 0x40e7c8 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM10

(97) 0x40e7cf VFMADD213SD	-0x18(%RAX),%XMM10,%XMM11

(97) 0x40e7d5 VMOVSD	%XMM11,-0x18(%RAX)

(97) 0x40e7da VMULSD	-0x10(%RDX),%XMM0,%XMM12

(97) 0x40e7df VFMADD213SD	-0x10(%RAX),%XMM10,%XMM12

(97) 0x40e7e5 VMOVSD	%XMM12,-0x10(%RAX)

(97) 0x40e7ea VMULSD	-0x8(%RDX),%XMM0,%XMM13

(97) 0x40e7ef VFMADD213SD	-0x8(%RAX),%XMM13,%XMM10

(97) 0x40e7f5 VMOVSD	%XMM10,-0x8(%RAX)

(97) 0x40e7fa CMP	%RCX,%R8

(97) 0x40e7fd JE	40e910

  (98) 0x40e803 MOVSXD	(%RCX),%RSI

  (98) 0x40e806 MOVSXD	0x4(%RCX),%R12

  (98) 0x40e80a VMULSD	(%RDX),%XMM0,%XMM15

  (98) 0x40e80e ADD	$0x10,%RCX

  (98) 0x40e812 ADD	$0x60,%RAX

  (98) 0x40e816 ADD	$0x60,%RDX

  (98) 0x40e81a SAL	$0x4,%RSI

  (98) 0x40e81e VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM14

  (98) 0x40e824 MOVSXD	-0x8(%RCX),%RSI

  (98) 0x40e828 VFMADD213SD	-0x60(%RAX),%XMM14,%XMM15

  (98) 0x40e82e VMOVSD	%XMM15,-0x60(%RAX)

  (98) 0x40e833 VMULSD	-0x58(%RDX),%XMM0,%XMM1

  (98) 0x40e838 VFMADD213SD	-0x58(%RAX),%XMM14,%XMM1

  (98) 0x40e83e VMOVSD	%XMM1,-0x58(%RAX)

  (98) 0x40e843 VMULSD	-0x50(%RDX),%XMM0,%XMM3

  (98) 0x40e848 SAL	$0x4,%R12

  (98) 0x40e84c VFMADD213SD	-0x50(%RAX),%XMM3,%XMM14

  (98) 0x40e852 VMOVSD	%XMM14,-0x50(%RAX)

  (98) 0x40e857 VMULSD	-0x48(%RDX),%XMM0,%XMM5

  (98) 0x40e85c VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM4

  (98) 0x40e863 VFMADD213SD	-0x48(%RAX),%XMM4,%XMM5

  (98) 0x40e869 VMOVSD	%XMM5,-0x48(%RAX)

  (98) 0x40e86e VMULSD	-0x40(%RDX),%XMM0,%XMM6

  (98) 0x40e873 SAL	$0x4,%RSI

  (98) 0x40e877 VFMADD213SD	-0x40(%RAX),%XMM4,%XMM6

  (98) 0x40e87d VMOVSD	%XMM6,-0x40(%RAX)

  (98) 0x40e882 VMULSD	-0x38(%RDX),%XMM0,%XMM7

  (98) 0x40e887 VFMADD213SD	-0x38(%RAX),%XMM7,%XMM4

  (98) 0x40e88d VMOVSD	%XMM4,-0x38(%RAX)

  (98) 0x40e892 VMULSD	-0x30(%RDX),%XMM0,%XMM9

  (98) 0x40e897 VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM8

  (98) 0x40e89d VFMADD213SD	-0x30(%RAX),%XMM8,%XMM9

  (98) 0x40e8a3 VMOVSD	%XMM9,-0x30(%RAX)

  (98) 0x40e8a8 VMULSD	-0x28(%RDX),%XMM0,%XMM10

  (98) 0x40e8ad VFMADD213SD	-0x28(%RAX),%XMM8,%XMM10

  (98) 0x40e8b3 VMOVSD	%XMM10,-0x28(%RAX)

  (98) 0x40e8b8 VMULSD	-0x20(%RDX),%XMM0,%XMM11

  (98) 0x40e8bd VFMADD213SD	-0x20(%RAX),%XMM11,%XMM8

  (98) 0x40e8c3 VMOVSD	%XMM8,-0x20(%RAX)

  (98) 0x40e8c8 MOVSXD	-0x4(%RCX),%R12

  (98) 0x40e8cc VMULSD	-0x18(%RDX),%XMM0,%XMM13

  (98) 0x40e8d1 SAL	$0x4,%R12

  (98) 0x40e8d5 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM12

  (98) 0x40e8dc VFMADD213SD	-0x18(%RAX),%XMM12,%XMM13

  (98) 0x40e8e2 VMOVSD	%XMM13,-0x18(%RAX)

  (98) 0x40e8e7 VMULSD	-0x10(%RDX),%XMM0,%XMM14

  (98) 0x40e8ec VFMADD213SD	-0x10(%RAX),%XMM12,%XMM14

  (98) 0x40e8f2 VMOVSD	%XMM14,-0x10(%RAX)

  (98) 0x40e8f7 VMULSD	-0x8(%RDX),%XMM0,%XMM15

  (98) 0x40e8fc VFMADD213SD	-0x8(%RAX),%XMM15,%XMM12

  (98) 0x40e902 VMOVSD	%XMM12,-0x8(%RAX)

  (98) 0x40e907 CMP	%RCX,%R8

  (98) 0x40e90a JNE	40e803

(97) 0x40e910 ADD	$0x600,%RDI

(97) 0x40e917 ADD	$0x4,%R10

(97) 0x40e91b ADD	$0x40,%R9

(97) 0x40e91f CMP	%R11,%RDI

(97) 0x40e922 JNE	40e6c0

0x40e928 ADD	$0x8,%RSP

0x40e92c POP	%RBX

0x40e92d POP	%R12

0x40e92f POP	%R13

0x40e931 POP	%RBP

0x40e932 RET

0x40e933 INC	%EAX

0x40e935 XOR	%EDX,%EDX

0x40e937 JMP	40e66e

0x40e93c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.87+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.59+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	timestep	timestep.c:85	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 0.88 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.00 to 0.40 cycles (15.06x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	47
nb uops	47
loop length	152
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	5.88
Dispatch	4.00
DIV/SQRT	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

2% of peak load performance is reached (7.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40e640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40e933 <advancePosition._omp_fn.0+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40e928 <advancePosition._omp_fn.0+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x2099(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R11,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x18(%R13),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R8,%R8,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R9,%R8,4),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40e66e <advancePosition._omp_fn.0+0x2e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 0.88 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	47
nb uops	47
loop length	152
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	5.88
Dispatch	4.00
DIV/SQRT	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

2% of peak load performance is reached (7.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40e640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40e933 <advancePosition._omp_fn.0+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40e928 <advancePosition._omp_fn.0+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x2099(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R11,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x18(%R13),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R8,%R8,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R9,%R8,4),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40e66e <advancePosition._omp_fn.0+0x2e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advancePosition._omp_fn.0–	1.96	0.50
▼Loop 97 - timestep.c:88-94 - exec–	0.28	0.06
○Loop 98 - timestep.c:88-94 - exec	1.69	0.36

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code