OV - exec - Function mkSeed

	Function: mkSeed	Module: exec	Source: random.c:45-75 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 45 - 75

--------------------------------------------------------------------------------

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

[...]

68:    uint32_t s2 = (id+callSite) * UINT32_C(2654435761);

69:

70:    uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2;

71:    for (unsigned jj=0; jj<10; ++jj)

72:       lcg61(&iSeed);

73:

74:    return iSeed;

75: }

0x40e490 IMUL	$-0x61c8864f,%EDI,%ECX

0x40e496 ADD	%ESI,%EDI

0x40e498 MOV	$0x613606df9756715,%R8

0x40e4a2 MOV	$0x9,%ESI

0x40e4a7 IMUL	$-0x61c8864f,%EDI,%EDI

0x40e4ad SAL	$0x20,%RCX

0x40e4b1 ADD	%RDI,%RCX

0x40e4b4 IMUL	%R8,%RCX

0x40e4b8 MOV	%RCX,%RAX

0x40e4bb MOV	%RCX,%R9

0x40e4be MUL	%RSI

0x40e4c1 SUB	%RDX,%R9

0x40e4c4 SHR	$0x1,%R9

0x40e4c7 ADD	%R9,%RDX

0x40e4ca SHR	$0x3c,%RDX

0x40e4ce MOV	%RDX,%R10

0x40e4d1 SAL	$0x3d,%R10

0x40e4d5 SUB	%RDX,%R10

0x40e4d8 SUB	%R10,%RCX

0x40e4db IMUL	%R8,%RCX

0x40e4df MOV	%RCX,%RAX

0x40e4e2 MOV	%RCX,%R11

0x40e4e5 MUL	%RSI

0x40e4e8 SUB	%RDX,%R11

0x40e4eb SHR	$0x1,%R11

0x40e4ee ADD	%R11,%RDX

0x40e4f1 SHR	$0x3c,%RDX

0x40e4f5 MOV	%RDX,%RDI

0x40e4f8 SAL	$0x3d,%RDI

0x40e4fc SUB	%RDX,%RDI

0x40e4ff SUB	%RDI,%RCX

0x40e502 IMUL	%R8,%RCX

0x40e506 MOV	%RCX,%RAX

0x40e509 MOV	%RCX,%R9

0x40e50c MUL	%RSI

0x40e50f SUB	%RDX,%R9

0x40e512 SHR	$0x1,%R9

0x40e515 ADD	%R9,%RDX

0x40e518 SHR	$0x3c,%RDX

0x40e51c MOV	%RDX,%R10

0x40e51f SAL	$0x3d,%R10

0x40e523 SUB	%RDX,%R10

0x40e526 SUB	%R10,%RCX

0x40e529 IMUL	%R8,%RCX

0x40e52d MOV	%RCX,%RAX

0x40e530 MOV	%RCX,%R11

0x40e533 MUL	%RSI

0x40e536 SUB	%RDX,%R11

0x40e539 SHR	$0x1,%R11

0x40e53c ADD	%R11,%RDX

0x40e53f SHR	$0x3c,%RDX

0x40e543 MOV	%RDX,%RDI

0x40e546 SAL	$0x3d,%RDI

0x40e54a SUB	%RDX,%RDI

0x40e54d SUB	%RDI,%RCX

0x40e550 IMUL	%R8,%RCX

0x40e554 MOV	%RCX,%RAX

0x40e557 MOV	%RCX,%R9

0x40e55a MUL	%RSI

0x40e55d SUB	%RDX,%R9

0x40e560 SHR	$0x1,%R9

0x40e563 ADD	%R9,%RDX

0x40e566 SHR	$0x3c,%RDX

0x40e56a MOV	%RDX,%R10

0x40e56d SAL	$0x3d,%R10

0x40e571 SUB	%RDX,%R10

0x40e574 SUB	%R10,%RCX

0x40e577 IMUL	%R8,%RCX

0x40e57b MOV	%RCX,%RAX

0x40e57e MOV	%RCX,%R11

0x40e581 MUL	%RSI

0x40e584 SUB	%RDX,%R11

0x40e587 SHR	$0x1,%R11

0x40e58a ADD	%R11,%RDX

0x40e58d SHR	$0x3c,%RDX

0x40e591 MOV	%RDX,%RDI

0x40e594 SAL	$0x3d,%RDI

0x40e598 SUB	%RDX,%RDI

0x40e59b SUB	%RDI,%RCX

0x40e59e IMUL	%R8,%RCX

0x40e5a2 MOV	%RCX,%RAX

0x40e5a5 MOV	%RCX,%R9

0x40e5a8 MUL	%RSI

0x40e5ab SUB	%RDX,%R9

0x40e5ae SHR	$0x1,%R9

0x40e5b1 ADD	%R9,%RDX

0x40e5b4 SHR	$0x3c,%RDX

0x40e5b8 MOV	%RDX,%R10

0x40e5bb SAL	$0x3d,%R10

0x40e5bf SUB	%RDX,%R10

0x40e5c2 SUB	%R10,%RCX

0x40e5c5 IMUL	%R8,%RCX

0x40e5c9 MOV	%RCX,%RAX

0x40e5cc MOV	%RCX,%R11

0x40e5cf MUL	%RSI

0x40e5d2 SUB	%RDX,%R11

0x40e5d5 SHR	$0x1,%R11

0x40e5d8 ADD	%R11,%RDX

0x40e5db SHR	$0x3c,%RDX

0x40e5df MOV	%RDX,%RDI

0x40e5e2 SAL	$0x3d,%RDI

0x40e5e6 SUB	%RDX,%RDI

0x40e5e9 SUB	%RDI,%RCX

0x40e5ec IMUL	%R8,%RCX

0x40e5f0 MOV	%RCX,%RAX

0x40e5f3 MOV	%RCX,%R9

0x40e5f6 MUL	%RSI

0x40e5f9 SUB	%RDX,%R9

0x40e5fc SHR	$0x1,%R9

0x40e5ff ADD	%R9,%RDX

0x40e602 SHR	$0x3c,%RDX

0x40e606 MOV	%RDX,%R10

0x40e609 SAL	$0x3d,%R10

0x40e60d SUB	%RDX,%R10

0x40e610 SUB	%R10,%RCX

0x40e613 IMUL	%R8,%RCX

0x40e617 MOV	%RCX,%RAX

0x40e61a MOV	%RCX,%R8

0x40e61d MUL	%RSI

0x40e620 MOV	%RCX,%RAX

0x40e623 SUB	%RDX,%R8

0x40e626 SHR	$0x1,%R8

0x40e629 ADD	%R8,%RDX

0x40e62c SHR	$0x3c,%RDX

0x40e630 MOV	%RDX,%RSI

0x40e633 SAL	$0x3d,%RSI

0x40e637 SUB	%RDX,%RSI

0x40e63a SUB	%RSI,%RAX

0x40e63d RET

0x40e63e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►63.34+	randomDisplacements._omp_fn.0	initAtoms.c:200	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►32.28+	setTemperature._omp_fn.0	initAtoms.c:160	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.39+	randomDisplacements._omp_fn.0	initAtoms.c:200	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	randomDisplacements	initAtoms.c:205	exec
○	main	CoMD.c:202	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec
►1.99+	setTemperature._omp_fn.0	initAtoms.c:160	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	setTemperature	initAtoms.c:151	exec
○	main	CoMD.c:200	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_10

Source file and lines	random.c:45-75
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-46,68-75.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.00 to 2.16 cycles (8.35x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	139
loop length	430
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.38 cycles
front end	17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.38
Dispatch	18.00
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40e490

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
IMUL $-0x61c8864f,%EDI,%ECX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
ADD %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV $0x613606df9756715,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
MOV $0x9,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL $-0x61c8864f,%EDI,%EDI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
SAL $0x20,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R8	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SUB %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
RET	1	0	0	0	0.33	0.33	0.33	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_10

Source file and lines	random.c:45-75
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-46,68-75.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	139
loop length	430
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.38 cycles
front end	17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.38
Dispatch	18.00
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40e490

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
IMUL $-0x61c8864f,%EDI,%ECX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
ADD %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV $0x613606df9756715,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
MOV $0x9,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL $-0x61c8864f,%EDI,%EDI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
SAL $0x20,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R8	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SUB %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
RET	1	0	0	0	0.33	0.33	0.33	1	0.50	N/A

Name	Coverage (%)	Time (s)
○mkSeed	0.02	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code