OV - exec - Function ljForce._omp

	Function: ljForce._omp_fn.1	Module: exec	Source: ljForce.c:172-216 [...]	Coverage (incl. loops): 81.62% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

0x40b780 PUSH	%RBP

0x40b781 MOV	%RSP,%RBP

0x40b784 PUSH	%R15

0x40b786 PUSH	%R14

0x40b788 PUSH	%R13

0x40b78a PUSH	%R12

0x40b78c PUSH	%RBX

0x40b78d MOV	%RDI,%RBX

0x40b790 SUB	$0x48,%RSP

0x40b794 MOV	(%RDI),%RAX

0x40b797 MOV	0x18(%RAX),%R12

0x40b79b MOV	%RAX,-0x50(%RBP)

0x40b79f CALL	403060 <omp_get_num_threads@plt>

0x40b7a4 MOV	%EAX,%R13D

0x40b7a7 CALL	403160 <omp_get_thread_num@plt>

0x40b7ac MOV	%EAX,%ECX

0x40b7ae MOV	0xc(%R12),%EAX

0x40b7b3 CLTD

0x40b7b4 IDIV	%R13D

0x40b7b7 CMP	%EDX,%ECX

0x40b7b9 JL	40bdd5

0x40b7bf IMUL	%EAX,%ECX

0x40b7c2 ADD	%EDX,%ECX

0x40b7c4 LEA	(%RAX,%RCX,1),%R11D

0x40b7c8 CMP	%R11D,%ECX

0x40b7cb JGE	40bdeb

0x40b7d1 MOV	0x30(%RBX),%R9D

0x40b7d5 MOVSXD	%ECX,%RSI

0x40b7d8 MOV	%ECX,%R10D

0x40b7db VMOVSD	0x587d(%RIP),%XMM10

0x40b7e3 MOV	%RSI,%R8

0x40b7e6 MOV	0x78(%R12),%RDI

0x40b7eb VMOVSD	0x20(%RBX),%XMM11

0x40b7f0 VMOVSD	0x18(%RBX),%XMM12

0x40b7f5 NOT	%R8

0x40b7f8 VMOVSD	0x10(%RBX),%XMM3

0x40b7fd VMULSD	0x8(%RBX),%XMM10,%XMM10

0x40b802 ADD	%R11D,%R8D

0x40b805 SAL	$0x6,%R10D

0x40b809 MOVSXD	%R9D,%R14

0x40b80c AND	$0x7,%R8D

0x40b810 SAL	$0x2,%R14

0x40b814 TEST	%R9D,%R9D

0x40b817 JLE	40bdf1

0x40b81d MOV	(%RDI,%RSI,4),%R15D

0x40b821 MOV	0x80(%R12),%R8

0x40b829 MOV	%RBX,-0x60(%RBP)

0x40b82d VMOVQ	%RDI,%XMM22

0x40b833 MOV	%R10D,%ECX

0x40b836 MOV	%R11D,%EBX

0x40b839 MOV	%R14,%R12

0x40b83c VXORPD	%XMM7,%XMM7,%XMM7

0x40b840 VMOVSD	0x4ee8(%RIP),%XMM9

0x40b848 VMOVSD	0x5278(%RIP),%XMM8

0x40b850 VMOVSD	0x5810(%RIP),%XMM14

0x40b858 VMOVSD	0x5810(%RIP),%XMM13

(86) 0x40b860 MOV	(%R8,%RSI,8),%R9

(86) 0x40b864 MOV	%ESI,%R13D

(86) 0x40b867 LEA	(%R15,%RCX,1),%EDX

(86) 0x40b86b MOV	%ECX,%EAX

(86) 0x40b86d VMOVD	%R15D,%XMM5

(86) 0x40b872 VMOVDQA64	%XMM22,%XMM4

(86) 0x40b878 MOV	%EDX,%ECX

(86) 0x40b87a MOV	%RSI,-0x68(%RBP)

(86) 0x40b87e SAL	$0x6,%R13D

(86) 0x40b882 MOV	%R12,-0x70(%RBP)

(86) 0x40b886 VMOVQ	%R8,%XMM21

(86) 0x40b88c MOVSXD	%R13D,%R10

(86) 0x40b88f MOV	%EBX,%R13D

(86) 0x40b892 LEA	(%R12,%R9,1),%R14

(86) 0x40b896 LEA	(,%R10,8),%R11

(86) 0x40b89e MOV	%R11,-0x48(%RBP)

(86) 0x40b8a2 MOV	%R14,-0x58(%RBP)

  (85) 0x40b8a6 MOV	(%R9),%R15D

  (85) 0x40b8a9 TEST	%R15D,%R15D

  (85) 0x40b8ac JS	40bed0

  (85) 0x40b8b2 MOVSXD	%R15D,%RBX

  (85) 0x40b8b5 VMOVQ	%XMM4,%RSI

  (85) 0x40b8ba VMOVD	%XMM5,%EDI

  (85) 0x40b8be MOV	(%RSI,%RBX,4),%R8D

  (85) 0x40b8c2 TEST	%EDI,%EDI

  (85) 0x40b8c4 JLE	40b9b4

  (85) 0x40b8ca MOV	%EAX,%R10D

  (85) 0x40b8cd LEA	(%RBX,%RBX,2),%RDX

  (85) 0x40b8d1 MOV	%EAX,%R14D

  (85) 0x40b8d4 MOV	-0x48(%RBP),%RBX

  (85) 0x40b8d8 NOT	%R10D

  (85) 0x40b8db SAL	$0x6,%R15D

  (85) 0x40b8df ADD	%ECX,%R10D

  (85) 0x40b8e2 LEA	(%R8,%R15,1),%R12D

  (85) 0x40b8e6 SAL	$0x9,%RDX

  (85) 0x40b8ea AND	$0x7,%R10D

  (85) 0x40b8ee TEST	%R8D,%R8D

  (85) 0x40b8f1 JG	40b9f4

  (85) 0x40b8f7 MOV	-0x48(%RBP),%R11

  (85) 0x40b8fb LEA	0x1(%RAX),%R14D

  (85) 0x40b8ff LEA	0x8(%R11),%RBX

  (85) 0x40b903 CMP	%ECX,%R14D

  (85) 0x40b906 JGE	40b9b4

  (85) 0x40b90c TEST	%R10D,%R10D

  (85) 0x40b90f JE	40b9a2

  (85) 0x40b915 CMP	$0x1,%R10D

  (85) 0x40b919 JE	40b991

  (85) 0x40b91b CMP	$0x2,%R10D

  (85) 0x40b91f JE	40b985

  (85) 0x40b921 CMP	$0x3,%R10D

  (85) 0x40b925 JE	40b979

  (85) 0x40b927 CMP	$0x4,%R10D

  (85) 0x40b92b JE	40b969

  (85) 0x40b92d CMP	$0x5,%R10D

  (85) 0x40b931 JE	40b959

  (85) 0x40b933 CMP	$0x6,%R10D

  (85) 0x40b937 JE	40b949

  (85) 0x40b939 TEST	%R8D,%R8D

  (85) 0x40b93c JG	40b9f4

  (85) 0x40b942 INC	%R14D

  (85) 0x40b945 ADD	$0x8,%RBX

  (85) 0x40b949 TEST	%R8D,%R8D

  (85) 0x40b94c JG	40b9f4

  (85) 0x40b952 INC	%R14D

  (85) 0x40b955 ADD	$0x8,%RBX

  (85) 0x40b959 TEST	%R8D,%R8D

  (85) 0x40b95c JG	40b9f4

  (85) 0x40b962 INC	%R14D

  (85) 0x40b965 ADD	$0x8,%RBX

  (85) 0x40b969 TEST	%R8D,%R8D

  (85) 0x40b96c JG	40b9f4

  (85) 0x40b972 INC	%R14D

  (85) 0x40b975 ADD	$0x8,%RBX

  (85) 0x40b979 TEST	%R8D,%R8D

  (85) 0x40b97c JG	40b9f4

  (85) 0x40b97e INC	%R14D

  (85) 0x40b981 ADD	$0x8,%RBX

  (85) 0x40b985 TEST	%R8D,%R8D

  (85) 0x40b988 JG	40b9f4

  (85) 0x40b98a INC	%R14D

  (85) 0x40b98d ADD	$0x8,%RBX

  (85) 0x40b991 TEST	%R8D,%R8D

  (85) 0x40b994 JG	40b9f4

  (85) 0x40b996 INC	%R14D

  (85) 0x40b999 ADD	$0x8,%RBX

  (85) 0x40b99d CMP	%ECX,%R14D

  (85) 0x40b9a0 JGE	40b9b4

    (89) 0x40b9a2 TEST	%R8D,%R8D

    (89) 0x40b9a5 JG	40b9f4

    (89) 0x40b9a7 ADD	$0x8,%R14D

    (89) 0x40b9ab ADD	$0x40,%RBX

    (89) 0x40b9af CMP	%ECX,%R14D

    (89) 0x40b9b2 JL	40b9a2

  (85) 0x40b9b4 ADD	$0x4,%R9

  (85) 0x40b9b8 CMP	%R9,-0x58(%RBP)

  (85) 0x40b9bc JNE	40b8a6

(86) 0x40b9c2 MOV	-0x68(%RBP),%RSI

(86) 0x40b9c6 MOV	%EAX,%ECX

(86) 0x40b9c8 MOV	-0x70(%RBP),%R12

(86) 0x40b9cc MOV	%R13D,%EBX

(86) 0x40b9cf VMOVQ	%XMM21,%R8

(86) 0x40b9d5 ADD	$0x40,%ECX

(86) 0x40b9d8 INC	%RSI

(86) 0x40b9db CMP	%ESI,%R13D

(86) 0x40b9de JLE	40bd99

(86) 0x40b9e4 VMOVQ	%XMM22,%R13

(86) 0x40b9ea MOV	(%R13,%RSI,4),%R15D

(86) 0x40b9ef JMP	40b860

  (85) 0x40b9f4 MOV	-0x50(%RBP),%RSI

  (85) 0x40b9f8 MOV	%EAX,-0x34(%RBP)

  (85) 0x40b9fb MOV	%RDX,%RDI

  (85) 0x40b9fe MOV	%R15D,%EAX

  (85) 0x40ba01 MOV	%R14D,%R15D

  (85) 0x40ba04 MOV	%RBX,%R14

  (85) 0x40ba07 VXORPD	%XMM6,%XMM6,%XMM6

  (85) 0x40ba0b MOV	%R9,-0x40(%RBP)

  (85) 0x40ba0f MOV	0x20(%RSI),%R8

  (85) 0x40ba13 NOPW	%CS:(%RAX,%RAX,1)

  (85) 0x40ba1e XCHG	%AX,%AX

    (87) 0x40ba20 MOV	0x18(%R8),%RBX

    (87) 0x40ba24 LEA	(%R14,%R14,2),%R9

    (87) 0x40ba28 MOV	%EAX,%R10D

    (87) 0x40ba2b NOT	%R10D

    (87) 0x40ba2e ADD	%R12D,%R10D

    (87) 0x40ba31 AND	$0x1,%R10D

    (87) 0x40ba35 LEA	(%RBX,%R9,1),%R11

    (87) 0x40ba39 ADD	%RDI,%RBX

    (87) 0x40ba3c VMOVSD	(%R11),%XMM15

    (87) 0x40ba41 VMOVSD	0x8(%R11),%XMM1

    (87) 0x40ba47 VSUBSD	(%RBX),%XMM15,%XMM16

    (87) 0x40ba4d VSUBSD	0x8(%RBX),%XMM1,%XMM1

    (87) 0x40ba52 VMULSD	%XMM1,%XMM1,%XMM0

    (87) 0x40ba56 VFMADD231SD	%XMM16,%XMM16,%XMM0

    (87) 0x40ba5c VMOVSD	0x10(%R11),%XMM2

    (87) 0x40ba62 VSUBSD	0x10(%RBX),%XMM2,%XMM2

    (87) 0x40ba67 VFMADD231SD	%XMM2,%XMM2,%XMM0

    (87) 0x40ba6c VCOMISD	%XMM0,%XMM3

    (87) 0x40ba70 JB	40baf7

    (87) 0x40ba76 VCOMISD	%XMM6,%XMM0

    (87) 0x40ba7a JBE	40baf7

    (87) 0x40ba7c VDIVSD	%XMM0,%XMM9,%XMM0

    (87) 0x40ba80 VMULSD	%XMM0,%XMM0,%XMM15

    (87) 0x40ba84 VMULSD	%XMM10,%XMM0,%XMM17

    (87) 0x40ba8a VMULSD	%XMM0,%XMM12,%XMM0

    (87) 0x40ba8e VMULSD	%XMM0,%XMM15,%XMM0

    (87) 0x40ba92 VSUBSD	%XMM9,%XMM0,%XMM15

    (87) 0x40ba97 VFMSUB132SD	%XMM0,%XMM11,%XMM15

    (87) 0x40ba9c MOV	0x30(%R8),%RDX

    (87) 0x40baa0 MOV	0x28(%R8),%RSI

    (87) 0x40baa4 VMOVAPD	%XMM15,%XMM20

    (87) 0x40baaa VFMADD231SD	%XMM8,%XMM15,%XMM7

    (87) 0x40baaf VMOVAPD	%XMM0,%XMM15

    (87) 0x40bab3 VFMADD132SD	%XMM14,%XMM13,%XMM15

    (87) 0x40bab8 ADD	%R14,%RDX

    (87) 0x40babb ADD	%R9,%RSI

    (87) 0x40babe VFMADD213SD	(%RDX),%XMM8,%XMM20

    (87) 0x40bac4 VMOVSD	%XMM20,(%RDX)

    (87) 0x40baca VMULSD	%XMM15,%XMM0,%XMM0

    (87) 0x40bacf VMULSD	%XMM17,%XMM0,%XMM15

    (87) 0x40bad5 VFNMADD213SD	(%RSI),%XMM15,%XMM16

    (87) 0x40badb VFNMADD213SD	0x8(%RSI),%XMM15,%XMM1

    (87) 0x40bae1 VMOVSD	%XMM16,(%RSI)

    (87) 0x40bae7 VFNMADD213SD	0x10(%RSI),%XMM2,%XMM15

    (87) 0x40baed VMOVSD	%XMM1,0x8(%RSI)

    (87) 0x40baf2 VMOVSD	%XMM15,0x10(%RSI)

    (87) 0x40baf7 LEA	0x1(%RAX),%EDX

    (87) 0x40bafa LEA	0x18(%RBX),%RSI

    (87) 0x40bafe CMP	%R12D,%EDX

    (87) 0x40bb01 JGE	40bd6f

    (87) 0x40bb07 TEST	%R10D,%R10D

    (87) 0x40bb0a JE	40bbe0

    (87) 0x40bb10 VMOVSD	(%R11),%XMM1

    (87) 0x40bb15 VMOVSD	0x8(%R11),%XMM2

    (87) 0x40bb1b VSUBSD	0x18(%RBX),%XMM1,%XMM18

    (87) 0x40bb22 VSUBSD	0x8(%RSI),%XMM2,%XMM1

    (87) 0x40bb27 VMULSD	%XMM1,%XMM1,%XMM0

    (87) 0x40bb2b VFMADD231SD	%XMM18,%XMM18,%XMM0

    (87) 0x40bb31 VMOVSD	0x10(%R11),%XMM15

    (87) 0x40bb37 VSUBSD	0x10(%RSI),%XMM15,%XMM2

    (87) 0x40bb3c VFMADD231SD	%XMM2,%XMM2,%XMM0

    (87) 0x40bb41 VCOMISD	%XMM0,%XMM3

    (87) 0x40bb45 JB	40bbce

    (87) 0x40bb4b VCOMISD	%XMM6,%XMM0

    (87) 0x40bb4f JBE	40bbce

    (87) 0x40bb51 VDIVSD	%XMM0,%XMM9,%XMM0

    (87) 0x40bb55 VMULSD	%XMM0,%XMM0,%XMM15

    (87) 0x40bb59 VMULSD	%XMM10,%XMM0,%XMM19

    (87) 0x40bb5f VMULSD	%XMM0,%XMM12,%XMM0

    (87) 0x40bb63 VMULSD	%XMM0,%XMM15,%XMM0

    (87) 0x40bb67 VSUBSD	%XMM9,%XMM0,%XMM15

    (87) 0x40bb6c VFMSUB132SD	%XMM0,%XMM11,%XMM15

    (87) 0x40bb71 MOV	0x30(%R8),%RBX

    (87) 0x40bb75 MOV	0x28(%R8),%R10

    (87) 0x40bb79 VMOVAPD	%XMM15,%XMM23

    (87) 0x40bb7f VFMADD231SD	%XMM8,%XMM15,%XMM7

    (87) 0x40bb84 VMOVAPD	%XMM0,%XMM15

    (87) 0x40bb88 VFMADD132SD	%XMM14,%XMM13,%XMM15

    (87) 0x40bb8d ADD	%R14,%RBX

    (87) 0x40bb90 ADD	%R9,%R10

    (87) 0x40bb93 VFMADD213SD	(%RBX),%XMM8,%XMM23

    (87) 0x40bb99 VMOVSD	%XMM23,(%RBX)

    (87) 0x40bb9f VMULSD	%XMM15,%XMM0,%XMM0

    (87) 0x40bba4 VMULSD	%XMM19,%XMM0,%XMM15

    (87) 0x40bbaa VFNMADD213SD	(%R10),%XMM15,%XMM18

    (87) 0x40bbb0 VFNMADD213SD	0x8(%R10),%XMM15,%XMM1

    (87) 0x40bbb6 VMOVSD	%XMM18,(%R10)

    (87) 0x40bbbc VFNMADD213SD	0x10(%R10),%XMM2,%XMM15

    (87) 0x40bbc2 VMOVSD	%XMM1,0x8(%R10)

    (87) 0x40bbc8 VMOVSD	%XMM15,0x10(%R10)

    (87) 0x40bbce INC	%EDX

    (87) 0x40bbd0 ADD	$0x18,%RSI

    (87) 0x40bbd4 CMP	%R12D,%EDX

    (87) 0x40bbd7 JGE	40bd6f

    (87) 0x40bbdd NOPL	(%RAX)

      (88) 0x40bbe0 VMOVSD	(%R11),%XMM1

      (88) 0x40bbe5 VMOVSD	0x8(%R11),%XMM2

      (88) 0x40bbeb VSUBSD	(%RSI),%XMM1,%XMM24

      (88) 0x40bbf1 VSUBSD	0x8(%RSI),%XMM2,%XMM1

      (88) 0x40bbf6 VMULSD	%XMM1,%XMM1,%XMM0

      (88) 0x40bbfa VFMADD231SD	%XMM24,%XMM24,%XMM0

      (88) 0x40bc00 VMOVSD	0x10(%R11),%XMM15

      (88) 0x40bc06 VSUBSD	0x10(%RSI),%XMM15,%XMM2

      (88) 0x40bc0b VFMADD231SD	%XMM2,%XMM2,%XMM0

      (88) 0x40bc10 VCOMISD	%XMM0,%XMM3

      (88) 0x40bc14 JB	40bc9d

      (88) 0x40bc1a VCOMISD	%XMM6,%XMM0

      (88) 0x40bc1e JBE	40bc9d

      (88) 0x40bc20 VDIVSD	%XMM0,%XMM9,%XMM0

      (88) 0x40bc24 VMULSD	%XMM0,%XMM0,%XMM15

      (88) 0x40bc28 VMULSD	%XMM10,%XMM0,%XMM25

      (88) 0x40bc2e VMULSD	%XMM0,%XMM12,%XMM0

      (88) 0x40bc32 VMULSD	%XMM0,%XMM15,%XMM0

      (88) 0x40bc36 VSUBSD	%XMM9,%XMM0,%XMM15

      (88) 0x40bc3b VFMSUB132SD	%XMM0,%XMM11,%XMM15

      (88) 0x40bc40 MOV	0x30(%R8),%RBX

      (88) 0x40bc44 MOV	0x28(%R8),%R10

      (88) 0x40bc48 VMOVAPD	%XMM15,%XMM26

      (88) 0x40bc4e VFMADD231SD	%XMM8,%XMM15,%XMM7

      (88) 0x40bc53 VMOVAPD	%XMM0,%XMM15

      (88) 0x40bc57 VFMADD132SD	%XMM14,%XMM13,%XMM15

      (88) 0x40bc5c ADD	%R14,%RBX

      (88) 0x40bc5f ADD	%R9,%R10

      (88) 0x40bc62 VFMADD213SD	(%RBX),%XMM8,%XMM26

      (88) 0x40bc68 VMOVSD	%XMM26,(%RBX)

      (88) 0x40bc6e VMULSD	%XMM15,%XMM0,%XMM0

      (88) 0x40bc73 VMULSD	%XMM25,%XMM0,%XMM15

      (88) 0x40bc79 VFNMADD213SD	(%R10),%XMM15,%XMM24

      (88) 0x40bc7f VFNMADD213SD	0x8(%R10),%XMM15,%XMM1

      (88) 0x40bc85 VMOVSD	%XMM24,(%R10)

      (88) 0x40bc8b VFNMADD213SD	0x10(%R10),%XMM2,%XMM15

      (88) 0x40bc91 VMOVSD	%XMM1,0x8(%R10)

      (88) 0x40bc97 VMOVSD	%XMM15,0x10(%R10)

      (88) 0x40bc9d VMOVSD	(%R11),%XMM1

      (88) 0x40bca2 VMOVSD	0x8(%R11),%XMM2

      (88) 0x40bca8 VSUBSD	0x18(%RSI),%XMM1,%XMM27

      (88) 0x40bcaf VSUBSD	0x20(%RSI),%XMM2,%XMM1

      (88) 0x40bcb4 VMULSD	%XMM1,%XMM1,%XMM0

      (88) 0x40bcb8 VFMADD231SD	%XMM27,%XMM27,%XMM0

      (88) 0x40bcbe VMOVSD	0x10(%R11),%XMM15

      (88) 0x40bcc4 VSUBSD	0x28(%RSI),%XMM15,%XMM15

      (88) 0x40bcc9 INC	%EDX

      (88) 0x40bccb LEA	0x18(%RSI),%RBX

      (88) 0x40bccf VFMADD231SD	%XMM15,%XMM15,%XMM0

      (88) 0x40bcd4 VCOMISD	%XMM0,%XMM3

      (88) 0x40bcd8 JB	40bd60

      (88) 0x40bcde VCOMISD	%XMM6,%XMM0

      (88) 0x40bce2 JBE	40bd60

      (88) 0x40bce4 VDIVSD	%XMM0,%XMM9,%XMM0

      (88) 0x40bce8 VMULSD	%XMM0,%XMM0,%XMM2

      (88) 0x40bcec VMULSD	%XMM10,%XMM0,%XMM28

      (88) 0x40bcf2 VMULSD	%XMM0,%XMM12,%XMM0

      (88) 0x40bcf6 VMULSD	%XMM0,%XMM2,%XMM0

      (88) 0x40bcfa VSUBSD	%XMM9,%XMM0,%XMM2

      (88) 0x40bcff VFMSUB132SD	%XMM0,%XMM11,%XMM2

      (88) 0x40bd04 MOV	0x30(%R8),%RSI

      (88) 0x40bd08 MOV	0x28(%R8),%R10

      (88) 0x40bd0c VMOVAPD	%XMM2,%XMM29

      (88) 0x40bd12 VFMADD231SD	%XMM8,%XMM2,%XMM7

      (88) 0x40bd17 VMOVAPD	%XMM0,%XMM2

      (88) 0x40bd1b VFMADD132SD	%XMM14,%XMM13,%XMM2

      (88) 0x40bd20 ADD	%R14,%RSI

      (88) 0x40bd23 ADD	%R9,%R10

      (88) 0x40bd26 VFMADD213SD	(%RSI),%XMM8,%XMM29

      (88) 0x40bd2c VMOVSD	%XMM29,(%RSI)

      (88) 0x40bd32 VMULSD	%XMM2,%XMM0,%XMM0

      (88) 0x40bd36 VMULSD	%XMM28,%XMM0,%XMM2

      (88) 0x40bd3c VFNMADD213SD	(%R10),%XMM2,%XMM27

      (88) 0x40bd42 VFNMADD213SD	0x8(%R10),%XMM2,%XMM1

      (88) 0x40bd48 VMOVSD	%XMM27,(%R10)

      (88) 0x40bd4e VFNMADD213SD	0x10(%R10),%XMM15,%XMM2

      (88) 0x40bd54 VMOVSD	%XMM1,0x8(%R10)

      (88) 0x40bd5a VMOVSD	%XMM2,0x10(%R10)

      (88) 0x40bd60 INC	%EDX

      (88) 0x40bd62 LEA	0x18(%RBX),%RSI

      (88) 0x40bd66 CMP	%R12D,%EDX

      (88) 0x40bd69 JL	40bbe0

    (87) 0x40bd6f INC	%R15D

    (87) 0x40bd72 ADD	$0x8,%R14

    (87) 0x40bd76 CMP	%R15D,%ECX

    (87) 0x40bd79 JG	40ba20

  (85) 0x40bd7f MOV	-0x40(%RBP),%R9

  (85) 0x40bd83 MOV	-0x34(%RBP),%EAX

  (85) 0x40bd86 ADD	$0x4,%R9

  (85) 0x40bd8a CMP	%R9,-0x58(%RBP)

  (85) 0x40bd8e JNE	40b8a6

(86) 0x40bd94 JMP	40b9c2

0x40bd99 MOV	-0x60(%RBP),%RBX

0x40bd9d MOV	0x28(%RBX),%RDX

0x40bda1 LEA	0x28(%RBX),%R11

(84) 0x40bda5 VMOVQ	%RDX,%XMM1

(84) 0x40bdaa MOV	%RDX,%RAX

(84) 0x40bdad VADDSD	%XMM1,%XMM7,%XMM15

(84) 0x40bdb1 VMOVQ	%XMM15,%R10

(84) 0x40bdb6 LOCK CMPXCHG	%R10,(%R11)

(84) 0x40bdbb MOV	%RDX,%RDI

(84) 0x40bdbe MOV	%RAX,%RDX

(84) 0x40bdc1 CMP	%RAX,%RDI

(84) 0x40bdc4 JNE	40bda5

0x40bdc6 ADD	$0x48,%RSP

0x40bdca POP	%RBX

0x40bdcb POP	%R12

0x40bdcd POP	%R13

0x40bdcf POP	%R14

0x40bdd1 POP	%R15

0x40bdd3 POP	%RBP

0x40bdd4 RET

0x40bdd5 INC	%EAX

0x40bdd7 XOR	%EDX,%EDX

0x40bdd9 IMUL	%EAX,%ECX

0x40bddc ADD	%EDX,%ECX

0x40bdde LEA	(%RAX,%RCX,1),%R11D

0x40bde2 CMP	%R11D,%ECX

0x40bde5 JL	40b7d1

0x40bdeb VXORPD	%XMM7,%XMM7,%XMM7

0x40bdef JMP	40bd9d

0x40bdf1 INC	%RSI

0x40bdf4 ADD	$0x40,%R10D

0x40bdf8 CMP	%ESI,%R11D

0x40bdfb JLE	40bdeb

0x40bdfd TEST	%R8D,%R8D

0x40be00 JE	40bea3

0x40be06 CMP	$0x1,%R8D

0x40be0a JE	40be8a

0x40be0c CMP	$0x2,%R8D

0x40be10 JE	40be7a

0x40be12 CMP	$0x3,%R8D

0x40be16 JE	40be6a

0x40be18 CMP	$0x4,%R8D

0x40be1c JE	40be5a

0x40be1e CMP	$0x5,%R8D

0x40be22 JE	40be4a

0x40be24 CMP	$0x6,%R8D

0x40be28 JE	40be3a

0x40be2a TEST	%R9D,%R9D

0x40be2d JG	40b81d

0x40be33 INC	%RSI

0x40be36 ADD	$0x40,%R10D

0x40be3a TEST	%R9D,%R9D

0x40be3d JG	40b81d

0x40be43 INC	%RSI

0x40be46 ADD	$0x40,%R10D

0x40be4a TEST	%R9D,%R9D

0x40be4d JG	40b81d

0x40be53 INC	%RSI

0x40be56 ADD	$0x40,%R10D

0x40be5a TEST	%R9D,%R9D

0x40be5d JG	40b81d

0x40be63 INC	%RSI

0x40be66 ADD	$0x40,%R10D

0x40be6a TEST	%R9D,%R9D

0x40be6d JG	40b81d

0x40be73 INC	%RSI

0x40be76 ADD	$0x40,%R10D

0x40be7a TEST	%R9D,%R9D

0x40be7d JG	40b81d

0x40be83 INC	%RSI

0x40be86 ADD	$0x40,%R10D

0x40be8a TEST	%R9D,%R9D

0x40be8d JG	40b81d

0x40be93 INC	%RSI

0x40be96 ADD	$0x40,%R10D

0x40be9a CMP	%ESI,%R11D

0x40be9d JLE	40bdeb

(90) 0x40bea3 TEST	%R9D,%R9D

(90) 0x40bea6 JG	40b81d

(90) 0x40beac ADD	$0x8,%RSI

(90) 0x40beb0 ADD	$0x200,%R10D

(90) 0x40beb7 CMP	%ESI,%R11D

(90) 0x40beba JG	40bea3

0x40bebc JMP	40bdeb

0x40bec1 NOPW	%CS:(%RAX,%RAX,1)

0x40becc NOPL	(%RAX)

0x40bed0 MOV	$0x411058,%ECX

0x40bed5 MOV	$0xb6,%EDX

0x40beda MOV	$0x410f70,%ESI

0x40bedf MOV	$0x411050,%EDI

0x40bee4 CALL	4030c0 <__assert_fail@plt>

0x40bee9 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.95+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.63+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.63 to 6.67 cycles (2.49x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 16.63 to 1.17 cycles (14.19x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 132 bytes (16 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	133
nb uops	133
loop length	509
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.63 cycles
front end	16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.00	0.00
cycles	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	16.63
Dispatch	14.33
DIV/SQRT	6.00
Overall L1	16.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	18%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	7%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	11%
store	12%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.63 cycles. At this rate:

3% of peak load performance is reached (7.94 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.63 to 14.33 cycles (1.16x speedup).

ASM code

In the binary file, the address of the function is: 40b780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc(%R12),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40bdd5 <ljForce._omp_fn.1+0x655>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40bdeb <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBX),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVSXD %ECX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD 0x587d(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x78(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x20(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOT %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD 0x10(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD 0x8(%RBX),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %R11D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R10D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD %R9D,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x2,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40bdf1 <ljForce._omp_fn.1+0x671>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RDI,%RSI,4),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x80(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %RDI,%XMM22	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R10D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0x4ee8(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x5278(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x5810(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x5810(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA 0x28(%RBX),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40b7d1 <ljForce._omp_fn.1+0x51>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 40bd9d <ljForce._omp_fn.1+0x61d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40bdeb <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40bea3 <ljForce._omp_fn.1+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be8a <ljForce._omp_fn.1+0x70a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be7a <ljForce._omp_fn.1+0x6fa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be6a <ljForce._omp_fn.1+0x6ea>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be5a <ljForce._omp_fn.1+0x6da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be4a <ljForce._omp_fn.1+0x6ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be3a <ljForce._omp_fn.1+0x6ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 40bdeb <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 40bdeb <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x411058,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0xb6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x410f70,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x411050,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	ljForce.c:172-216
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.63 to 6.67 cycles (2.49x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:182
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:173

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 132 bytes (16 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	133
nb uops	133
loop length	509
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.63 cycles
front end	16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.00	0.00
cycles	14.33	14.33	14.33	14.33	14.33	14.33	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	16.63
Dispatch	14.33
DIV/SQRT	6.00
Overall L1	16.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	18%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	7%
load	9%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	14%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	8%
load	11%
store	12%
mul	12%
add-sub	7%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.63 cycles. At this rate:

3% of peak load performance is reached (7.94 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.96 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40b780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc(%R12),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40bdd5 <ljForce._omp_fn.1+0x655>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40bdeb <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RBX),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOVSXD %ECX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVSD 0x587d(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x78(%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x20(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%RBX),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
NOT %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSD 0x10(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD 0x8(%RBX),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
ADD %R11D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%R10D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD %R9D,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x2,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40bdf1 <ljForce._omp_fn.1+0x671>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RDI,%RSI,4),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x80(%R12),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %RDI,%XMM22	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %R10D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSD 0x4ee8(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x5278(%RIP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x5810(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x5810(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA 0x28(%RBX),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x48,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40b7d1 <ljForce._omp_fn.1+0x51>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 40bd9d <ljForce._omp_fn.1+0x61d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40bdeb <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40bea3 <ljForce._omp_fn.1+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be8a <ljForce._omp_fn.1+0x70a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be7a <ljForce._omp_fn.1+0x6fa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be6a <ljForce._omp_fn.1+0x6ea>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be5a <ljForce._omp_fn.1+0x6da>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be4a <ljForce._omp_fn.1+0x6ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 40be3a <ljForce._omp_fn.1+0x6ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 40b81d <ljForce._omp_fn.1+0x9d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %ESI,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 40bdeb <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 40bdeb <ljForce._omp_fn.1+0x66b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x411058,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0xb6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x410f70,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x411050,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼ljForce._omp_fn.1–	81.62	20.90
▼Loop 86 - ljForce.c:175-216 - exec–	0.01	0.01
▼Loop 85 - ljForce.c:178-216 - exec–	0.28	0.06
▼Loop 87 - ljForce.c:187-216 - exec–	11.85	2.55
○Loop 88 - ljForce.c:191-216 - exec	69.48	14.92
○Loop 89 - ljForce.c:187-191 - exec	0.00	0.00
○Loop 90 - ljForce.c:178-178 - exec	0.00	0.00
○Loop 84 - ljForce.c:172-172 - exec	0.00	0.00

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