OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:288-385 [...]	Coverage (incl. loops): 0.08% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 288 - 385

--------------------------------------------------------------------------------

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40b090 PUSH	%RBP

0x40b091 MOV	%RSP,%RBP

0x40b094 PUSH	%R15

0x40b096 PUSH	%R14

0x40b098 PUSH	%R13

0x40b09a PUSH	%R12

0x40b09c PUSH	%RBX

0x40b09d MOV	%RSI,%R13

0x40b0a0 MOV	%RDI,%RBX

0x40b0a3 SUB	$0x18,%RSP

0x40b0a7 MOVSXD	0xc(%RDI),%RAX

0x40b0ab CMP	0x14(%RDI),%EAX

0x40b0ae JGE	40b0d2

0x40b0b0 MOV	0x78(%RDI),%RDX

0x40b0b4 NOPW	%CS:(%RAX,%RAX,1)

0x40b0bf NOP

(81) 0x40b0c0 MOVL	$0,(%RDX,%RAX,4)

(81) 0x40b0c7 INC	%RAX

(81) 0x40b0ca CMP	%EAX,0x14(%RBX)

(81) 0x40b0cd JG	40b0c0

0x40b0cf MOV	0xc(%RBX),%EAX

0x40b0d2 TEST	%EAX,%EAX

0x40b0d4 JLE	40b179

0x40b0da MOV	0x78(%RBX),%R9

0x40b0de XOR	%R12D,%R12D

0x40b0e1 NOPW	%CS:(%RAX,%RAX,1)

0x40b0ec NOPL	(%RAX)

(79) 0x40b0f0 MOV	(%R9,%R12,4),%ESI

(79) 0x40b0f4 MOV	%R12D,%ECX

(79) 0x40b0f7 LEA	(,%R12,4),%R14

(79) 0x40b0ff XOR	%R15D,%R15D

(79) 0x40b102 MOV	%R12D,-0x38(%RBP)

(79) 0x40b106 SAL	$0x6,%ECX

(79) 0x40b109 MOV	%ECX,-0x34(%RBP)

(79) 0x40b10c TEST	%ESI,%ESI

(79) 0x40b10e JG	40b13e

(79) 0x40b110 JMP	40b16c

0x40b112 NOPW	%CS:(%RAX,%RAX,1)

0x40b11d NOPL	(%RAX)

  (80) 0x40b120 MOV	-0x38(%RBP),%ECX

  (80) 0x40b123 MOV	%EAX,%R8D

  (80) 0x40b126 MOV	%R15D,%EDX

  (80) 0x40b129 MOV	%R13,%RSI

  (80) 0x40b12c MOV	%RBX,%RDI

  (80) 0x40b12f CALL	40afe0 <moveAtom>

  (80) 0x40b134 MOV	0x78(%RBX),%R9

  (80) 0x40b138 CMP	%R15D,(%R9,%R14,1)

  (80) 0x40b13c JLE	40b16c

  (80) 0x40b13e MOV	-0x34(%RBP),%EAX

  (80) 0x40b141 MOV	0x18(%R13),%R8

  (80) 0x40b145 ADD	%R15D,%EAX

  (80) 0x40b148 CLTQ

  (80) 0x40b14a LEA	(%RAX,%RAX,2),%RDI

  (80) 0x40b14e LEA	(%R8,%RDI,8),%RSI

  (80) 0x40b152 MOV	%RBX,%RDI

  (80) 0x40b155 CALL	40ae40 <getBoxFromCoord>

  (80) 0x40b15a CMP	%R12D,%EAX

  (80) 0x40b15d JNE	40b120

  (80) 0x40b15f MOV	0x78(%RBX),%R9

  (80) 0x40b163 INC	%R15D

  (80) 0x40b166 CMP	%R15D,(%R9,%R14,1)

  (80) 0x40b16a JG	40b13e

(79) 0x40b16c INC	%R12

(79) 0x40b16f CMP	%R12D,0xc(%RBX)

(79) 0x40b173 JG	40b0f0

0x40b179 ADD	$0x18,%RSP

0x40b17d POP	%RBX

0x40b17e POP	%R12

0x40b180 POP	%R13

0x40b182 POP	%R14

0x40b184 POP	%R15

0x40b186 POP	%RBP

0x40b187 RET

0x40b188 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►85.83+	redistributeAtoms	timestep.c:148	exec
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
►13.49+	redistributeAtoms	timestep.c:148	exec
○	timestep	timestep.c:47	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	linkCells.c:288-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:288-304,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.38 to 0.22 cycles (15.11x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	34
nb uops	27
loop length	118
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.33	1.33	1.33	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	1.33
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.38 cycles. At this rate:

3% of peak load performance is reached (8.30 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.38 to 1.33 cycles (2.53x speedup).

ASM code

In the binary file, the address of the function is: 40b090

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD 0xc(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JGE 40b0d2 <updateLinkCells+0x42>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 40b179 <updateLinkCells+0xe9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	linkCells.c:288-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:288-304,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	34
nb uops	27
loop length	118
used x86 registers	12
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.33	1.33	1.33	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	1.33
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.38 cycles. At this rate:

3% of peak load performance is reached (8.30 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40b090

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD 0xc(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JGE 40b0d2 <updateLinkCells+0x42>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 40b179 <updateLinkCells+0xe9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.08	0.02
▼Loop 79 - linkCells.c:291-301 - exec–	0.01	0.05
○Loop 80 - linkCells.c:295-301 - exec	0.07	0.50
○Loop 81 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code