OV - exec - Function computeVcm._omp

	Function: computeVcm._omp_fn.0	Module: exec	Source: initAtoms.c:218-228	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 218 - 228

--------------------------------------------------------------------------------

218:    #pragma omp parallel for reduction(+:v0) reduction(+:v1) reduction(+:v2) reduction(+:v3)

219:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

220:    {

221:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

222:       {

223:          v0 += s->atoms->p[iOff][0];

224:          v1 += s->atoms->p[iOff][1];

225:          v2 += s->atoms->p[iOff][2];

226:

227:          int iSpecies = s->atoms->iSpecies[iOff];

228:          v3 += s->species[iSpecies].mass;

0x409080 PUSH	%RBP

0x409081 MOV	%RSP,%RBP

0x409084 PUSH	%R14

0x409086 PUSH	%R13

0x409088 PUSH	%R12

0x40908a PUSH	%RBX

0x40908b MOV	%RDI,%RBX

0x40908e SUB	$0x20,%RSP

0x409092 MOV	(%RDI),%R12

0x409095 CALL	403060 <omp_get_num_threads@plt>

0x40909a MOV	%EAX,%R13D

0x40909d CALL	403160 <omp_get_thread_num@plt>

0x4090a2 MOV	%EAX,%ECX

0x4090a4 MOV	0x18(%R12),%R14

0x4090a9 MOV	0xc(%R14),%EAX

0x4090ad CLTD

0x4090ae IDIV	%R13D

0x4090b1 CMP	%EDX,%ECX

0x4090b3 JL	4092f2

0x4090b9 IMUL	%EAX,%ECX

0x4090bc ADD	%ECX,%EDX

0x4090be LEA	(%RAX,%RDX,1),%ESI

0x4090c1 CMP	%ESI,%EDX

0x4090c3 JGE	4092e0

0x4090c9 MOV	0x78(%R14),%RDI

0x4090cd MOVSXD	%EDX,%R9

0x4090d0 MOV	%EAX,%R10D

0x4090d3 VXORPD	%XMM0,%XMM0,%XMM0

0x4090d7 ADD	%R9,%R10

0x4090da LEA	(%R9,%R9,2),%R14

0x4090de MOV	%R9,%R13

0x4090e1 VMOVAPD	%XMM0,%XMM1

0x4090e5 LEA	(%R10,%R10,2),%RSI

0x4090e9 VMOVAPD	%XMM0,%XMM2

0x4090ed VMOVAPD	%XMM0,%XMM3

0x4090f1 SAL	$0x9,%R14

0x4090f5 SAL	$0x6,%R13

0x4090f9 SAL	$0x9,%RSI

0x4090fd LEA	(%RDI,%R9,4),%R8

0x409101 NOPW	%CS:(%RAX,%RAX,1)

0x40910c NOPL	(%RAX)

(62) 0x409110 MOVSXD	(%R8),%RCX

(62) 0x409113 TEST	%ECX,%ECX

(62) 0x409115 JLE	409260

(62) 0x40911b MOV	0x20(%R12),%RAX

(62) 0x409120 ADD	%R13,%RCX

(62) 0x409123 MOVSXD	%R13D,%RDX

(62) 0x409126 MOV	0x28(%R12),%R9

(62) 0x40912b MOV	0x10(%RAX),%R11

(62) 0x40912f MOV	0x20(%RAX),%RAX

(62) 0x409133 LEA	(%R11,%RCX,4),%R10

(62) 0x409137 LEA	(%R11,%RDX,4),%RDI

(62) 0x40913b ADD	%R14,%RAX

(62) 0x40913e MOV	%R10,%RCX

(62) 0x409141 SUB	%RDI,%RCX

(62) 0x409144 SUB	$0x4,%RCX

(62) 0x409148 SHR	$0x2,%RCX

(62) 0x40914c INC	%RCX

(62) 0x40914f AND	$0x3,%ECX

(62) 0x409152 JE	4091d9

(62) 0x409158 CMP	$0x1,%RCX

(62) 0x40915c JE	4091ac

(62) 0x40915e CMP	$0x2,%RCX

(62) 0x409162 JE	409188

(62) 0x409164 MOVSXD	(%RDI),%R11

(62) 0x409167 VADDSD	(%RAX),%XMM3,%XMM3

(62) 0x40916b VADDSD	0x8(%RAX),%XMM2,%XMM2

(62) 0x409170 VADDSD	0x10(%RAX),%XMM1,%XMM1

(62) 0x409175 ADD	$0x4,%RDI

(62) 0x409179 ADD	$0x18,%RAX

(62) 0x40917d SAL	$0x4,%R11

(62) 0x409181 VADDSD	0x8(%R9,%R11,1),%XMM0,%XMM0

(62) 0x409188 MOVSXD	(%RDI),%RDX

(62) 0x40918b VADDSD	(%RAX),%XMM3,%XMM3

(62) 0x40918f VADDSD	0x8(%RAX),%XMM2,%XMM2

(62) 0x409194 VADDSD	0x10(%RAX),%XMM1,%XMM1

(62) 0x409199 ADD	$0x4,%RDI

(62) 0x40919d ADD	$0x18,%RAX

(62) 0x4091a1 SAL	$0x4,%RDX

(62) 0x4091a5 VADDSD	0x8(%R9,%RDX,1),%XMM0,%XMM0

(62) 0x4091ac MOVSXD	(%RDI),%RCX

(62) 0x4091af ADD	$0x4,%RDI

(62) 0x4091b3 VADDSD	(%RAX),%XMM3,%XMM3

(62) 0x4091b7 VADDSD	0x8(%RAX),%XMM2,%XMM2

(62) 0x4091bc VADDSD	0x10(%RAX),%XMM1,%XMM1

(62) 0x4091c1 ADD	$0x18,%RAX

(62) 0x4091c5 SAL	$0x4,%RCX

(62) 0x4091c9 VADDSD	0x8(%R9,%RCX,1),%XMM0,%XMM0

(62) 0x4091d0 CMP	%RDI,%R10

(62) 0x4091d3 JE	409260

  (63) 0x4091d9 MOVSXD	(%RDI),%R11

  (63) 0x4091dc MOVSXD	0x4(%RDI),%RDX

  (63) 0x4091e0 MOVSXD	0x8(%RDI),%RCX

  (63) 0x4091e4 ADD	$0x10,%RDI

  (63) 0x4091e8 VADDSD	(%RAX),%XMM3,%XMM4

  (63) 0x4091ec VADDSD	0x8(%RAX),%XMM2,%XMM5

  (63) 0x4091f1 VADDSD	0x10(%RAX),%XMM1,%XMM6

  (63) 0x4091f6 VADDSD	0x18(%RAX),%XMM4,%XMM8

  (63) 0x4091fb VADDSD	0x20(%RAX),%XMM5,%XMM9

  (63) 0x409200 VADDSD	0x28(%RAX),%XMM6,%XMM10

  (63) 0x409205 VADDSD	0x30(%RAX),%XMM8,%XMM12

  (63) 0x40920a VADDSD	0x38(%RAX),%XMM9,%XMM13

  (63) 0x40920f VADDSD	0x40(%RAX),%XMM10,%XMM14

  (63) 0x409214 VADDSD	0x48(%RAX),%XMM12,%XMM3

  (63) 0x409219 VADDSD	0x50(%RAX),%XMM13,%XMM2

  (63) 0x40921e VADDSD	0x58(%RAX),%XMM14,%XMM1

  (63) 0x409223 ADD	$0x60,%RAX

  (63) 0x409227 SAL	$0x4,%R11

  (63) 0x40922b VADDSD	0x8(%R9,%R11,1),%XMM0,%XMM7

  (63) 0x409232 MOVSXD	-0x4(%RDI),%R11

  (63) 0x409236 SAL	$0x4,%RDX

  (63) 0x40923a SAL	$0x4,%RCX

  (63) 0x40923e VADDSD	0x8(%R9,%RDX,1),%XMM7,%XMM11

  (63) 0x409245 SAL	$0x4,%R11

  (63) 0x409249 VADDSD	0x8(%R9,%RCX,1),%XMM11,%XMM15

  (63) 0x409250 VADDSD	0x8(%R9,%R11,1),%XMM15,%XMM0

  (63) 0x409257 CMP	%RDI,%R10

  (63) 0x40925a JNE	4091d9

(62) 0x409260 ADD	$0x600,%R14

(62) 0x409267 ADD	$0x4,%R8

(62) 0x40926b ADD	$0x40,%R13

(62) 0x40926f CMP	%RSI,%R14

(62) 0x409272 JNE	409110

0x409278 VMOVSD	%XMM0,-0x40(%RBP)

0x40927d VMOVSD	%XMM1,-0x38(%RBP)

0x409282 VMOVSD	%XMM2,-0x30(%RBP)

0x409287 VMOVSD	%XMM3,-0x28(%RBP)

0x40928c CALL	4031c0 <GOMP_atomic_start@plt>

0x409291 VMOVSD	-0x28(%RBP),%XMM3

0x409296 VMOVSD	-0x30(%RBP),%XMM1

0x40929b VADDSD	0x20(%RBX),%XMM3,%XMM2

0x4092a0 VADDSD	0x18(%RBX),%XMM1,%XMM0

0x4092a5 VMOVSD	%XMM2,0x20(%RBX)

0x4092aa VMOVSD	%XMM0,0x18(%RBX)

0x4092af VMOVSD	-0x38(%RBP),%XMM4

0x4092b4 VMOVSD	-0x40(%RBP),%XMM6

0x4092b9 VADDSD	0x10(%RBX),%XMM4,%XMM5

0x4092be VADDSD	0x8(%RBX),%XMM6,%XMM7

0x4092c3 VMOVSD	%XMM5,0x10(%RBX)

0x4092c8 VMOVSD	%XMM7,0x8(%RBX)

0x4092cd ADD	$0x20,%RSP

0x4092d1 POP	%RBX

0x4092d2 POP	%R12

0x4092d4 POP	%R13

0x4092d6 POP	%R14

0x4092d8 POP	%RBP

0x4092d9 JMP	403190

0x4092de XCHG	%AX,%AX

0x4092e0 VXORPD	%XMM0,%XMM0,%XMM0

0x4092e4 VMOVAPD	%XMM0,%XMM1

0x4092e8 VMOVAPD	%XMM0,%XMM2

0x4092ec VMOVAPD	%XMM0,%XMM3

0x4092f0 JMP	409278

0x4092f2 INC	%EAX

0x4092f4 XOR	%EDX,%EDX

0x4092f6 JMP	4090b9

0x4092fb NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►98.30+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.70+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	setVcm	initAtoms.c:218	exec
○	setTemperature	initAtoms.c:170	exec
○	main	CoMD.c:200	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:468	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	initAtoms.c:218-228
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218-228.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 4.25 cycles (2.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.25 to 0.73 cycles (12.63x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_atomic_start@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:221
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 92 bytes (11 double precision FP elements). The binary function is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	75
nb uops	74
loop length	280
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.25 cycles
front end	9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	5.75	5.75	5.75	5.75	0.00	0.00	2.00	2.00	4.00	4.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	5.75	5.75	5.75	5.75	0.00	0.00	2.00	2.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	9.25
Dispatch	5.75
DIV/SQRT	6.00
Overall L1	9.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	22%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	12%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.25 cycles. At this rate:

3% of peak load performance is reached (9.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 409080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x18(%R12),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 4092f2 <computeVcm._omp_fn.0+0x272>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 4092e0 <computeVcm._omp_fn.0+0x260>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R9,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R9,%R9,2),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%R10,%R10,2),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVAPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SAL $0x9,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x6,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x9,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RDI,%R9,4),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4031c0 <GOMP_atomic_start@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x28(%RBP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x30(%RBP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x20(%RBX),%XMM3,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD 0x18(%RBX),%XMM1,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM2,0x20(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x18(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x38(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x40(%RBP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x10(%RBX),%XMM4,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD 0x8(%RBX),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM5,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM7,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403190 <GOMP_atomic_end@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 409278 <computeVcm._omp_fn.0+0x1f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4090b9 <computeVcm._omp_fn.0+0x39>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_10

Source file and lines	initAtoms.c:218-228
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218-228.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 4.25 cycles (2.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

GOMP_atomic_start@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:221
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 92 bytes (11 double precision FP elements). The binary function is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	75
nb uops	74
loop length	280
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.25 cycles
front end	9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	5.75	5.75	5.75	5.75	0.00	0.00	2.00	2.00	4.00	4.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	5.75	5.75	5.75	5.75	0.00	0.00	2.00	2.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	9.25
Dispatch	5.75
DIV/SQRT	6.00
Overall L1	9.25

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	22%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	12%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.25 cycles. At this rate:

3% of peak load performance is reached (9.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 409080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x18(%R12),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 4092f2 <computeVcm._omp_fn.0+0x272>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 4092e0 <computeVcm._omp_fn.0+0x260>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R9,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R9,%R9,2),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (%R10,%R10,2),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVAPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SAL $0x9,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x6,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x9,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RDI,%R9,4),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM3,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4031c0 <GOMP_atomic_start@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
VMOVSD -0x28(%RBP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x30(%RBP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x20(%RBX),%XMM3,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD 0x18(%RBX),%XMM1,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM2,0x20(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM0,0x18(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x38(%RBP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x40(%RBP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD 0x10(%RBX),%XMM4,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD 0x8(%RBX),%XMM6,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM5,0x10(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM7,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403190 <GOMP_atomic_end@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 409278 <computeVcm._omp_fn.0+0x1f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4090b9 <computeVcm._omp_fn.0+0x39>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼computeVcm._omp_fn.0–	0.02	0.01
▼Loop 62 - initAtoms.c:221-228 - exec–	0.00	0.00
○Loop 63 - initAtoms.c:221-228 - exec	0.02	0.00

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