OV - exec - Function sortAtomsInCell

	Function: sortAtomsInCell	Module: exec	Source: haloExchange.c:614-645	Coverage (incl. loops): 0.98% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 614 - 645

--------------------------------------------------------------------------------

614: {

615:    int nAtoms = boxes->nAtoms[iBox];

616:

617:    AtomMsg tmp[nAtoms];

618:

619:    int begin = iBox*MAXATOMS;

620:    int end = begin + nAtoms;

621:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

622:    {

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

629:       tmp[iTmp].py =   atoms->p[ii][1];

630:       tmp[iTmp].pz =   atoms->p[ii][2];

631:    }

632:    qsort(&tmp, nAtoms, sizeof(AtomMsg), sortAtomsById);

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

643:    }

644:

645: }

0x40cb20 PUSH	%RBP

0x40cb21 MOV	%RSP,%RBP

0x40cb24 PUSH	%R15

0x40cb26 PUSH	%R14

0x40cb28 PUSH	%R12

0x40cb2a PUSH	%RBX

0x40cb2b MOV	0x78(%RSI),%RAX

0x40cb2f MOVSXD	%EDX,%RCX

0x40cb32 MOV	(%RAX,%RCX,4),%ESI

0x40cb35 IMUL	$0x38,%RSI,%RAX

0x40cb39 ADD	$0xf,%RAX

0x40cb3d AND	$-0x10,%RAX

0x40cb41 MOV	%RSP,%RBX

0x40cb44 SUB	%RAX,%RBX

0x40cb47 MOV	%RBX,%RSP

0x40cb4a TEST	%ESI,%ESI

0x40cb4c JLE	40cc57

0x40cb52 MOV	%RDI,%R14

0x40cb55 SAL	$0x6,%EDX

0x40cb58 LEA	(%RSI,%RDX,1),%R9D

0x40cb5c MOV	0x8(%RDI),%RAX

0x40cb60 MOV	0x10(%RDI),%RCX

0x40cb64 MOV	0x18(%RDI),%RDI

0x40cb68 MOV	0x20(%R14),%R8

0x40cb6c MOVSXD	%EDX,%R15

0x40cb6f MOVSXD	%R9D,%R12

0x40cb72 LEA	(%R15,%R15,1),%RDX

0x40cb76 LEA	(%RDX,%RDX,2),%RDX

0x40cb7a ADD	$0x4,%RDX

0x40cb7e MOV	%RBX,%R9

0x40cb81 MOV	%R15,%R10

0x40cb84 NOPW	%CS:(%RAX,%RAX,1)

(87) 0x40cb90 MOV	(%RAX,%R10,4),%R11D

(87) 0x40cb94 MOV	%R11D,(%R9)

(87) 0x40cb97 MOV	(%RCX,%R10,4),%R11D

(87) 0x40cb9b MOV	%R11D,0x4(%R9)

(87) 0x40cb9f MOVUPS	-0x10(%RDI,%RDX,4),%XMM0

(87) 0x40cba4 MOVUPS	%XMM0,0x8(%R9)

(87) 0x40cba9 MOVSD	(%RDI,%RDX,4),%XMM0

(87) 0x40cbae MOVSD	%XMM0,0x18(%R9)

(87) 0x40cbb4 MOVUPS	-0x10(%R8,%RDX,4),%XMM0

(87) 0x40cbba MOVUPS	%XMM0,0x20(%R9)

(87) 0x40cbbf MOVSD	(%R8,%RDX,4),%XMM0

(87) 0x40cbc5 MOVSD	%XMM0,0x30(%R9)

(87) 0x40cbcb INC	%R10

(87) 0x40cbce ADD	$0x6,%RDX

(87) 0x40cbd2 ADD	$0x38,%R9

(87) 0x40cbd6 CMP	%R12,%R10

(87) 0x40cbd9 JL	40cb90

0x40cbdb MOV	$0x38,%EDX

0x40cbe0 MOV	$0x40cc80,%ECX

0x40cbe5 MOV	%RBX,%RDI

0x40cbe8 CALL	405380 <qsort@plt>

0x40cbed MOV	0x8(%R14),%RAX

0x40cbf1 MOV	0x10(%R14),%RCX

0x40cbf5 MOV	0x18(%R14),%RDX

0x40cbf9 MOV	0x20(%R14),%RSI

0x40cbfd LEA	(%R15,%R15,2),%RDI

0x40cc01 LEA	0x10(,%RDI,8),%RDI

0x40cc09 NOPL	(%RAX)

(88) 0x40cc10 MOV	(%RBX),%R8D

(88) 0x40cc13 MOV	%R8D,(%RAX,%R15,4)

(88) 0x40cc17 MOV	0x4(%RBX),%R8D

(88) 0x40cc1b MOV	%R8D,(%RCX,%R15,4)

(88) 0x40cc1f MOVUPS	0x8(%RBX),%XMM0

(88) 0x40cc23 MOVUPS	%XMM0,-0x10(%RDX,%RDI,1)

(88) 0x40cc28 MOVSD	0x18(%RBX),%XMM0

(88) 0x40cc2d MOVSD	%XMM0,(%RDX,%RDI,1)

(88) 0x40cc32 MOVUPS	0x20(%RBX),%XMM0

(88) 0x40cc36 MOVUPS	%XMM0,-0x10(%RSI,%RDI,1)

(88) 0x40cc3b MOVSD	0x30(%RBX),%XMM0

(88) 0x40cc40 MOVSD	%XMM0,(%RSI,%RDI,1)

(88) 0x40cc45 INC	%R15

(88) 0x40cc48 ADD	$0x18,%RDI

(88) 0x40cc4c ADD	$0x38,%RBX

(88) 0x40cc50 CMP	%R12,%R15

(88) 0x40cc53 JL	40cc10

0x40cc55 JMP	40cc6c

0x40cc57 MOVSXD	%ESI,%RSI

0x40cc5a MOV	$0x38,%EDX

0x40cc5f MOV	$0x40cc80,%ECX

0x40cc64 MOV	%RBX,%RDI

0x40cc67 CALL	405380 <qsort@plt>

0x40cc6c LEA	-0x20(%RBP),%RSP

0x40cc70 POP	%RBX

0x40cc71 POP	%R12

0x40cc73 POP	%R14

0x40cc75 POP	%R15

0x40cc77 POP	%RBP

0x40cc78 RET

0x40cc79 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►12.54+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►12.34+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►12.02+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.84+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.84+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.76+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.75+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.69+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_3

Source file and lines	haloExchange.c:614-645
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:614-645.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 7.00 to 0.45 cycles (15.46x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qsort@plt: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes.

General properties

nb instructions	57
nb uops	56
loop length	208
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Dispatch	4.33
Overall L1	7.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

4% of peak load performance is reached (10.86 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 4.33 cycles (1.62x speedup).

ASM code

In the binary file, the address of the function is: 40cb20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x78(%RSI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %EDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RAX,%RCX,4),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL $0x38,%RSI,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD $0xf,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
AND $-0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 40cc57 <sortAtomsInCell.A+0x137>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RSI,%RDX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x8(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSXD %EDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %R9D,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%R15,%R15,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RDX,%RDX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x38,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x40cc80,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405380 <qsort@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x8(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%R15,%R15,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x10(,%RDI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 40cc6c <sortAtomsInCell.A+0x14c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOVSXD %ESI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x38,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x40cc80,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405380 <qsort@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0x20(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_3

Source file and lines	haloExchange.c:614-645
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:614-645.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

qsort@plt: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:632

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes.

General properties

nb instructions	57
nb uops	56
loop length	208
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.00 cycles
front end	7.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.00
Dispatch	4.33
Overall L1	7.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.00 cycles. At this rate:

4% of peak load performance is reached (10.86 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40cb20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV 0x78(%RSI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %EDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RAX,%RCX,4),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL $0x38,%RSI,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD $0xf,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
AND $-0x10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RBX,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
TEST %ESI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 40cc57 <sortAtomsInCell.A+0x137>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RSI,%RDX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV 0x8(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%R14),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSXD %EDX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %R9D,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%R15,%R15,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RDX,%RDX,2),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x38,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x40cc80,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405380 <qsort@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x8(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA (%R15,%R15,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x10(,%RDI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 40cc6c <sortAtomsInCell.A+0x14c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOVSXD %ESI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x38,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x40cc80,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 405380 <qsort@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0x20(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼sortAtomsInCell–	0.98	0.29
○Loop 87 - haloExchange.c:621-630 - exec	0.95	0.27
○Loop 88 - haloExchange.c:633-642 - exec	0.03	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code