OV - exec - Function mkSeed

	Function: mkSeed	Module: exec	Source: random.c:46-74 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 46 - 74

--------------------------------------------------------------------------------

46:    *seed %= UINT64_C(2305843009213693951);

[...]

66: {

67:    uint32_t s1 = id * UINT32_C(2654435761);

68:    uint32_t s2 = (id+callSite) * UINT32_C(2654435761);

69:

70:    uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2;

71:    for (unsigned jj=0; jj<10; ++jj)

72:       lcg61(&iSeed);

73:

74:    return iSeed;

0x419db0 PUSH	%RBP

0x419db1 MOV	%RSP,%RBP

0x419db4 IMUL	$-0x61c8864f,%EDI,%EAX

0x419dba ADD	%EDI,%ESI

0x419dbc IMUL	$-0x61c8864f,%ESI,%ESI

0x419dc2 SAL	$0x20,%RAX

0x419dc6 OR	%RAX,%RSI

0x419dc9 MOV	$0x613606df9756715,%RDI

0x419dd3 IMUL	%RDI,%RSI

0x419dd7 MOV	$0x9,%R8D

0x419ddd MOV	%RSI,%RAX

0x419de0 MUL	%R8

0x419de3 MOV	%RSI,%RCX

0x419de6 SUB	%RDX,%RCX

0x419de9 SHR	$0x1,%RCX

0x419dec ADD	%RDX,%RCX

0x419def SHR	$0x3c,%RCX

0x419df3 MOV	%RCX,%RAX

0x419df6 SAL	$0x3d,%RAX

0x419dfa SUB	%RAX,%RCX

0x419dfd ADD	%RSI,%RCX

0x419e00 IMUL	%RDI,%RCX

0x419e04 MOV	%RCX,%RAX

0x419e07 MUL	%R8

0x419e0a MOV	%RCX,%RSI

0x419e0d SUB	%RDX,%RSI

0x419e10 SHR	$0x1,%RSI

0x419e13 ADD	%RDX,%RSI

0x419e16 SHR	$0x3c,%RSI

0x419e1a MOV	%RSI,%RAX

0x419e1d SAL	$0x3d,%RAX

0x419e21 SUB	%RAX,%RSI

0x419e24 ADD	%RCX,%RSI

0x419e27 IMUL	%RDI,%RSI

0x419e2b MOV	%RSI,%RAX

0x419e2e MUL	%R8

0x419e31 MOV	%RSI,%RCX

0x419e34 SUB	%RDX,%RCX

0x419e37 SHR	$0x1,%RCX

0x419e3a ADD	%RDX,%RCX

0x419e3d SHR	$0x3c,%RCX

0x419e41 MOV	%RCX,%RAX

0x419e44 SAL	$0x3d,%RAX

0x419e48 SUB	%RAX,%RCX

0x419e4b ADD	%RSI,%RCX

0x419e4e IMUL	%RDI,%RCX

0x419e52 MOV	%RCX,%RAX

0x419e55 MUL	%R8

0x419e58 MOV	%RCX,%RSI

0x419e5b SUB	%RDX,%RSI

0x419e5e SHR	$0x1,%RSI

0x419e61 ADD	%RDX,%RSI

0x419e64 SHR	$0x3c,%RSI

0x419e68 MOV	%RSI,%RAX

0x419e6b SAL	$0x3d,%RAX

0x419e6f SUB	%RAX,%RSI

0x419e72 ADD	%RCX,%RSI

0x419e75 IMUL	%RDI,%RSI

0x419e79 MOV	%RSI,%RAX

0x419e7c MUL	%R8

0x419e7f MOV	%RSI,%RCX

0x419e82 SUB	%RDX,%RCX

0x419e85 SHR	$0x1,%RCX

0x419e88 ADD	%RDX,%RCX

0x419e8b SHR	$0x3c,%RCX

0x419e8f MOV	%RCX,%RAX

0x419e92 SAL	$0x3d,%RAX

0x419e96 SUB	%RAX,%RCX

0x419e99 ADD	%RSI,%RCX

0x419e9c IMUL	%RDI,%RCX

0x419ea0 MOV	%RCX,%RAX

0x419ea3 MUL	%R8

0x419ea6 MOV	%RCX,%RSI

0x419ea9 SUB	%RDX,%RSI

0x419eac SHR	$0x1,%RSI

0x419eaf ADD	%RDX,%RSI

0x419eb2 SHR	$0x3c,%RSI

0x419eb6 MOV	%RSI,%RAX

0x419eb9 SAL	$0x3d,%RAX

0x419ebd SUB	%RAX,%RSI

0x419ec0 ADD	%RCX,%RSI

0x419ec3 IMUL	%RDI,%RSI

0x419ec7 MOV	%RSI,%RAX

0x419eca MUL	%R8

0x419ecd MOV	%RSI,%RCX

0x419ed0 SUB	%RDX,%RCX

0x419ed3 SHR	$0x1,%RCX

0x419ed6 ADD	%RDX,%RCX

0x419ed9 SHR	$0x3c,%RCX

0x419edd MOV	%RCX,%RAX

0x419ee0 SAL	$0x3d,%RAX

0x419ee4 SUB	%RAX,%RCX

0x419ee7 ADD	%RSI,%RCX

0x419eea IMUL	%RDI,%RCX

0x419eee MOV	%RCX,%RAX

0x419ef1 MUL	%R8

0x419ef4 MOV	%RCX,%RSI

0x419ef7 SUB	%RDX,%RSI

0x419efa SHR	$0x1,%RSI

0x419efd ADD	%RDX,%RSI

0x419f00 SHR	$0x3c,%RSI

0x419f04 MOV	%RSI,%RAX

0x419f07 SAL	$0x3d,%RAX

0x419f0b SUB	%RAX,%RSI

0x419f0e ADD	%RCX,%RSI

0x419f11 IMUL	%RDI,%RSI

0x419f15 MOV	%RSI,%RAX

0x419f18 MUL	%R8

0x419f1b MOV	%RSI,%RCX

0x419f1e SUB	%RDX,%RCX

0x419f21 SHR	$0x1,%RCX

0x419f24 ADD	%RDX,%RCX

0x419f27 SHR	$0x3c,%RCX

0x419f2b MOV	%RCX,%RAX

0x419f2e SAL	$0x3d,%RAX

0x419f32 SUB	%RAX,%RCX

0x419f35 ADD	%RSI,%RCX

0x419f38 IMUL	%RDI,%RCX

0x419f3c MOV	%RCX,%RAX

0x419f3f MUL	%R8

0x419f42 MOV	%RCX,%RAX

0x419f45 SUB	%RDX,%RAX

0x419f48 SHR	$0x1,%RAX

0x419f4b ADD	%RDX,%RAX

0x419f4e SHR	$0x3c,%RAX

0x419f52 MOV	%RAX,%RDX

0x419f55 SAL	$0x3d,%RDX

0x419f59 SUB	%RDX,%RAX

0x419f5c ADD	%RCX,%RAX

0x419f5f POP	%RBP

0x419f60 RET

0x419f61 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►68.36+	randomDisplacements.extracted	initAtoms.c:199	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►28.36+	setTemperature.extracted.30	initAtoms.c:159	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.55+	randomDisplacements.extracted	initAtoms.c:199	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	randomDisplacements	initAtoms.c:205	exec
○	main	CoMD.c:202	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_3

Source file and lines	random.c:46-74
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46,66-74.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.00 to 1.66 cycles (10.87x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	131
nb uops	141
loop length	433
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.63 cycles
front end	17.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.63
Dispatch	18.00
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 419db0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
IMUL $-0x61c8864f,%EDI,%EAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
ADD %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
IMUL $-0x61c8864f,%ESI,%ESI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
SAL $0x20,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
OR %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
MOV $0x613606df9756715,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV $0x9,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
POP %RBP	1	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_3

Source file and lines	random.c:46-74
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46,66-74.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	131
nb uops	141
loop length	433
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.63 cycles
front end	17.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.63
Dispatch	18.00
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 419db0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
IMUL $-0x61c8864f,%EDI,%EAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
ADD %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
IMUL $-0x61c8864f,%ESI,%ESI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
SAL $0x20,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
OR %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
MOV $0x613606df9756715,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV $0x9,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
ADD %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RDI,%RSI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RSI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RDI,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MUL %R8	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
POP %RBP	1	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	1	0.50	N/A

Name	Coverage (%)	Time (s)
○mkSeed	0.02	0.01

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Vectorization

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Matching between your function (in the source code) and the binary function

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Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code