OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.39% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

[...]

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x411930 PUSH	%RBP

0x411931 MOV	%RSP,%RBP

0x411934 PUSH	%R15

0x411936 PUSH	%R14

0x411938 PUSH	%R13

0x41193a PUSH	%R12

0x41193c PUSH	%RBX

0x41193d SUB	$0x68,%RSP

0x411941 MOV	%RDI,%R14

0x411944 MOV	0xc(%RDI),%R8D

0x411948 CMP	0x14(%RDI),%R8D

0x41194c JGE	411977

0x41194e MOVSXD	%R8D,%RAX

0x411951 MOV	0x78(%R14),%RCX

0x411955 NOPW	%CS:(%RAX,%RAX,1)

(140) 0x411960 MOVL	$0,(%RCX,%RAX,4)

(140) 0x411967 INC	%RAX

(140) 0x41196a MOVSXD	0x14(%R14),%RDX

(140) 0x41196e CMP	%RDX,%RAX

(140) 0x411971 JL	411960

0x411973 MOV	0xc(%R14),%R8D

0x411977 TEST	%R8D,%R8D

0x41197a JLE	411d53

0x411980 MOV	0x78(%R14),%RDX

0x411984 XOR	%R12D,%R12D

0x411987 MOV	%RSI,-0x48(%RBP)

0x41198b JMP	41199f

0x41198d NOPL	(%RAX)

(138) 0x411990 INC	%R12

(138) 0x411993 MOVSXD	%R8D,%RAX

(138) 0x411996 CMP	%RAX,%R12

(138) 0x411999 JGE	411d53

(138) 0x41199f CMPL	$0,(%RDX,%R12,4)

(138) 0x4119a4 JLE	411990

(138) 0x4119a6 MOVSXD	%R12D,%RAX

(138) 0x4119a9 SAL	$0x6,%RAX

(138) 0x4119ad MOV	%RAX,-0x50(%RBP)

(138) 0x4119b1 XOR	%ECX,%ECX

(138) 0x4119b3 MOV	%R8D,%EDI

(138) 0x4119b6 JMP	4119d4

0x4119b8 NOPL	(%RAX,%RAX,1)

  (139) 0x4119c0 MOV	-0x40(%RBP),%RCX

  (139) 0x4119c4 INC	%ECX

  (139) 0x4119c6 MOV	-0x48(%RBP),%RSI

  (139) 0x4119ca MOV	0x78(%R14),%RDX

  (139) 0x4119ce CMP	(%RDX,%R12,4),%ECX

  (139) 0x4119d2 JGE	411990

  (139) 0x4119d4 MOV	%EDI,-0x2c(%RBP)

  (139) 0x4119d7 MOV	%RDX,-0x68(%RBP)

  (139) 0x4119db MOV	%R8,-0x38(%RBP)

  (139) 0x4119df MOV	0x18(%RSI),%R15

  (139) 0x4119e3 MOV	-0x50(%RBP),%RAX

  (139) 0x4119e7 MOV	%RCX,-0x40(%RBP)

  (139) 0x4119eb ADD	%ECX,%EAX

  (139) 0x4119ed CLTQ

  (139) 0x4119ef MOV	%RAX,-0x70(%RBP)

  (139) 0x4119f3 LEA	(%RAX,%RAX,2),%RBX

  (139) 0x4119f7 MOVSD	(%R15,%RBX,8),%XMM0

  (139) 0x4119fd MOVSD	%XMM0,-0x78(%RBP)

  (139) 0x411a02 MOVSD	0x8(%R15,%RBX,8),%XMM0

  (139) 0x411a09 MOVSD	%XMM0,-0x58(%RBP)

  (139) 0x411a0e SUBSD	0x20(%R14),%XMM0

  (139) 0x411a14 MULSD	0x68(%R14),%XMM0

  (139) 0x411a1a CALL	41b320 <floor>

  (139) 0x411a1f MOVSD	%XMM0,-0x80(%RBP)

  (139) 0x411a24 MOVSD	0x10(%R15,%RBX,8),%XMM0

  (139) 0x411a2b MOVSD	%XMM0,-0x88(%RBP)

  (139) 0x411a33 SUBSD	0x28(%R14),%XMM0

  (139) 0x411a39 MULSD	0x70(%R14),%XMM0

  (139) 0x411a3f CALL	41b320 <floor>

  (139) 0x411a44 MOVSD	-0x78(%RBP),%XMM1

  (139) 0x411a49 UCOMISD	0x30(%R14),%XMM1

  (139) 0x411a4f MOV	(%R14),%R13D

  (139) 0x411a52 MOV	%R13D,%ECX

  (139) 0x411a55 JAE	411a83

  (139) 0x411a57 MOVSD	%XMM0,-0x60(%RBP)

  (139) 0x411a5c SUBSD	0x18(%R14),%XMM1

  (139) 0x411a62 MULSD	0x60(%R14),%XMM1

  (139) 0x411a68 MOVAPD	%XMM1,%XMM0

  (139) 0x411a6c CALL	41b320 <floor>

  (139) 0x411a71 CVTTSD2SI	%XMM0,%ECX

  (139) 0x411a75 CMP	%ECX,%R13D

  (139) 0x411a78 JNE	411a7e

  (139) 0x411a7a LEA	-0x1(%R13),%ECX

  (139) 0x411a7e MOVSD	-0x60(%RBP),%XMM0

  (139) 0x411a83 CVTTSD2SI	-0x80(%RBP),%EAX

  (139) 0x411a88 MOVSD	0x38(%R14),%XMM3

  (139) 0x411a8e MOV	0x4(%R14),%EDX

  (139) 0x411a92 MOV	0x8(%R14),%ESI

  (139) 0x411a96 CMP	%EAX,%EDX

  (139) 0x411a98 JNE	411a9d

  (139) 0x411a9a LEA	-0x1(%RDX),%EAX

  (139) 0x411a9d MOVSD	-0x58(%RBP),%XMM1

  (139) 0x411aa2 UCOMISD	%XMM3,%XMM1

  (139) 0x411aa6 MOV	%EAX,%R8D

  (139) 0x411aa9 CMOVAE	%EDX,%R8D

  (139) 0x411aad MOVSD	-0x88(%RBP),%XMM2

  (139) 0x411ab5 UCOMISD	0x40(%R14),%XMM2

  (139) 0x411abb JAE	411af0

  (139) 0x411abd CVTTSD2SI	%XMM0,%EDI

  (139) 0x411ac1 CMP	%EDI,%ESI

  (139) 0x411ac3 JNE	411ac8

  (139) 0x411ac5 LEA	-0x1(%RSI),%EDI

  (139) 0x411ac8 CMP	$-0x1,%EDI

  (139) 0x411acb JE	411b20

  (139) 0x411acd UCOMISD	%XMM3,%XMM1

  (139) 0x411ad1 JB	411b4e

  (139) 0x411ad3 IMUL	%ESI,%EDX

  (139) 0x411ad6 ADD	$0x2,%R13D

  (139) 0x411ada ADD	%ESI,%EDI

  (139) 0x411adc IMUL	%R13D,%EDI

  (139) 0x411ae0 LEA	(%RCX,%RDX,2),%EAX

  (139) 0x411ae3 ADD	%EDI,%EAX

  (139) 0x411ae5 MOV	-0x38(%RBP),%R8

  (139) 0x411ae9 JMP	411b87

0x411aee XCHG	%AX,%AX

  (139) 0x411af0 LEA	(%RSI,%RSI,1),%EAX

  (139) 0x411af3 IMUL	%EDX,%EAX

  (139) 0x411af6 ADD	$0x2,%R13D

  (139) 0x411afa LEA	(%R8,%RSI,2),%ESI

  (139) 0x411afe ADD	%ESI,%EDX

  (139) 0x411b00 ADD	$0x3,%EDX

  (139) 0x411b03 IMUL	%R13D,%EDX

  (139) 0x411b07 MOV	-0x2c(%RBP),%EDI

  (139) 0x411b0a ADD	%EDI,%ECX

  (139) 0x411b0c ADD	%EAX,%ECX

  (139) 0x411b0e LEA	(%RDX,%RCX,1),%EAX

  (139) 0x411b11 INC	%EAX

  (139) 0x411b13 MOV	-0x38(%RBP),%R8

  (139) 0x411b17 TEST	%EAX,%EAX

  (139) 0x411b19 JNS	411b97

0x411b1b JMP	411d3a

  (139) 0x411b20 LEA	(%RSI,%RSI,1),%EAX

  (139) 0x411b23 IMUL	%EAX,%EDX

  (139) 0x411b26 ADD	$0x2,%R13D

  (139) 0x411b2a LEA	(%R8,%RSI,2),%EAX

  (139) 0x411b2e INC	%EAX

  (139) 0x411b30 IMUL	%R13D,%EAX

  (139) 0x411b34 ADD	%EDX,%ECX

  (139) 0x411b36 ADD	%EAX,%ECX

  (139) 0x411b38 MOV	-0x38(%RBP),%R8

  (139) 0x411b3c LEA	(%R8,%RCX,1),%EAX

  (139) 0x411b40 INC	%EAX

  (139) 0x411b42 MOV	%R8D,%EDI

  (139) 0x411b45 TEST	%EAX,%EAX

  (139) 0x411b47 JNS	411b97

0x411b49 JMP	411d3a

  (139) 0x411b4e CMP	$-0x1,%EAX

  (139) 0x411b51 MOV	-0x38(%RBP),%R8

  (139) 0x411b55 JE	411b76

  (139) 0x411b57 CMP	%ECX,%R13D

  (139) 0x411b5a JNE	411d14

  (139) 0x411b60 ADD	%ESI,%EDI

  (139) 0x411b62 IMUL	%EDI,%EDX

  (139) 0x411b65 ADD	%R8D,%EAX

  (139) 0x411b68 ADD	%EDX,%EAX

  (139) 0x411b6a MOV	%R8D,%EDI

  (139) 0x411b6d TEST	%EAX,%EAX

  (139) 0x411b6f JNS	411b97

0x411b71 JMP	411d3a

  (139) 0x411b76 IMUL	%EDX,%ESI

  (139) 0x411b79 ADD	$0x2,%R13D

  (139) 0x411b7d IMUL	%EDI,%R13D

  (139) 0x411b81 LEA	(%RCX,%RSI,2),%EAX

  (139) 0x411b84 ADD	%R13D,%EAX

  (139) 0x411b87 ADD	%R8D,%EAX

  (139) 0x411b8a INC	%EAX

  (139) 0x411b8c MOV	%R8D,%EDI

  (139) 0x411b8f TEST	%EAX,%EAX

  (139) 0x411b91 JS	411d3a

  (139) 0x411b97 CMP	0x14(%R14),%EAX

  (139) 0x411b9b JGE	411d62

  (139) 0x411ba1 MOV	%EAX,%EDX

  (139) 0x411ba3 CMP	%RDX,%R12

  (139) 0x411ba6 JE	4119c0

  (139) 0x411bac LEA	(%R15,%RBX,8),%RCX

  (139) 0x411bb0 MOV	-0x68(%RBP),%RSI

  (139) 0x411bb4 MOVSXD	(%RSI,%RDX,4),%RDI

  (139) 0x411bb8 MOVSXD	%EAX,%R10

  (139) 0x411bbb SAL	$0x6,%R10

  (139) 0x411bbf ADD	%RDI,%R10

  (139) 0x411bc2 MOV	-0x48(%RBP),%RSI

  (139) 0x411bc6 MOV	0x8(%RSI),%RDI

  (139) 0x411bca MOV	-0x70(%RBP),%RBX

  (139) 0x411bce MOV	(%RDI,%RBX,4),%R8D

  (139) 0x411bd2 MOV	%R8D,(%RDI,%R10,4)

  (139) 0x411bd6 MOV	0x10(%RSI),%RDI

  (139) 0x411bda MOV	(%RDI,%RBX,4),%R8D

  (139) 0x411bde MOV	%R8D,(%RDI,%R10,4)

  (139) 0x411be2 LEA	(,%R10,8),%RDI

  (139) 0x411bea LEA	(%RDI,%RDI,2),%RDI

  (139) 0x411bee MOV	0x10(%RCX),%R8

  (139) 0x411bf2 MOV	%R8,0x10(%R15,%RDI,1)

  (139) 0x411bf7 MOVUPS	(%RCX),%XMM0

  (139) 0x411bfa MOVUPS	%XMM0,(%R15,%RDI,1)

  (139) 0x411bff MOV	0x20(%RSI),%R8

  (139) 0x411c03 LEA	(,%RBX,8),%RCX

  (139) 0x411c0b LEA	(%RCX,%RCX,2),%RCX

  (139) 0x411c0f MOV	0x10(%R8,%RCX,1),%R9

  (139) 0x411c14 MOV	%R9,0x10(%R8,%RDI,1)

  (139) 0x411c19 MOVUPS	(%R8,%RCX,1),%XMM0

  (139) 0x411c1e MOVUPS	%XMM0,(%R8,%RDI,1)

  (139) 0x411c23 MOV	0x28(%RSI),%R8

  (139) 0x411c27 MOV	0x10(%R8,%RCX,1),%R9

  (139) 0x411c2c MOV	%R9,0x10(%R8,%RDI,1)

  (139) 0x411c31 MOVUPD	(%R8,%RCX,1),%XMM0

  (139) 0x411c37 MOVUPD	%XMM0,(%R8,%RDI,1)

  (139) 0x411c3d MOV	0x30(%RSI),%RDI

  (139) 0x411c41 MOV	(%RDI,%RBX,8),%R8

  (139) 0x411c45 MOV	%R8,(%RDI,%R10,8)

  (139) 0x411c49 MOV	0x78(%R14),%R9

  (139) 0x411c4d MOV	(%R9,%RDX,4),%EDI

  (139) 0x411c51 LEA	0x1(%RDI),%R8D

  (139) 0x411c55 MOV	%R8D,(%R9,%RDX,4)

  (139) 0x411c59 CMP	$0x3f,%EDI

  (139) 0x411c5c JGE	411d7b

  (139) 0x411c62 MOVSXD	(%R9,%R12,4),%RDX

  (139) 0x411c66 DEC	%RDX

  (139) 0x411c69 MOV	%EDX,(%R9,%R12,4)

  (139) 0x411c6d TEST	%EDX,%EDX

  (139) 0x411c6f JE	411cef

  (139) 0x411c71 ADD	-0x50(%RBP),%RDX

  (139) 0x411c75 MOV	0x8(%RSI),%R8

  (139) 0x411c79 MOV	(%R8,%RDX,4),%EDI

  (139) 0x411c7d MOV	%EDI,(%R8,%RBX,4)

  (139) 0x411c81 MOV	0x10(%RSI),%R8

  (139) 0x411c85 MOV	(%R8,%RDX,4),%EDI

  (139) 0x411c89 MOV	%EDI,(%R8,%RBX,4)

  (139) 0x411c8d MOV	0x18(%RSI),%R9

  (139) 0x411c91 LEA	(,%RDX,8),%RDI

  (139) 0x411c99 LEA	(%RDI,%RDI,2),%RDI

  (139) 0x411c9d MOV	0x10(%R9,%RDI,1),%R8

  (139) 0x411ca2 MOV	%R8,0x10(%R9,%RCX,1)

  (139) 0x411ca7 MOVUPS	(%R9,%RDI,1),%XMM0

  (139) 0x411cac MOVUPS	%XMM0,(%R9,%RCX,1)

  (139) 0x411cb1 MOV	0x20(%RSI),%R9

  (139) 0x411cb5 MOV	0x10(%R9,%RDI,1),%R8

  (139) 0x411cba MOV	%R8,0x10(%R9,%RCX,1)

  (139) 0x411cbf MOVUPS	(%R9,%RDI,1),%XMM0

  (139) 0x411cc4 MOVUPS	%XMM0,(%R9,%RCX,1)

  (139) 0x411cc9 MOV	0x28(%RSI),%R9

  (139) 0x411ccd MOV	0x10(%R9,%RDI,1),%R8

  (139) 0x411cd2 MOV	%R8,0x10(%R9,%RCX,1)

  (139) 0x411cd7 MOVUPD	(%R9,%RDI,1),%XMM0

  (139) 0x411cdd MOVUPD	%XMM0,(%R9,%RCX,1)

  (139) 0x411ce3 MOV	0x30(%RSI),%RCX

  (139) 0x411ce7 MOV	(%RCX,%RDX,8),%RDX

  (139) 0x411ceb MOV	%RDX,(%RCX,%RBX,8)

  (139) 0x411cef MOV	0xc(%R14),%R8D

  (139) 0x411cf3 CMP	%EAX,%R8D

  (139) 0x411cf6 JGE	411cfa

  (139) 0x411cf8 DECL	(%RSI)

  (139) 0x411cfa MOV	%R8D,%EDI

  (139) 0x411cfd MOV	-0x40(%RBP),%RCX

  (139) 0x411d01 MOV	0x78(%R14),%RDX

  (139) 0x411d05 CMP	(%RDX,%R12,4),%ECX

  (139) 0x411d09 JL	4119d4

(138) 0x411d0f JMP	411990

  (139) 0x411d14 IMUL	%EDI,%EDX

  (139) 0x411d17 ADD	%EAX,%EDX

  (139) 0x411d19 LEA	(%RDX,%R8,1),%EAX

  (139) 0x411d1d IMUL	%R13D,%EDX

  (139) 0x411d21 ADD	%ECX,%EDX

  (139) 0x411d23 CMP	$-0x1,%ECX

  (139) 0x411d26 MOV	-0x2c(%RBP),%EDI

  (139) 0x411d29 CMOVE	%R8D,%EDI

  (139) 0x411d2d CMOVE	%EAX,%EDX

  (139) 0x411d30 MOV	%EDX,%EAX

  (139) 0x411d32 TEST	%EAX,%EAX

  (139) 0x411d34 JNS	411b97

0x411d3a MOV	$0x42fb96,%EDI

0x411d3f MOV	$0x42fabf,%ESI

0x411d44 MOV	$0x42fba0,%ECX

0x411d49 MOV	$0xf6,%EDX

0x411d4e CALL	405100 <__assert_fail@plt>

0x411d53 ADD	$0x68,%RSP

0x411d57 POP	%RBX

0x411d58 POP	%R12

0x411d5a POP	%R13

0x411d5c POP	%R14

0x411d5e POP	%R15

0x411d60 POP	%RBP

0x411d61 RET

0x411d62 MOV	$0x42fbcf,%EDI

0x411d67 MOV	$0x42fabf,%ESI

0x411d6c MOV	$0x42fba0,%ECX

0x411d71 MOV	$0xf7,%EDX

0x411d76 CALL	405100 <__assert_fail@plt>

0x411d7b MOV	$0x42fbe9,%EDI

0x411d80 MOV	$0x42fabf,%ESI

0x411d85 MOV	$0x42fc08,%ECX

0x411d8a MOV	$0x106,%EDX

0x411d8f CALL	405100 <__assert_fail@plt>

0x411d94 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►74.30+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►24.77+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_3

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-237,246-247,258-269,288-304,327-334,352-365,371-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.25 to 0.41 cycles (15.13x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	52
nb uops	50
loop length	204
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.25 cycles
front end	6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Dispatch	4.50
Overall L1	6.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	8%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.25 cycles. At this rate:

1% of peak load performance is reached (4.48 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.25 to 4.50 cycles (1.39x speedup).

ASM code

In the binary file, the address of the function is: 411930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP 0x14(%RDI),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JGE 411977 <updateLinkCells.A+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x78(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%R14),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 411d53 <updateLinkCells.A+0x423>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 41199f <updateLinkCells.A+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 411d3a <updateLinkCells.A+0x40a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 411d3a <updateLinkCells.A+0x40a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 411d3a <updateLinkCells.A+0x40a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV $0x42fb96,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x42fabf,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x42fba0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 405100 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV $0x42fbcf,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x42fabf,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x42fba0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 405100 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV $0x42fbe9,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x42fabf,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x42fc08,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 405100 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_3

Source file and lines	linkCells.c:211-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	52
nb uops	50
loop length	204
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.25 cycles
front end	6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.25
Dispatch	4.50
Overall L1	6.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	8%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.25 cycles. At this rate:

1% of peak load performance is reached (4.48 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 411930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP 0x14(%RDI),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JGE 411977 <updateLinkCells.A+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x78(%R14),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%R14),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 411d53 <updateLinkCells.A+0x423>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%R14),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 41199f <updateLinkCells.A+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 411d3a <updateLinkCells.A+0x40a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 411d3a <updateLinkCells.A+0x40a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 411d3a <updateLinkCells.A+0x40a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV $0x42fb96,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x42fabf,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x42fba0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 405100 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV $0x42fbcf,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x42fabf,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x42fba0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 405100 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV $0x42fbe9,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV $0x42fabf,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x42fc08,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 405100 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.39	0.11
▼Loop 138 - linkCells.c:211-373 - exec–	0.00	0.03
○Loop 139 - linkCells.c:211-373 - exec	0.39	3.60
○Loop 140 - linkCells.c:384-385 - exec	0.00	0.00

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Vectorization

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CALL instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code