OV - exec - Loop 115

	Loop Id: 115	Module: exec	Source: timestep.c:110-116	Coverage: 0.03%

0x212220 VPMOVSXDQ	-0x30(%RDX),%YMM10    [3]

0x212226 VPMOVSXDQ	-0x20(%RDX),%YMM9    [3]

0x21222c VMOVUPD	0x100(%R13,%RDI,4),%YMM19    [2]

0x212234 VMOVUPD	0x160(%R13,%RDI,4),%YMM20    [2]

0x21223c VEXTRACTI128	$0x1,%YMM10,%XMM11

0x212242 VEXTRACTI128	$0x1,%YMM9,%XMM13

0x212248 VMOVQ	%XMM11,%R14

0x21224d SAL	$0x4,%R14

0x212251 VMOVSD	0x8(%R9,%R14,1),%XMM12    [1]

0x212258 VPEXTRQ	$0x1,%XMM11,%R14

0x21225e SAL	$0x4,%R14

0x212262 VMOVHPD	0x8(%R9,%R14,1),%XMM12,%XMM11    [1]

0x212269 VMOVQ	%XMM10,%R14

0x21226e SAL	$0x4,%R14

0x212272 VMOVSD	0x8(%R9,%R14,1),%XMM12    [1]

0x212279 VPEXTRQ	$0x1,%XMM10,%R14

0x21227f VPMOVSXDQ	-0x10(%RDX),%YMM10    [3]

0x212285 SAL	$0x4,%R14

0x212289 VMOVHPD	0x8(%R9,%R14,1),%XMM12,%XMM12    [1]

0x212290 VMOVQ	%XMM13,%R14

0x212295 SAL	$0x4,%R14

0x212299 VMOVSD	0x8(%R9,%R14,1),%XMM14    [1]

0x2122a0 VPEXTRQ	$0x1,%XMM13,%R14

0x2122a6 SAL	$0x4,%R14

0x2122aa VMOVHPD	0x8(%R9,%R14,1),%XMM14,%XMM13    [1]

0x2122b1 VMOVQ	%XMM9,%R14

0x2122b6 SAL	$0x4,%R14

0x2122ba VMOVSD	0x8(%R9,%R14,1),%XMM14    [1]

0x2122c1 VPEXTRQ	$0x1,%XMM9,%R14

0x2122c7 SAL	$0x4,%R14

0x2122cb VMOVHPD	0x8(%R9,%R14,1),%XMM14,%XMM15    [1]

0x2122d2 VEXTRACTI128	$0x1,%YMM10,%XMM9

0x2122d8 VMOVQ	%XMM9,%R14

0x2122dd SAL	$0x4,%R14

0x2122e1 VMOVSD	0x8(%R9,%R14,1),%XMM14    [1]

0x2122e8 VPEXTRQ	$0x1,%XMM9,%R14

0x2122ee VPMOVSXDQ	(%RDX),%YMM9    [3]

0x2122f3 ADD	$0x40,%RDX

0x2122f7 SAL	$0x4,%R14

0x2122fb VMOVHPD	0x8(%R9,%R14,1),%XMM14,%XMM16    [1]

0x212303 VMOVQ	%XMM10,%R14

0x212308 SAL	$0x4,%R14

0x21230c VMOVSD	0x8(%R9,%R14,1),%XMM14    [1]

0x212313 VPEXTRQ	$0x1,%XMM10,%R14

0x212319 SAL	$0x4,%R14

0x21231d VMOVHPD	0x8(%R9,%R14,1),%XMM14,%XMM17    [1]

0x212325 VEXTRACTI128	$0x1,%YMM9,%XMM10

0x21232b VMOVQ	%XMM10,%R14

0x212330 SAL	$0x4,%R14

0x212334 VMOVSD	0x8(%R9,%R14,1),%XMM14    [1]

0x21233b VPEXTRQ	$0x1,%XMM10,%R14

0x212341 SAL	$0x4,%R14

0x212345 VMOVHPD	0x8(%R9,%R14,1),%XMM14,%XMM18    [1]

0x21234d VMOVQ	%XMM9,%R14

0x212352 VINSERTF128	$0x1,%XMM11,%YMM12,%YMM14

0x212358 VINSERTF128	$0x1,%XMM13,%YMM15,%YMM11

0x21235e VMOVUPD	(%R13,%RDI,4),%ZMM15    [2]

0x212366 VMOVUPD	0xc0(%R13,%RDI,4),%ZMM13    [2]

0x21236e VMOVUPD	0x120(%R13,%RDI,4),%ZMM12    [2]

0x212379 SAL	$0x4,%R14

0x21237d VMOVSD	0x8(%R9,%R14,1),%XMM10    [1]

0x212384 VPEXTRQ	$0x1,%XMM9,%R14

0x21238a SAL	$0x4,%R14

0x21238e VMOVHPD	0x8(%R9,%R14,1),%XMM10,%XMM9    [1]

0x212395 VINSERTF32X4	$0x1,%XMM16,%YMM17,%YMM10

0x21239c VMOVUPD	0x40(%R13,%RDI,4),%YMM16    [2]

0x2123a4 VMOVUPD	0x60(%R13,%RDI,4),%ZMM17    [2]

0x2123af VMOVAPD	%ZMM15,%ZMM21

0x2123b5 VMOVAPD	%ZMM15,%ZMM25

0x2123bb VMOVAPD	%ZMM13,%ZMM23

0x2123c1 VPERMT2PD	%ZMM19,%ZMM1,%ZMM23

0x2123c7 VMOVAPD	%ZMM13,%ZMM27

0x2123cd VMOVAPD	%ZMM12,%ZMM24

0x2123d3 VPERMT2PD	%ZMM20,%ZMM1,%ZMM24

0x2123d9 VPERMT2PD	%ZMM19,%ZMM2,%ZMM27

0x2123df VMOVAPD	%ZMM12,%ZMM28

0x2123e5 VPERMT2PD	%ZMM20,%ZMM2,%ZMM28

0x2123eb VPERMT2PD	%ZMM19,%ZMM3,%ZMM13

0x2123f1 VPERMT2PD	%ZMM20,%ZMM3,%ZMM12

0x2123f7 VINSERTF32X4	$0x1,%XMM18,%YMM9,%YMM9

0x2123fe VMOVUPD	0xa0(%R13,%RDI,4),%YMM18    [2]

0x212406 VPERMT2PD	%ZMM16,%ZMM1,%ZMM21

0x21240c VMOVAPD	%ZMM17,%ZMM22

0x212412 VPERMT2PD	%ZMM16,%ZMM2,%ZMM25

0x212418 VMOVAPD	%ZMM17,%ZMM26

0x21241e VPERMT2PD	%ZMM16,%ZMM3,%ZMM15

0x212424 ADD	$0x60,%RDI

0x212428 VMULPD	%YMM23,%YMM23,%YMM23

0x21242e VMULPD	%YMM24,%YMM24,%YMM24

0x212434 VFMADD213PD	%YMM23,%YMM27,%YMM27

0x21243a VFMADD213PD	%YMM24,%YMM28,%YMM28

0x212440 VMULPD	%YMM21,%YMM21,%YMM21

0x212446 VPERMT2PD	%ZMM18,%ZMM1,%ZMM22

0x21244c VPERMT2PD	%ZMM18,%ZMM2,%ZMM26

0x212452 VFMADD213PD	%YMM21,%YMM25,%YMM25

0x212458 VPERMT2PD	%ZMM18,%ZMM3,%ZMM17

0x21245e VFMADD213PD	%YMM27,%YMM13,%YMM13

0x212464 VFMADD213PD	%YMM28,%YMM12,%YMM12

0x21246a VFMADD213PD	%YMM25,%YMM15,%YMM15

0x212470 VMULPD	%YMM22,%YMM22,%YMM22

0x212476 VFMADD213PD	%YMM22,%YMM26,%YMM26

0x21247c VMULPD	%YMM4,%YMM15,%YMM15

0x212480 VDIVPD	%YMM14,%YMM15,%YMM14

0x212485 VFMADD213PD	%YMM26,%YMM17,%YMM17

0x21248b VMULPD	%YMM4,%YMM17,%YMM15

0x212491 VDIVPD	%YMM11,%YMM15,%YMM11

0x212496 VADDPD	%YMM5,%YMM14,%YMM5

0x21249a VADDPD	%YMM6,%YMM11,%YMM6

0x21249e VMULPD	%YMM4,%YMM13,%YMM11

0x2124a2 VDIVPD	%YMM10,%YMM11,%YMM10

0x2124a7 VMULPD	%YMM4,%YMM12,%YMM11

0x2124ab VDIVPD	%YMM9,%YMM11,%YMM9

0x2124b0 VADDPD	%YMM7,%YMM10,%YMM7

0x2124b4 VADDPD	%YMM8,%YMM9,%YMM8

0x2124b9 CMP	%RDI,%RBX

0x2124bc JNE	212220

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Coverage (%)	Name	Source Location	Module
►96.82+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.27+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	timestep	timestep.c:120	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.39
CQA speedup if fully vectorized	1.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P10, P11, P12, P13,
Function	kineticEnergy.omp_outlined
Source	timestep.c:110-116
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	low
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	9.54
Front-end cycles	15.38
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	5.67
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	7.00
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	16.00
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	116.00
Nb uops	123.00
Nb loads	28.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	16.00
Nb FLOP mul	32.00
Nb FLOP fma	32.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.00
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	66.67
Vectorization ratio load	42.86
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	63.64
Vector-efficiency ratio all	46.88
Vector-efficiency ratio load	32.14
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	54.55

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.39
CQA speedup if fully vectorized	1.68
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P10, P11, P12, P13,
Function	kineticEnergy.omp_outlined
Source	timestep.c:110-116
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	low
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	11.50
CQA cycles if fully vectorized	9.54
Front-end cycles	15.38
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	5.67
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	7.00
P7 cycles	7.00
P8 cycles	7.00
P9 cycles	7.00
P10 cycles	16.00
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	16.00
P14 cycles	8.00
P15 cycles	8.00
DIV/SQRT cycles	16.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	116.00
Nb uops	123.00
Nb loads	28.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	16.00
Nb FLOP mul	32.00
Nb FLOP fma	32.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.00
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	66.67
Vectorization ratio load	42.86
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	63.64
Vector-efficiency ratio all	46.88
Vector-efficiency ratio load	32.14
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	54.55

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy.omp_outlined
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 9.54 cycles (1.68x speedup).

Details

66% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.
63% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

execution of divide and square root operations (the divide/square root unit is a bottleneck)
execution of FP add operations (the FP add unit is a bottleneck)

Workaround

- Reduce the number of division or square root instructions:
  - If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
- Check whether you really need double precision. If not, switch to single precision to speedup execution
Reduce the number of FP add instructions

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPEXTRQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
VINSERTF32X4: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

24 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

48: addition or subtraction (32 inside FMA instructions)
64: multiply (32 inside FMA instructions)
16: divide

The binary loop is loading 576 bytes (72 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	116
nb uops	123
loop length	674
used x86 registers	6
used mmx registers	0
used xmm registers	10
used ymm registers	25
used zmm registers	19
nb stack references	0
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	5.67	5.67	5.67	7.00	7.00	7.00	7.00	16.00	16.00	16.00	16.00	8.00	8.00
cycles	0.67	0.67	0.67	5.67	5.67	5.67	7.00	7.00	7.00	7.00	16.00	16.00	16.00	16.00	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.38
Dispatch	16.00
DIV/SQRT	16.00
Data deps.	2.00
Overall L1	16.00

Vectorization ratios

INT

all	33%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	77%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	66%
load	42%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	63%

Vector efficiency ratios

INT

all	16%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	56%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	87%

INT+FP

all	46%
load	32%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	54%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

14% of peak load performance is reached (36.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 212220

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPMOVSXDQ -0x30(%RDX),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ -0x20(%RDX),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVUPD 0x100(%R13,%RDI,4),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x160(%R13,%RDI,4),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTI128 $0x1,%YMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM11,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM12,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM10,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPMOVSXDQ -0x10(%RDX),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM12,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM13,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM13,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPMOVSXDQ (%RDX),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
ADD $0x40,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM10,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM10,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM11,%YMM12,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VINSERTF128 $0x1,%XMM13,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVUPD (%R13,%RDI,4),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0xc0(%R13,%RDI,4),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x120(%R13,%RDI,4),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM10,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM16,%YMM17,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVUPD 0x40(%R13,%RDI,4),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x60(%R13,%RDI,4),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM15,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM15,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM13,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM1,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM13,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM12,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM1,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM2,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM12,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM2,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM3,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM3,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VINSERTF32X4 $0x1,%XMM18,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVUPD 0xa0(%R13,%RDI,4),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %ZMM16,%ZMM1,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM17,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM16,%ZMM2,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM17,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM16,%ZMM3,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
ADD $0x60,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD %YMM23,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM24,%YMM24,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM23,%YMM27,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM24,%YMM28,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM21,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %ZMM18,%ZMM1,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM2,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VFMADD213PD %YMM21,%YMM25,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPERMT2PD %ZMM18,%ZMM3,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VFMADD213PD %YMM27,%YMM13,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM28,%YMM12,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM25,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM22,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM22,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM14,%YMM15,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VFMADD213PD %YMM26,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM17,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM11,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VADDPD %YMM5,%YMM14,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM6,%YMM11,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM4,%YMM13,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM10,%YMM11,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM4,%YMM12,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VADDPD %YMM7,%YMM10,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM8,%YMM9,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
CMP %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 212220 <kineticEnergy.omp_outlined+0x200>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	kineticEnergy.omp_outlined
Source file and lines	timestep.c:110-116
Module	exec

gain
potential
hint
expert

Vectorization

Details

66% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

42% of SSE/AVX loads are used in vector version.
63% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

execution of divide and square root operations (the divide/square root unit is a bottleneck)
execution of FP add operations (the FP add unit is a bottleneck)

Workaround

- Reduce the number of division or square root instructions:
  - If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
- Check whether you really need double precision. If not, switch to single precision to speedup execution
Reduce the number of FP add instructions

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPEXTRQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
VINSERTF32X4: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

24 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

48: addition or subtraction (32 inside FMA instructions)
64: multiply (32 inside FMA instructions)
16: divide

The binary loop is loading 576 bytes (72 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	116
nb uops	123
loop length	674
used x86 registers	6
used mmx registers	0
used xmm registers	10
used ymm registers	25
used zmm registers	19
nb stack references	0
ADD-SUB / MUL ratio	0.50

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	15.38 cycles
front end	15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	5.67	5.67	5.67	7.00	7.00	7.00	7.00	16.00	16.00	16.00	16.00	8.00	8.00
cycles	0.67	0.67	0.67	5.67	5.67	5.67	7.00	7.00	7.00	7.00	16.00	16.00	16.00	16.00	8.00	8.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	16.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.38
Dispatch	16.00
DIV/SQRT	16.00
Data deps.	2.00
Overall L1	16.00

Vectorization ratios

INT

all	33%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	77%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	66%
load	42%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	63%

Vector efficiency ratios

INT

all	16%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	56%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	87%

INT+FP

all	46%
load	32%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	54%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

14% of peak load performance is reached (36.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 212220

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPMOVSXDQ -0x30(%RDX),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ -0x20(%RDX),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVUPD 0x100(%R13,%RDI,4),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x160(%R13,%RDI,4),%YMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTI128 $0x1,%YMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM11,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM12,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM10,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPMOVSXDQ -0x10(%RDX),%YMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM12,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM13,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM13,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPMOVSXDQ (%RDX),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
ADD $0x40,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM10,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM10,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM14,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM11,%YMM12,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VINSERTF128 $0x1,%XMM13,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVUPD (%R13,%RDI,4),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0xc0(%R13,%RDI,4),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x120(%R13,%RDI,4),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R9,%R14,1),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVHPD 0x8(%R9,%R14,1),%XMM10,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM16,%YMM17,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVUPD 0x40(%R13,%RDI,4),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x60(%R13,%RDI,4),%ZMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM15,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM15,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM13,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM1,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM13,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM12,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM1,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM2,%ZMM27	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM12,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM2,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM3,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM20,%ZMM3,%ZMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VINSERTF32X4 $0x1,%XMM18,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVUPD 0xa0(%R13,%RDI,4),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %ZMM16,%ZMM1,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM17,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM16,%ZMM2,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM17,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM16,%ZMM3,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
ADD $0x60,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD %YMM23,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM24,%YMM24,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM23,%YMM27,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM24,%YMM28,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM21,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPERMT2PD %ZMM18,%ZMM1,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM18,%ZMM2,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VFMADD213PD %YMM21,%YMM25,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPERMT2PD %ZMM18,%ZMM3,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	5	0.50	vect (100.0%)
VFMADD213PD %YMM27,%YMM13,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM28,%YMM12,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM25,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM22,%YMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM22,%YMM26,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM14,%YMM15,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VFMADD213PD %YMM26,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM4,%YMM17,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM11,%YMM15,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VADDPD %YMM5,%YMM14,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM6,%YMM11,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM4,%YMM13,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM10,%YMM11,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD %YMM4,%YMM12,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VADDPD %YMM7,%YMM10,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM8,%YMM9,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
CMP %RDI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 212220 <kineticEnergy.omp_outlined+0x200>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code