OV - exec - Loop 110

	Loop Id: 110	Module: exec	Source: timestep.c:76-78	Coverage: 0.21%

0x211d40 VMOVUPD	(%R11,%R8,1),%ZMM18    [2]

0x211d47 VMOVUPD	0x40(%R11,%R8,1),%YMM19    [2]

0x211d4f VMOVUPD	0x40(%R10,%R8,1),%YMM22    [1]

0x211d57 VBROADCASTSD	(%RBX),%YMM17    [3]

0x211d5d VMOVAPD	%ZMM18,%ZMM20

0x211d63 VMOVAPD	%ZMM18,%ZMM21

0x211d69 VPERMT2PD	%ZMM19,%ZMM0,%ZMM20

0x211d6f VPERMT2PD	%ZMM19,%ZMM1,%ZMM21

0x211d75 VPERMT2PD	%ZMM19,%ZMM2,%ZMM18

0x211d7b VMOVUPD	(%R10,%R8,1),%ZMM19    [1]

0x211d82 VMOVAPD	%ZMM19,%ZMM23

0x211d88 VPERMT2PD	%ZMM22,%ZMM0,%ZMM23

0x211d8e VMOVAPD	%ZMM19,%ZMM24

0x211d94 VPERMT2PD	%ZMM22,%ZMM1,%ZMM24

0x211d9a VPERMT2PD	%ZMM22,%ZMM2,%ZMM19

0x211da0 VFMADD231PD	%YMM20,%YMM17,%YMM23

0x211da6 VFMADD231PD	%YMM21,%YMM17,%YMM24

0x211dac VFMADD231PD	%YMM18,%YMM17,%YMM19

0x211db2 VINSERTF64X4	$0x1,%YMM24,%ZMM23,%ZMM17

0x211db9 VMOVAPD	%ZMM17,%ZMM18

0x211dbf VPERMT2PD	%ZMM19,%ZMM3,%ZMM18

0x211dc5 VPERMT2PD	%ZMM19,%ZMM4,%ZMM17

0x211dcb VMOVUPD	%ZMM17,(%R10,%R8,1)    [1]

0x211dd2 VMOVUPD	%YMM18,0x40(%R10,%R8,1)    [1]

0x211dda ADD	$0x60,%R8

0x211dde ADD	$0x4,%RCX

0x211de2 JNE	211d40

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 76 - 78

--------------------------------------------------------------------------------

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module
►95.93+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.92+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	timestep	timestep.c:39	exec
○	main	CoMD.c:125	exec
►1.92+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	timestep	timestep.c:55	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.80
CQA speedup if fully vectorized	1.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P11, P12,
Function	advanceVelocity.omp_outlined
Source	timestep.c:76-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	4.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	4.25
Front-end cycles	3.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	3.00
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	5.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.33
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	65.78
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	96.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	95.83
Vectorization ratio load	80.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	93.33
Vector-efficiency ratio all	81.77
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	75.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	90.83

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.80
CQA speedup if fully vectorized	1.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P11, P12,
Function	advanceVelocity.omp_outlined
Source	timestep.c:76-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	intermediate
Unroll factor	4
CQA cycles	4.50
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	4.25
Front-end cycles	3.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	3.00
P11 cycles	4.50
P12 cycles	4.50
P13 cycles	0.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	5.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.33
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	65.78
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	96.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	95.83
Vectorization ratio load	80.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	93.33
Vector-efficiency ratio all	81.77
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	75.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	90.83

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity.omp_outlined
Source file and lines	timestep.c:76-78
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76-78.

It is intermediate loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is highly vectorized. 81% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.50 to 3.25 cycles (1.38x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 12 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VINSERTF64X4: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	26
loop length	168
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	13
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	1.75	1.75	1.75	1.75	3.00	4.50	4.50	0.00	1.00	1.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	1.75	1.75	1.75	1.75	3.00	4.50	4.50	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.25
Dispatch	4.50
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

all	95%
load	80%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

Vector efficiency ratios

all	81%
load	62%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

17% of peak load performance is reached (44.44 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 211d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11,%R8,1),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R11,%R8,1),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%R10,%R8,1),%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD (%RBX),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %ZMM18,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM0,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM1,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM2,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD (%R10,%R8,1),%ZMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM19,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM0,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM19,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM1,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM2,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VFMADD231PD %YMM20,%YMM17,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM17,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM18,%YMM17,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VINSERTF64X4 $0x1,%YMM24,%ZMM23,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (50.0%)
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM3,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM4,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD %ZMM17,(%R10,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %YMM18,0x40(%R10,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x60,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 211d40 <advanceVelocity.omp_outlined+0x390>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	advanceVelocity.omp_outlined
Source file and lines	timestep.c:76-78
Module	exec

gain
potential
hint
expert

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is highly vectorized. 81% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

80% of SSE/AVX loads are used in vector version.
93% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 12 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VINSERTF64X4: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	26
loop length	168
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	13
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	1.75	1.75	1.75	1.75	3.00	4.50	4.50	0.00	1.00	1.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	1.75	1.75	1.75	1.75	3.00	4.50	4.50	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.25
Dispatch	4.50
Data deps.	1.00
Overall L1	4.50

Vectorization ratios

all	95%
load	80%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

Vector efficiency ratios

all	81%
load	62%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

17% of peak load performance is reached (44.44 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 211d40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R11,%R8,1),%ZMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R11,%R8,1),%YMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD 0x40(%R10,%R8,1),%YMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VBROADCASTSD (%RBX),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %ZMM18,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM18,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM0,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM1,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM2,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD (%R10,%R8,1),%ZMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM19,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM0,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM19,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM1,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM22,%ZMM2,%ZMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VFMADD231PD %YMM20,%YMM17,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM21,%YMM17,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM18,%YMM17,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VINSERTF64X4 $0x1,%YMM24,%ZMM23,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (50.0%)
VMOVAPD %ZMM17,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM3,%ZMM18	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM19,%ZMM4,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD %ZMM17,(%R10,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %YMM18,0x40(%R10,%R8,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x60,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 211d40 <advanceVelocity.omp_outlined+0x390>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code