OV - exec - Loop 102

	Loop Id: 102	Module: exec	Source: ljForce.c:191-216 [...]	Coverage: 62.55%

0x20f2a0 INC	%R15

0x20f2a3 ADD	$0x18,%R10

0x20f2a7 CMP	%R8,%R15

0x20f2aa JGE	20f280

0x20f2ac VMOVUPD	(%R11),%XMM8    [3]

0x20f2b1 VSUBPD	-0x10(%R10),%XMM8,%XMM8    [2]

0x20f2b7 VMULPD	%XMM8,%XMM8,%XMM9

0x20f2bc VSHUFPD	$0x1,%XMM9,%XMM9,%XMM10

0x20f2c2 VADDSD	%XMM9,%XMM10,%XMM10

0x20f2c7 VMOVSD	0x10(%R11),%XMM9    [3]

0x20f2cd VSUBSD	(%R10),%XMM9,%XMM9    [2]

0x20f2d2 VFMADD231SD	%XMM9,%XMM9,%XMM10

0x20f2d7 VUCOMISD	%XMM0,%XMM10

0x20f2db JBE	20f2a0

0x20f2dd VUCOMISD	(%RCX),%XMM10    [8]

0x20f2e1 JA	20f2a0

0x20f2e3 VDIVSD	%XMM10,%XMM1,%XMM10

0x20f2e8 MOV	0x30(%R13),%RBX    [5]

0x20f2ec VMULSD	%XMM10,%XMM10,%XMM11

0x20f2f1 VMULSD	%XMM10,%XMM11,%XMM11

0x20f2f6 VMULSD	(%RDX),%XMM11,%XMM11    [9]

0x20f2fa VMULSD	%XMM7,%XMM10,%XMM10

0x20f2fe VADDSD	%XMM3,%XMM11,%XMM12

0x20f302 VFNMADD213SD	(%RDI),%XMM11,%XMM12    [1]

0x20f307 VMULSD	%XMM11,%XMM10,%XMM10

0x20f30c VMULSD	%XMM4,%XMM12,%XMM12

0x20f310 VADDSD	(%RBX,%RAX,8),%XMM12,%XMM13    [7]

0x20f315 VADDSD	%XMM2,%XMM12,%XMM2

0x20f319 VMOVSD	%XMM13,(%RBX,%RAX,8)    [7]

0x20f31e VMOVAPD	%XMM5,%XMM13

0x20f322 VFMADD213SD	%XMM6,%XMM11,%XMM13

0x20f327 MOV	0x28(%R13),%RBX    [5]

0x20f32b VMULSD	%XMM13,%XMM10,%XMM10

0x20f330 VMULSD	(%RSI),%XMM10,%XMM10    [4]

0x20f334 VMOVDDUP	%XMM10,%XMM11

0x20f339 VFMADD213PD	(%RBX,%R12,8),%XMM11,%XMM8    [6]

0x20f33f VMOVUPD	%XMM8,(%RBX,%R12,8)    [6]

0x20f345 VFMADD213SD	0x10(%RBX,%R12,8),%XMM10,%XMM9    [6]

0x20f34c VMOVSD	%XMM9,0x10(%RBX,%R12,8)    [6]

0x20f353 JMP	20f2a0

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 191 - 216

--------------------------------------------------------------------------------

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.06
CQA speedup if fully vectorized	6.82
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks
Function	ljForce.omp_outlined.5
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	12
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	1.94
CQA cycles if fully vectorized	0.59
Front-end cycles	3.13
P0 cycles	0.94
P1 cycles	0.94
P2 cycles	0.94
P3 cycles	1.06
P4 cycles	1.06
P5 cycles	1.06
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	2.08
P9 cycles	2.08
P10 cycles	3.50
P11 cycles	3.50
P12 cycles	3.17
P13 cycles	3.17
P14 cycles	1.33
P15 cycles	1.33
DIV/SQRT cycles	1.33
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.33
Nb uops	25.00
Nb loads	7.33
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.83
Nb FLOP add-sub	5.00
Nb FLOP mul	4.67
Nb FLOP fma	2.67
Nb FLOP div	0.33
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.58
Bytes prefetched	0.00
Bytes loaded	77.33
Bytes stored	10.67
Stride 0	3.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.67
Stride indirect	0.00
Vectorization ratio all	35.68
Vectorization ratio load	39.09
Vectorization ratio store	33.33
Vectorization ratio mul	70.37
Vectorization ratio add_sub	27.78
Vectorization ratio fma	6.67
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	41.11
Vector-efficiency ratio all	16.96
Vector-efficiency ratio load	17.39
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	21.30
Vector-efficiency ratio add_sub	15.97
Vector-efficiency ratio fma	13.33
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.64

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	6.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P12, P13,
Function	ljForce.omp_outlined.5
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	12
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.32
Front-end cycles	1.88
P0 cycles	0.83
P1 cycles	0.83
P2 cycles	0.83
P3 cycles	0.83
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	15.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	4.00
Nb FLOP mul	2.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	44.44
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	33.33
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	18.06
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	16.67
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.11
CQA speedup if fully vectorized	7.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P10, P11,
Function	ljForce.omp_outlined.5
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	12
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	3.56
CQA cycles if fully vectorized	1.06
Front-end cycles	5.25
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.33
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	5.00
P13 cycles	5.00
P14 cycles	2.50
P15 cycles	2.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	42.00
Nb loads	13.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	4.00
Nb FLOP add-sub	7.00
Nb FLOP mul	10.00
Nb FLOP fma	6.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	32.00
Stride 0	6.00
Stride 1	1.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	22.58
Vectorization ratio load	27.27
Vectorization ratio store	33.33
Vectorization ratio mul	11.11
Vectorization ratio add_sub	16.67
Vectorization ratio fma	20.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	40.00
Vector-efficiency ratio all	15.32
Vector-efficiency ratio load	15.91
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	13.89
Vector-efficiency ratio add_sub	14.58
Vector-efficiency ratio fma	15.00
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	17.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.00
CQA speedup if fully vectorized	6.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P12, P13,
Function	ljForce.omp_outlined.5
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	unrolled by 12
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	12
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.38
Front-end cycles	2.25
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	1.50
P11 cycles	1.50
P12 cycles	2.50
P13 cycles	2.50
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	18.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.20
Nb FLOP add-sub	4.00
Nb FLOP mul	2.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.40
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	40.00
Vectorization ratio load	40.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	33.33
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	17.50
Vector-efficiency ratio load	17.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	16.67
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:191-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:191,197-216.

It is main loop of related source loop which is unrolled by 12 (including vectorization).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.59 cycles (6.82x speedup).

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

39% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
27% of SSE/AVX addition or subtraction instructions are used in vector version.
70% of SSE/AVX multiply instructions are used in vector version.
6% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 2.67 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 0 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

9 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15.333333333333 FP arithmetical operations:

7.67: addition or subtraction (2 inside FMA instructions)
7.33: multiply (2 inside FMA instructions)
0.33: divide

The binary loop is loading 77 bytes (9 double precision FP elements). The binary loop is storing 10 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	23.33
nb uops	25
loop length	104
used x86 registers	7
used mmx registers	0
used xmm registers	7.33
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	2.22

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	3.13 cycles
front end	3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.94	0.94	0.94	1.06	1.06	1.06	2.08	2.08	2.08	2.08	3.50	3.50	3.17	3.17	1.33	1.33
cycles	0.94	0.94	0.94	1.06	1.06	1.06	2.08	2.08	2.08	2.08	3.50	3.50	3.17	3.17	1.33	1.33

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	1.33
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	3.13
Dispatch	4.00
DIV/SQRT	1.33
Data deps.	2.00
Overall L1	4.00

Vectorization ratios

all	35%
load	39%
store	33%
mul	70%
add-sub	27%
fma	6%
div/sqrt	0%
other	41%

Vector efficiency ratios

all	16%
load	17%
store	16%
mul	21%
add-sub	15%
fma	13%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

8% of peak load performance is reached (21.16 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.42 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.32 cycles (6.22x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP add operations (the FP add unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.00 to 1.88 cycles (1.07x speedup).

Workaround

Reduce the number of FP add instructions

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:198

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

5: addition or subtraction (1 inside FMA instructions)
3: multiply (1 inside FMA instructions)

The binary loop is loading 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	14
nb uops	15
loop length	61
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.88 cycles
front end	1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.83	0.83	0.83	0.83	0.83	0.83	1.00	1.00	1.00	1.00	1.50	1.50	2.00	2.00	0.50	0.50
cycles	0.83	0.83	0.83	0.83	0.83	0.83	1.00	1.00	1.00	1.00	1.50	1.50	2.00	2.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	1.88
Dispatch	2.00
Data deps.	2.00
Overall L1	2.00

Vectorization ratios

all	44%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	16%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

9% of peak load performance is reached (24.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20f2ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JGE 20f280 <ljForce.omp_outlined.5+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R11),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD -0x10(%R10),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM9,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x10(%R11),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD (%R10),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 20f2a0 <ljForce.omp_outlined.5+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.50 to 1.06 cycles (7.06x speedup).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

27% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
11% of SSE/AVX multiply instructions are used in vector version.
20% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
40% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.50 to 5.25 cycles (1.43x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 7.50 to 7.00 cycles (1.07x speedup).

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:198
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

20 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 30 FP arithmetical operations:

13: addition or subtraction (6 inside FMA instructions)
16: multiply (6 inside FMA instructions)
1: divide

The binary loop is loading 128 bytes (16 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	42
loop length	184
used x86 registers	12
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.33	1.33	1.33	4.00	4.00	4.00	4.00	7.50	7.50	5.00	5.00	2.50	2.50
cycles	1.00	1.00	1.00	1.33	1.33	1.33	4.00	4.00	4.00	4.00	7.50	7.50	5.00	5.00	2.50	2.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	5.25
Dispatch	7.50
DIV/SQRT	4.00
Data deps.	2.00
Overall L1	7.50

Vectorization ratios

all	22%
load	27%
store	33%
mul	11%
add-sub	16%
fma	20%
div/sqrt	0%
other	40%

Vector efficiency ratios

all	15%
load	15%
store	16%
mul	13%
add-sub	14%
fma	15%
div/sqrt	12%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

6% of peak load performance is reached (17.07 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.27 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20f2ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JGE 20f280 <ljForce.omp_outlined.5+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R11),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD -0x10(%R10),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM9,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x10(%R11),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD (%R10),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 20f2a0 <ljForce.omp_outlined.5+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VUCOMISD (%RCX),%XMM10	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 20f2a0 <ljForce.omp_outlined.5+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VDIVSD %XMM10,%XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOV 0x30(%R13),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULSD %XMM10,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM10,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD (%RDX),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM7,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM3,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFNMADD213SD (%RDI),%XMM11,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMULSD %XMM11,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD %XMM4,%XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VADDSD (%RBX,%RAX,8),%XMM12,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM2,%XMM12,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM13,(%RBX,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %XMM5,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VFMADD213SD %XMM6,%XMM11,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%R13),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULSD %XMM13,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMULSD (%RSI),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVDDUP %XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VFMADD213PD (%RBX,%R12,8),%XMM11,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	vect (25.0%)
VMOVUPD %XMM8,(%RBX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VFMADD213SD 0x10(%RBX,%R12,8),%XMM10,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM9,0x10(%RBX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 20f2a0 <ljForce.omp_outlined.5+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.37 cycles (6.67x speedup).

Details

40% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

40% of SSE/AVX loads are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP add operations (the FP add unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.25 cycles (1.11x speedup).

Workaround

Reduce the number of FP add instructions

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:198
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:201

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

5: addition or subtraction (1 inside FMA instructions)
3: multiply (1 inside FMA instructions)

The binary loop is loading 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	16
nb uops	18
loop length	67
used x86 registers	5
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	3.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.25	1.25	1.25	1.25	1.50	1.50	2.50	2.50	1.00	1.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.25	1.25	1.25	1.25	1.50	1.50	2.50	2.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.25
Dispatch	2.50
Data deps.	2.00
Overall L1	2.50

Vectorization ratios

all	40%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

all	17%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	16%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

8% of peak load performance is reached (22.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20f2ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JGE 20f280 <ljForce.omp_outlined.5+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVUPD (%R11),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSUBPD -0x10(%R10),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VMULPD %XMM8,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM9,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x10(%R11),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VSUBSD (%R10),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VFMADD231SD %XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM10	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 20f2a0 <ljForce.omp_outlined.5+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VUCOMISD (%RCX),%XMM10	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JA 20f2a0 <ljForce.omp_outlined.5+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

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ASM code

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Execution units bottlenecks

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FMA

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Complex instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties