OV - exec - Loop 100

	Loop Id: 100	Module: exec	Source: ljForce.c:178-216 [...]	Coverage: 0.19%

0x20f210 MOV	-0x98(%RBP),%R8

0x20f217 INC	%R8

0x20f21a CMP	%R8,-0x40(%RBP)

0x20f21e JE	20f1a0

0x20f220 MOV	-0x68(%RBP),%RAX

0x20f224 MOV	(%RAX,%R8,4),%EAX

0x20f228 TEST	%EAX,%EAX

0x20f22a JS	20f3cc

0x20f230 MOV	%R8,-0x98(%RBP)

0x20f237 MOV	-0x60(%RBP),%R8

0x20f23b MOV	(%R8,%RAX,4),%R8D

0x20f23f TEST	%R8D,%R8D

0x20f242 JLE	20f210

0x20f244 MOV	-0x88(%RBP),%R10

0x20f24b SAL	$0x6,%EAX

0x20f24e MOVSXD	%EAX,%R9

0x20f251 ADD	%EAX,%R8D

0x20f254 LEA	(%R9,%R9,2),%RAX

0x20f258 MOVSXD	%R8D,%R8

0x20f25b MOV	0x20(%R10),%R13

0x20f25f MOV	0x18(%R13),%R14

0x20f263 LEA	0x10(%R14,%RAX,8),%RAX

0x20f268 MOV	%RAX,-0xa8(%RBP)

0x20f26f MOV	-0x90(%RBP),%RAX

0x20f276 JMP	20f28c

  (101) 0x20f280 INC	%RAX

  (101) 0x20f283 CMP	%RAX,-0xa0(%RBP)

  (101) 0x20f28a JLE	20f210

  (101) 0x20f28c MOV	-0xa8(%RBP),%R10

  (101) 0x20f293 LEA	(%RAX,%RAX,2),%R12

  (101) 0x20f297 MOV	%R9,%R15

  (101) 0x20f29a LEA	(%R14,%R12,8),%R11

  (101) 0x20f29e JMP	20f2ac

    (102) 0x20f2a0 INC	%R15

    (102) 0x20f2a3 ADD	$0x18,%R10

    (102) 0x20f2a7 CMP	%R8,%R15

    (102) 0x20f2aa JGE	20f280

    (102) 0x20f2ac VMOVUPD	(%R11),%XMM8

    (102) 0x20f2b1 VSUBPD	-0x10(%R10),%XMM8,%XMM8

    (102) 0x20f2b7 VMULPD	%XMM8,%XMM8,%XMM9

    (102) 0x20f2bc VSHUFPD	$0x1,%XMM9,%XMM9,%XMM10

    (102) 0x20f2c2 VADDSD	%XMM9,%XMM10,%XMM10

    (102) 0x20f2c7 VMOVSD	0x10(%R11),%XMM9

    (102) 0x20f2cd VSUBSD	(%R10),%XMM9,%XMM9

    (102) 0x20f2d2 VFMADD231SD	%XMM9,%XMM9,%XMM10

    (102) 0x20f2d7 VUCOMISD	%XMM0,%XMM10

    (102) 0x20f2db JBE	20f2a0

    (102) 0x20f2dd VUCOMISD	(%RCX),%XMM10

    (102) 0x20f2e1 JA	20f2a0

    (102) 0x20f2e3 VDIVSD	%XMM10,%XMM1,%XMM10

    (102) 0x20f2e8 MOV	0x30(%R13),%RBX

    (102) 0x20f2ec VMULSD	%XMM10,%XMM10,%XMM11

    (102) 0x20f2f1 VMULSD	%XMM10,%XMM11,%XMM11

    (102) 0x20f2f6 VMULSD	(%RDX),%XMM11,%XMM11

    (102) 0x20f2fa VMULSD	%XMM7,%XMM10,%XMM10

    (102) 0x20f2fe VADDSD	%XMM3,%XMM11,%XMM12

    (102) 0x20f302 VFNMADD213SD	(%RDI),%XMM11,%XMM12

    (102) 0x20f307 VMULSD	%XMM11,%XMM10,%XMM10

    (102) 0x20f30c VMULSD	%XMM4,%XMM12,%XMM12

    (102) 0x20f310 VADDSD	(%RBX,%RAX,8),%XMM12,%XMM13

    (102) 0x20f315 VADDSD	%XMM2,%XMM12,%XMM2

    (102) 0x20f319 VMOVSD	%XMM13,(%RBX,%RAX,8)

    (102) 0x20f31e VMOVAPD	%XMM5,%XMM13

    (102) 0x20f322 VFMADD213SD	%XMM6,%XMM11,%XMM13

    (102) 0x20f327 MOV	0x28(%R13),%RBX

    (102) 0x20f32b VMULSD	%XMM13,%XMM10,%XMM10

    (102) 0x20f330 VMULSD	(%RSI),%XMM10,%XMM10

    (102) 0x20f334 VMOVDDUP	%XMM10,%XMM11

    (102) 0x20f339 VFMADD213PD	(%RBX,%R12,8),%XMM11,%XMM8

    (102) 0x20f33f VMOVUPD	%XMM8,(%RBX,%R12,8)

    (102) 0x20f345 VFMADD213SD	0x10(%RBX,%R12,8),%XMM10,%XMM9

    (102) 0x20f34c VMOVSD	%XMM9,0x10(%RBX,%R12,8)

    (102) 0x20f353 JMP	20f2a0

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216

--------------------------------------------------------------------------------

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.91
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks
Function	ljForce.omp_outlined.5
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.88
CQA cycles if no scalar integer	2.88
CQA cycles if FP arith vectorized	2.88
CQA cycles if fully vectorized	0.22
Front-end cycles	2.81
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.88
P7 cycles	2.88
P8 cycles	2.88
P9 cycles	2.88
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.50
Nb loads	9.00
Nb stores	1.75
Nb stack references	6.25
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.16
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	14.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.10
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.59

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.44
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P6, P7, P8, P9,
Function	ljForce.omp_outlined.5
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.75
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	1.75
CQA cycles if fully vectorized	0.14
Front-end cycles	1.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	13.00
Nb uops	12.00
Nb loads	6.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.43
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	micro-operation queue, P6, P7, P8, P9,
Function	ljForce.omp_outlined.5
Source	ljForce.c:178-184,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.25
CQA cycles if no scalar integer	3.25
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	0.25
Front-end cycles	3.25
P0 cycles	2.33
P1 cycles	2.33
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	3.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	26.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.08
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	16.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.00
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:178-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:178-184,187.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.88 to 0.22 cycles (12.91x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 14 bytes.

General properties

nb instructions	22
nb uops	22.50
loop length	91
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6.25

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.81 cycles
front end	2.81 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.88	2.88	2.88	2.88	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.88	2.88	2.88	2.88	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	2.81
Dispatch	2.88
Data deps.	0.00
Overall L1	2.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.88 cycles. At this rate:

8% of peak load performance is reached (22.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:178-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 1.75 to 1.50 cycles (1.17x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	13
nb uops	12
loop length	52
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	1.75	1.75	1.75	1.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.50
Dispatch	1.75
Data deps.	0.00
Overall L1	1.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.75 cycles. At this rate:

8% of peak load performance is reached (22.86 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 20f220

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x98(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R8,-0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 20f1a0 <ljForce.omp_outlined.5+0x1b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%R8,4),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JS 20f3cc <ljForce.omp_outlined.5+0x3dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x60(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8,%RAX,4),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JLE 20f210 <ljForce.omp_outlined.5+0x220>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Function	ljForce.omp_outlined.5
Source file and lines	ljForce.c:178-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 2.33 cycles (1.39x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	25
nb uops	26
loop length	104
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.33	2.33	2.33	2.33	2.33	2.33	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.33	2.33	2.33	2.33	2.33	2.33	3.25	3.25	3.25	3.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	3.25
Dispatch	3.25
Data deps.	0.00
Overall L1	3.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.25 cycles. At this rate:

8% of peak load performance is reached (22.15 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.25 to 2.33 cycles (1.39x speedup).

ASM code

In the binary file, the address of the loop is: 20f220

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x98(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R8,-0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 20f1a0 <ljForce.omp_outlined.5+0x1b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%R8,4),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JS 20f3cc <ljForce.omp_outlined.5+0x3dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x60(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8,%RAX,4),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20f210 <ljForce.omp_outlined.5+0x220>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x88(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SAL $0x6,%EAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EAX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%R9,2),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOVSXD %R8D,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x20(%R10),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%R13),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x10(%R14,%RAX,8),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %RAX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 20f28c <ljForce.omp_outlined.5+0x29c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code