OV - exec - Function advanceVelocity.omp

	Function: advanceVelocity.omp_outlined	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 1.89% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x2119b0 PUSH	%RBP

0x2119b1 MOV	%RSP,%RBP

0x2119b4 PUSH	%R15

0x2119b6 PUSH	%R14

0x2119b8 PUSH	%R13

0x2119ba PUSH	%R12

0x2119bc PUSH	%RBX

0x2119bd SUB	$0x38,%RSP

0x2119c1 MOV	(%RDX),%R14D

0x2119c4 TEST	%R14D,%R14D

0x2119c7 JLE	211a47

0x2119c9 MOV	(%RDI),%ESI

0x2119cb DEC	%R14D

0x2119ce MOV	%R8,%RBX

0x2119d1 MOV	%RCX,%R15

0x2119d4 MOVL	$0,-0x30(%RBP)

0x2119db MOVL	$0x1,-0x3c(%RBP)

0x2119e2 MOVL	$0,-0x38(%RBP)

0x2119e9 MOV	%R14D,-0x2c(%RBP)

0x2119ed SUB	$0x8,%RSP

0x2119f1 LEA	-0x3c(%RBP),%RAX

0x2119f5 LEA	0x2634(%RIP),%RDI

0x2119fc LEA	-0x38(%RBP),%RCX

0x211a00 LEA	-0x30(%RBP),%R8

0x211a04 LEA	-0x2c(%RBP),%R9

0x211a08 MOV	%ESI,-0x34(%RBP)

0x211a0b MOV	$0x22,%EDX

0x211a10 PUSH	$0x1

0x211a12 PUSH	$0x1

0x211a14 PUSH	%RAX

0x211a15 CALL	212b40 <@plt_start@+0x180>

0x211a1a ADD	$0x20,%RSP

0x211a1e MOV	-0x2c(%RBP),%EAX

0x211a21 CMP	%R14D,%EAX

0x211a24 CMOVL	%EAX,%R14D

0x211a28 MOVSXD	-0x30(%RBP),%RAX

0x211a2c MOV	%R14D,-0x2c(%RBP)

0x211a30 CMP	%R14D,%EAX

0x211a33 JLE	211a56

0x211a35 MOV	-0x34(%RBP),%ESI

0x211a38 LEA	0x2609(%RIP),%RDI

0x211a3f VZEROUPPER

0x211a42 CALL	212b50 <@plt_start@+0x190>

0x211a47 ADD	$0x38,%RSP

0x211a4b POP	%RBX

0x211a4c POP	%R12

0x211a4e POP	%R13

0x211a50 POP	%R14

0x211a52 POP	%R15

0x211a54 POP	%RBP

0x211a55 RET

0x211a56 MOV	(%R15),%RDX

0x211a59 VMOVAPD	-0xd161(%RIP),%YMM0

0x211a61 VMOVAPD	-0xd129(%RIP),%YMM1

0x211a69 VMOVAPD	-0xd191(%RIP),%YMM2

0x211a71 VMOVAPD	-0xd1b9(%RIP),%YMM3

0x211a79 VMOVAPD	-0xc783(%RIP),%ZMM4

0x211a83 VMOVAPD	-0xca8d(%RIP),%ZMM5

0x211a8d VMOVAPD	-0xca57(%RIP),%ZMM6

0x211a97 VMOVAPD	-0xca21(%RIP),%ZMM7

0x211aa1 VMOVAPD	-0xc9eb(%RIP),%ZMM8

0x211aab VMOVAPD	-0xc9b5(%RIP),%ZMM9

0x211ab5 VMOVAPD	-0xc97f(%RIP),%ZMM10

0x211abf VMOVAPD	-0xc949(%RIP),%ZMM11

0x211ac9 VMOVAPD	-0xc913(%RIP),%ZMM12

0x211ad3 VMOVAPD	-0xc8dd(%RIP),%ZMM13

0x211add VMOVAPD	-0xc8a7(%RIP),%ZMM14

0x211ae7 VMOVAPD	-0xc871(%RIP),%ZMM15

0x211af1 VMOVAPD	-0xc83b(%RIP),%ZMM16

0x211afb MOV	%EAX,%ESI

0x211afd SAL	$0x6,%ESI

0x211b00 MOV	0x18(%RDX),%RCX

0x211b04 MOV	%RDX,-0x50(%RBP)

0x211b08 MOV	0x78(%RCX),%RDI

0x211b0c MOVSXD	%R14D,%RCX

0x211b0f MOV	%RCX,-0x60(%RBP)

0x211b13 LEA	0x8(%RBX),%RCX

0x211b17 MOV	%RCX,-0x58(%RBP)

0x211b1b MOV	%RDI,-0x48(%RBP)

0x211b1f JMP	211b44

0x211b21 NOPW	%CS:(%RAX,%RAX,1)

(107) 0x211b30 ADD	$0x40,%ESI

(107) 0x211b33 LEA	0x1(%RAX),%RCX

(107) 0x211b37 CMP	-0x60(%RBP),%RAX

(107) 0x211b3b MOV	%RCX,%RAX

(107) 0x211b3e JGE	211a35

(107) 0x211b44 MOV	(%RDI,%RAX,4),%R9D

(107) 0x211b48 TEST	%R9D,%R9D

(107) 0x211b4b JLE	211b30

(107) 0x211b4d MOV	0x20(%RDX),%RCX

(107) 0x211b51 MOVSXD	%ESI,%R15

(107) 0x211b54 XOR	%R12D,%R12D

(107) 0x211b57 MOV	0x20(%RCX),%R10

(107) 0x211b5b MOV	0x28(%RCX),%R11

(107) 0x211b5f CMP	$0x4,%R9D

(107) 0x211b63 JB	211e00

(107) 0x211b69 LEA	(,%R15,8),%RCX

(107) 0x211b71 LEA	(%RCX,%RCX,2),%R13

(107) 0x211b75 LEA	-0x1(%R9),%ECX

(107) 0x211b79 ADD	%R15,%RCX

(107) 0x211b7c SAL	$0x3,%RCX

(107) 0x211b80 LEA	(%R10,%R13,1),%R14

(107) 0x211b84 ADD	%R11,%R13

(107) 0x211b87 CMP	-0x58(%RBP),%R14

(107) 0x211b8b LEA	(%RCX,%RCX,2),%RCX

(107) 0x211b8f LEA	0x18(%R10,%RCX,1),%R8

(107) 0x211b94 LEA	0x18(%R11,%RCX,1),%RCX

(107) 0x211b99 SETB	%DL

(107) 0x211b9c CMP	%RBX,%R8

(107) 0x211b9f SETA	%DIL

(107) 0x211ba3 CMP	%RCX,%R14

(107) 0x211ba6 SETB	%CL

(107) 0x211ba9 CMP	%R8,%R13

(107) 0x211bac SETB	%R8B

(107) 0x211bb0 TEST	%DIL,%DL

(107) 0x211bb3 JNE	211bd4

(107) 0x211bb5 MOV	-0x50(%RBP),%RDX

(107) 0x211bb9 MOV	-0x48(%RBP),%RDI

(107) 0x211bbd AND	%R8B,%CL

(107) 0x211bc0 JNE	211e00

(107) 0x211bc6 CMP	$0x8,%R9D

(107) 0x211bca JAE	211be1

(107) 0x211bcc XOR	%R8D,%R8D

(107) 0x211bcf JMP	211d18

(107) 0x211bd4 MOV	-0x50(%RBP),%RDX

(107) 0x211bd8 MOV	-0x48(%RBP),%RDI

(107) 0x211bdc JMP	211e00

(107) 0x211be1 MOV	%R9D,%ECX

(107) 0x211be4 SHR	$0x3,%ECX

(107) 0x211be7 MOV	%R9D,%R8D

(107) 0x211bea AND	$-0x8,%R8D

(107) 0x211bee SAL	$0x6,%RCX

(107) 0x211bf2 LEA	(%RCX,%RCX,2),%R12

(107) 0x211bf6 XOR	%ECX,%ECX

(107) 0x211bf8 NOPL	(%RAX,%RAX,1)

  (109) 0x211c00 VMOVUPD	(%R13,%RCX,1),%ZMM18

  (109) 0x211c08 VMOVUPD	0x40(%R13,%RCX,1),%ZMM19

  (109) 0x211c10 VMOVUPD	0x40(%R14,%RCX,1),%ZMM26

  (109) 0x211c18 VMOVUPD	0x80(%R13,%RCX,1),%ZMM20

  (109) 0x211c20 VMOVUPD	0x80(%R14,%RCX,1),%ZMM23

  (109) 0x211c28 VBROADCASTSD	(%RBX),%ZMM17

  (109) 0x211c2e VMOVAPD	%ZMM18,%ZMM21

  (109) 0x211c34 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

  (109) 0x211c3a VMOVAPD	%ZMM18,%ZMM22

  (109) 0x211c40 VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

  (109) 0x211c46 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

  (109) 0x211c4c VMOVUPD	(%R14,%RCX,1),%ZMM18

  (109) 0x211c53 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

  (109) 0x211c59 VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

  (109) 0x211c5f VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

  (109) 0x211c65 VMOVAPD	%ZMM18,%ZMM24

  (109) 0x211c6b VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

  (109) 0x211c71 VMOVAPD	%ZMM18,%ZMM25

  (109) 0x211c77 VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

  (109) 0x211c7d VPERMT2PD	%ZMM18,%ZMM9,%ZMM26

  (109) 0x211c83 VPERMT2PD	%ZMM23,%ZMM6,%ZMM24

  (109) 0x211c89 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

  (109) 0x211c8f VPERMT2PD	%ZMM23,%ZMM10,%ZMM26

  (109) 0x211c95 VFMADD231PD	%ZMM21,%ZMM17,%ZMM24

  (109) 0x211c9b VFMADD231PD	%ZMM22,%ZMM17,%ZMM25

  (109) 0x211ca1 VFMADD231PD	%ZMM19,%ZMM17,%ZMM26

  (109) 0x211ca7 VMOVAPD	%ZMM25,%ZMM17

  (109) 0x211cad VPERMT2PD	%ZMM24,%ZMM11,%ZMM17

  (109) 0x211cb3 VMOVAPD	%ZMM24,%ZMM18

  (109) 0x211cb9 VPERMT2PD	%ZMM25,%ZMM13,%ZMM18

  (109) 0x211cbf VPERMT2PD	%ZMM25,%ZMM15,%ZMM24

  (109) 0x211cc5 VPERMT2PD	%ZMM26,%ZMM12,%ZMM17

  (109) 0x211ccb VPERMT2PD	%ZMM26,%ZMM14,%ZMM18

  (109) 0x211cd1 VPERMT2PD	%ZMM26,%ZMM16,%ZMM24

  (109) 0x211cd7 VMOVUPD	%ZMM24,(%R14,%RCX,1)

  (109) 0x211cde VMOVUPD	%ZMM18,0x40(%R14,%RCX,1)

  (109) 0x211ce6 VMOVUPD	%ZMM17,0x80(%R14,%RCX,1)

  (109) 0x211cee ADD	$0xc0,%RCX

  (109) 0x211cf5 CMP	%RCX,%R12

  (109) 0x211cf8 JNE	211c00

(107) 0x211cfe CMP	%R9,%R8

(107) 0x211d01 JE	211b30

(107) 0x211d07 TEST	$0x4,%R9B

(107) 0x211d0b JNE	211d18

(107) 0x211d0d ADD	%R8,%R15

(107) 0x211d10 MOV	%R8D,%R12D

(107) 0x211d13 JMP	211e00

(107) 0x211d18 MOV	%R9D,%R12D

(107) 0x211d1b AND	$-0x4,%R12D

(107) 0x211d1f MOV	%R8,%RCX

(107) 0x211d22 LEA	(%R12,%R15,1),%R14

(107) 0x211d26 ADD	%R8,%R15

(107) 0x211d29 SUB	%R12,%RCX

(107) 0x211d2c SAL	$0x3,%R15

(107) 0x211d30 LEA	(%R15,%R15,2),%R8

(107) 0x211d34 NOPW	%CS:(%RAX,%RAX,1)

  (110) 0x211d40 VMOVUPD	(%R11,%R8,1),%ZMM18

  (110) 0x211d47 VMOVUPD	0x40(%R11,%R8,1),%YMM19

  (110) 0x211d4f VMOVUPD	0x40(%R10,%R8,1),%YMM22

  (110) 0x211d57 VBROADCASTSD	(%RBX),%YMM17

  (110) 0x211d5d VMOVAPD	%ZMM18,%ZMM20

  (110) 0x211d63 VMOVAPD	%ZMM18,%ZMM21

  (110) 0x211d69 VPERMT2PD	%ZMM19,%ZMM0,%ZMM20

  (110) 0x211d6f VPERMT2PD	%ZMM19,%ZMM1,%ZMM21

  (110) 0x211d75 VPERMT2PD	%ZMM19,%ZMM2,%ZMM18

  (110) 0x211d7b VMOVUPD	(%R10,%R8,1),%ZMM19

  (110) 0x211d82 VMOVAPD	%ZMM19,%ZMM23

  (110) 0x211d88 VPERMT2PD	%ZMM22,%ZMM0,%ZMM23

  (110) 0x211d8e VMOVAPD	%ZMM19,%ZMM24

  (110) 0x211d94 VPERMT2PD	%ZMM22,%ZMM1,%ZMM24

  (110) 0x211d9a VPERMT2PD	%ZMM22,%ZMM2,%ZMM19

  (110) 0x211da0 VFMADD231PD	%YMM20,%YMM17,%YMM23

  (110) 0x211da6 VFMADD231PD	%YMM21,%YMM17,%YMM24

  (110) 0x211dac VFMADD231PD	%YMM18,%YMM17,%YMM19

  (110) 0x211db2 VINSERTF64X4	$0x1,%YMM24,%ZMM23,%ZMM17

  (110) 0x211db9 VMOVAPD	%ZMM17,%ZMM18

  (110) 0x211dbf VPERMT2PD	%ZMM19,%ZMM3,%ZMM18

  (110) 0x211dc5 VPERMT2PD	%ZMM19,%ZMM4,%ZMM17

  (110) 0x211dcb VMOVUPD	%ZMM17,(%R10,%R8,1)

  (110) 0x211dd2 VMOVUPD	%YMM18,0x40(%R10,%R8,1)

  (110) 0x211dda ADD	$0x60,%R8

  (110) 0x211dde ADD	$0x4,%RCX

  (110) 0x211de2 JNE	211d40

(107) 0x211de8 MOV	%R14,%R15

(107) 0x211deb CMP	%R9,%R12

(107) 0x211dee JE	211b30

(107) 0x211df4 NOPW	%CS:(%RAX,%RAX,1)

(107) 0x211e00 LEA	(%R15,%R15,2),%RCX

(107) 0x211e04 SUB	%R12D,%R9D

(107) 0x211e07 LEA	0x10(,%RCX,8),%RCX

(107) 0x211e0f NOP

  (108) 0x211e10 VMOVSD	(%RBX),%XMM17

  (108) 0x211e16 VMOVSD	-0x10(%R11,%RCX,1),%XMM18

  (108) 0x211e1e VFMADD213SD	-0x10(%R10,%RCX,1),%XMM17,%XMM18

  (108) 0x211e26 VMOVSD	%XMM18,-0x10(%R10,%RCX,1)

  (108) 0x211e2e VMOVSD	(%RBX),%XMM17

  (108) 0x211e34 VMOVSD	-0x8(%R11,%RCX,1),%XMM18

  (108) 0x211e3c VFMADD213SD	-0x8(%R10,%RCX,1),%XMM17,%XMM18

  (108) 0x211e44 VMOVSD	%XMM18,-0x8(%R10,%RCX,1)

  (108) 0x211e4c VMOVSD	(%RBX),%XMM17

  (108) 0x211e52 VMOVSD	(%R11,%RCX,1),%XMM18

  (108) 0x211e59 VFMADD213SD	(%R10,%RCX,1),%XMM17,%XMM18

  (108) 0x211e60 VMOVSD	%XMM18,(%R10,%RCX,1)

  (108) 0x211e67 ADD	$0x18,%RCX

  (108) 0x211e6b DEC	%R9D

  (108) 0x211e6e JNE	211e10

(107) 0x211e70 JMP	211b30

0x211e75 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.28+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	timestep	timestep.c:39	exec
○	main	CoMD.c:125	exec
►1.52+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	timestep	timestep.c:55	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_1

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.38 to 4.50 cycles (2.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 44% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.38 to 7.92 cycles (1.31x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1004 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	82
nb uops	83
loop length	395
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Dispatch	9.25
Overall L1	10.38

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	8%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	75%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.38 cycles. At this rate:

37% of peak load performance is reached (96.77 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.38 to 9.25 cycles (1.12x speedup).

ASM code

In the binary file, the address of the function is: 2119b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 211a47 <advanceVelocity.omp_outlined+0x97>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x3c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x2634(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212b40 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 211a56 <advanceVelocity.omp_outlined+0xa6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x2609(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 212b50 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0xd161(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xd129(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xd191(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xd1b9(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xc783(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xca8d(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xca57(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xca21(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc9eb(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc9b5(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc97f(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc949(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc913(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc8dd(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc8a7(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc871(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc83b(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV 0x18(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x78(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %R14D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x8(%RBX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 211b44 <advanceVelocity.omp_outlined+0x194>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_1

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.38 to 4.50 cycles (2.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1004 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	82
nb uops	83
loop length	395
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Dispatch	9.25
Overall L1	10.38

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	8%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	75%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.38 cycles. At this rate:

37% of peak load performance is reached (96.77 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2119b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 211a47 <advanceVelocity.omp_outlined+0x97>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x3c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x2634(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212b40 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 211a56 <advanceVelocity.omp_outlined+0xa6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x2609(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 212b50 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0xd161(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xd129(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xd191(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xd1b9(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xc783(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xca8d(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xca57(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xca21(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc9eb(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc9b5(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc97f(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc949(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc913(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc8dd(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc8a7(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc871(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc83b(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV 0x18(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x78(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %R14D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x8(%RBX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 211b44 <advanceVelocity.omp_outlined+0x194>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity.omp_outlined–	1.89	0.54
▼Loop 107 - timestep.c:72-78 - exec–	0.02	0.01
○Loop 109 - timestep.c:76-78 - exec	1.54	0.43
○Loop 110 - timestep.c:76-78 - exec	0.21	0.06
○Loop 108 - timestep.c:74-78 - exec	0.12	0.03

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