OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.36% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

[...]

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x20e660 PUSH	%RBP

0x20e661 MOV	%RSP,%RBP

0x20e664 PUSH	%R15

0x20e666 PUSH	%R14

0x20e668 PUSH	%R13

0x20e66a PUSH	%R12

0x20e66c PUSH	%RBX

0x20e66d SUB	$0x18,%RSP

0x20e671 MOV	0xc(%RDI),%R8D

0x20e675 CMP	%R8D,0x14(%RDI)

0x20e679 JLE	20e6a7

0x20e67b MOV	0x78(%RDI),%RCX

0x20e67f MOVSXD	%R8D,%RAX

0x20e682 NOPW	%CS:(%RAX,%RAX,1)

(92) 0x20e690 MOVL	$0,(%RCX,%RAX,4)

(92) 0x20e697 INC	%RAX

(92) 0x20e69a MOVSXD	0x14(%RDI),%RDX

(92) 0x20e69e CMP	%RDX,%RAX

(92) 0x20e6a1 JL	20e690

0x20e6a3 MOV	0xc(%RDI),%R8D

0x20e6a7 TEST	%R8D,%R8D

0x20e6aa JLE	20ea4c

0x20e6b0 MOV	0x78(%RDI),%R10

0x20e6b4 XOR	%EAX,%EAX

0x20e6b6 JMP	20e6cf

0x20e6b8 NOPL	(%RAX,%RAX,1)

(90) 0x20e6c0 INC	%RAX

(90) 0x20e6c3 MOVSXD	%R8D,%RCX

(90) 0x20e6c6 CMP	%RCX,%RAX

(90) 0x20e6c9 JGE	20ea4c

(90) 0x20e6cf CMPL	$0,(%R10,%RAX,4)

(90) 0x20e6d4 JLE	20e6c0

(90) 0x20e6d6 MOVSXD	%EAX,%RCX

(90) 0x20e6d9 XOR	%EDX,%EDX

(90) 0x20e6db SAL	$0x6,%RCX

(90) 0x20e6df MOV	%RCX,-0x38(%RBP)

(90) 0x20e6e3 JMP	20e700

0x20e6e5 NOPW	%CS:(%RAX,%RAX,1)

  (91) 0x20e6f0 MOV	-0x30(%RBP),%RDX

  (91) 0x20e6f4 INC	%EDX

  (91) 0x20e6f6 MOV	0x78(%RDI),%R10

  (91) 0x20e6fa CMP	%EDX,(%R10,%RAX,4)

  (91) 0x20e6fe JLE	20e6c0

  (91) 0x20e700 MOV	-0x38(%RBP),%RCX

  (91) 0x20e704 MOV	0x18(%RSI),%R11

  (91) 0x20e708 ADD	%EDX,%ECX

  (91) 0x20e70a MOVSXD	%ECX,%R9

  (91) 0x20e70d LEA	(%R9,%R9,2),%RBX

  (91) 0x20e711 VMOVSD	(%R11,%RBX,8),%XMM0

  (91) 0x20e717 VUCOMISD	0x30(%RDI),%XMM0

  (91) 0x20e71c JAE	20e750

  (91) 0x20e71e VSUBSD	0x18(%RDI),%XMM0,%XMM0

  (91) 0x20e723 MOV	(%RDI),%R12D

  (91) 0x20e726 VMULSD	0x60(%RDI),%XMM0,%XMM0

  (91) 0x20e72b VROUNDSD	$0x9,%XMM0,%XMM0,%XMM0

  (91) 0x20e731 VCVTTSD2SI	%XMM0,%R15D

  (91) 0x20e735 CMP	%R15D,%R12D

  (91) 0x20e738 JNE	20e756

  (91) 0x20e73a LEA	-0x1(%R12),%R15D

  (91) 0x20e73f JMP	20e756

0x20e741 NOPW	%CS:(%RAX,%RAX,1)

  (91) 0x20e750 MOV	(%RDI),%R12D

  (91) 0x20e753 MOV	%R12D,%R15D

  (91) 0x20e756 VMOVSD	0x8(%R11,%RBX,8),%XMM0

  (91) 0x20e75d MOV	0x4(%RDI),%R13D

  (91) 0x20e761 VSUBSD	0x20(%RDI),%XMM0,%XMM1

  (91) 0x20e766 VMULSD	0x68(%RDI),%XMM1,%XMM1

  (91) 0x20e76b VROUNDSD	$0x9,%XMM1,%XMM1,%XMM1

  (91) 0x20e771 VCVTTSD2SI	%XMM1,%R14D

  (91) 0x20e775 CMP	%R14D,%R13D

  (91) 0x20e778 JNE	20e77e

  (91) 0x20e77a LEA	-0x1(%R13),%R14D

  (91) 0x20e77e VMOVSD	0x38(%RDI),%XMM1

  (91) 0x20e783 VMOVSD	0x10(%R11,%RBX,8),%XMM2

  (91) 0x20e78a MOV	0x8(%RDI),%ECX

  (91) 0x20e78d MOV	%RDX,-0x30(%RBP)

  (91) 0x20e791 VUCOMISD	%XMM1,%XMM0

  (91) 0x20e795 CMOVAE	%R13D,%R14D

  (91) 0x20e799 VUCOMISD	0x40(%RDI),%XMM2

  (91) 0x20e79e JAE	20e800

  (91) 0x20e7a0 VSUBSD	0x28(%RDI),%XMM2,%XMM2

  (91) 0x20e7a5 VMULSD	0x70(%RDI),%XMM2,%XMM2

  (91) 0x20e7aa VROUNDSD	$0x9,%XMM2,%XMM2,%XMM2

  (91) 0x20e7b0 VCVTTSD2SI	%XMM2,%EDX

  (91) 0x20e7b4 CMP	%EDX,%ECX

  (91) 0x20e7b6 JNE	20e7bb

  (91) 0x20e7b8 LEA	-0x1(%RCX),%EDX

  (91) 0x20e7bb CMP	$-0x1,%EDX

  (91) 0x20e7be JE	20e831

  (91) 0x20e7c0 VUCOMISD	%XMM1,%XMM0

  (91) 0x20e7c4 JB	20e85a

  (91) 0x20e7ca IMUL	%ECX,%R13D

  (91) 0x20e7ce ADD	%ECX,%EDX

  (91) 0x20e7d0 ADD	$0x2,%R12D

  (91) 0x20e7d4 IMUL	%R12D,%EDX

  (91) 0x20e7d8 LEA	(%R15,%R13,2),%ECX

  (91) 0x20e7dc ADD	%R8D,%ECX

  (91) 0x20e7df LEA	0x1(%RDX,%RCX,1),%R14D

  (91) 0x20e7e4 TEST	%R14D,%R14D

  (91) 0x20e7e7 JNS	20e8d0

0x20e7ed JMP	20ea5b

0x20e7f2 NOPW	%CS:(%RAX,%RAX,1)

  (91) 0x20e800 LEA	(%RCX,%RCX,1),%EDX

  (91) 0x20e803 LEA	(%R14,%RCX,2),%ECX

  (91) 0x20e807 ADD	$0x2,%R12D

  (91) 0x20e80b ADD	%R8D,%R15D

  (91) 0x20e80e IMUL	%R13D,%EDX

  (91) 0x20e812 LEA	0x3(%R13,%RCX,1),%ECX

  (91) 0x20e817 IMUL	%R12D,%ECX

  (91) 0x20e81b ADD	%EDX,%R15D

  (91) 0x20e81e LEA	0x1(%RCX,%R15,1),%R14D

  (91) 0x20e823 TEST	%R14D,%R14D

  (91) 0x20e826 JNS	20e8d0

0x20e82c JMP	20ea5b

  (91) 0x20e831 LEA	(%RCX,%RCX,1),%EDX

  (91) 0x20e834 LEA	0x1(%R14,%RCX,2),%ECX

  (91) 0x20e839 ADD	$0x2,%R12D

  (91) 0x20e83d ADD	%R8D,%R15D

  (91) 0x20e840 IMUL	%EDX,%R13D

  (91) 0x20e844 IMUL	%R12D,%ECX

  (91) 0x20e848 ADD	%R13D,%R15D

  (91) 0x20e84b LEA	0x1(%RCX,%R15,1),%R14D

  (91) 0x20e850 TEST	%R14D,%R14D

  (91) 0x20e853 JNS	20e8d0

0x20e855 JMP	20ea5b

  (91) 0x20e85a CMP	$-0x1,%R14D

  (91) 0x20e85e JE	20e87b

  (91) 0x20e860 CMP	%R15D,%R12D

  (91) 0x20e863 JNE	20e89d

  (91) 0x20e865 ADD	%EDX,%ECX

  (91) 0x20e867 ADD	%R8D,%R14D

  (91) 0x20e86a IMUL	%ECX,%R13D

  (91) 0x20e86e ADD	%R13D,%R14D

  (91) 0x20e871 TEST	%R14D,%R14D

  (91) 0x20e874 JNS	20e8d0

0x20e876 JMP	20ea5b

  (91) 0x20e87b IMUL	%R13D,%ECX

  (91) 0x20e87f ADD	$0x2,%R12D

  (91) 0x20e883 IMUL	%EDX,%R12D

  (91) 0x20e887 LEA	(%R15,%RCX,2),%ECX

  (91) 0x20e88b ADD	%R8D,%ECX

  (91) 0x20e88e LEA	0x1(%R12,%RCX,1),%R14D

  (91) 0x20e893 TEST	%R14D,%R14D

  (91) 0x20e896 JNS	20e8d0

0x20e898 JMP	20ea5b

  (91) 0x20e89d IMUL	%EDX,%R13D

  (91) 0x20e8a1 ADD	%R14D,%R13D

  (91) 0x20e8a4 CMP	$-0x1,%R15D

  (91) 0x20e8a8 JE	20e8be

  (91) 0x20e8aa IMUL	%R13D,%R12D

  (91) 0x20e8ae ADD	%R15D,%R12D

  (91) 0x20e8b1 MOV	%R12D,%R14D

  (91) 0x20e8b4 TEST	%R14D,%R14D

  (91) 0x20e8b7 JNS	20e8d0

0x20e8b9 JMP	20ea5b

  (91) 0x20e8be ADD	%R8D,%R13D

  (91) 0x20e8c1 MOV	%R13D,%R14D

  (91) 0x20e8c4 TEST	%R14D,%R14D

  (91) 0x20e8c7 JS	20ea5b

  (91) 0x20e8cd NOPL	(%RAX)

  (91) 0x20e8d0 CMP	%R14D,0x14(%RDI)

  (91) 0x20e8d4 JLE	20ea7a

  (91) 0x20e8da MOV	%R14D,%EDX

  (91) 0x20e8dd CMP	%RDX,%RAX

  (91) 0x20e8e0 JE	20e6f0

  (91) 0x20e8e6 MOV	0x8(%RSI),%R15

  (91) 0x20e8ea MOVSXD	(%R10,%RDX,4),%R10

  (91) 0x20e8ee LEA	(%R11,%RBX,8),%RCX

  (91) 0x20e8f2 MOVSXD	%R14D,%R8

  (91) 0x20e8f5 SAL	$0x6,%R8

  (91) 0x20e8f9 MOV	(%R15,%R9,4),%EBX

  (91) 0x20e8fd ADD	%R10,%R8

  (91) 0x20e900 MOV	%EBX,(%R15,%R8,4)

  (91) 0x20e904 MOV	0x10(%RSI),%R10

  (91) 0x20e908 MOV	(%R10,%R9,4),%EBX

  (91) 0x20e90c MOV	%EBX,(%R10,%R8,4)

  (91) 0x20e910 LEA	(,%R8,8),%R10

  (91) 0x20e918 MOV	0x10(%RCX),%RBX

  (91) 0x20e91c LEA	(%R10,%R10,2),%R10

  (91) 0x20e920 MOV	%RBX,0x10(%R11,%R10,1)

  (91) 0x20e925 VMOVUPS	(%RCX),%XMM0

  (91) 0x20e929 LEA	(,%R9,8),%RCX

  (91) 0x20e931 LEA	(%RCX,%RCX,2),%RCX

  (91) 0x20e935 VMOVUPS	%XMM0,(%R11,%R10,1)

  (91) 0x20e93b MOV	0x20(%RSI),%R11

  (91) 0x20e93f MOV	0x10(%R11,%RCX,1),%RBX

  (91) 0x20e944 MOV	%RBX,0x10(%R11,%R10,1)

  (91) 0x20e949 VMOVUPS	(%R11,%RCX,1),%XMM0

  (91) 0x20e94f VMOVUPS	%XMM0,(%R11,%R10,1)

  (91) 0x20e955 MOV	0x28(%RSI),%R11

  (91) 0x20e959 MOV	0x10(%R11,%RCX,1),%RBX

  (91) 0x20e95e MOV	%RBX,0x10(%R11,%R10,1)

  (91) 0x20e963 VMOVUPD	(%R11,%RCX,1),%XMM0

  (91) 0x20e969 VMOVUPD	%XMM0,(%R11,%R10,1)

  (91) 0x20e96f MOV	0x30(%RSI),%R10

  (91) 0x20e973 MOV	(%R10,%R9,8),%R11

  (91) 0x20e977 MOV	%R11,(%R10,%R8,8)

  (91) 0x20e97b MOV	0x78(%RDI),%R8

  (91) 0x20e97f MOV	(%R8,%RDX,4),%R10D

  (91) 0x20e983 LEA	0x1(%R10),%R11D

  (91) 0x20e987 MOV	%R11D,(%R8,%RDX,4)

  (91) 0x20e98b CMP	$0x3f,%R10D

  (91) 0x20e98f JGE	20ea99

  (91) 0x20e995 MOVSXD	(%R8,%RAX,4),%RDX

  (91) 0x20e999 DEC	%RDX

  (91) 0x20e99c MOV	%EDX,(%R8,%RAX,4)

  (91) 0x20e9a0 TEST	%EDX,%EDX

  (91) 0x20e9a2 JE	20ea2a

  (91) 0x20e9a8 ADD	-0x38(%RBP),%RDX

  (91) 0x20e9ac MOV	0x8(%RSI),%R8

  (91) 0x20e9b0 MOV	(%R8,%RDX,4),%R10D

  (91) 0x20e9b4 MOV	%R10D,(%R8,%R9,4)

  (91) 0x20e9b8 MOV	0x10(%RSI),%R8

  (91) 0x20e9bc MOV	(%R8,%RDX,4),%R10D

  (91) 0x20e9c0 MOV	%R10D,(%R8,%R9,4)

  (91) 0x20e9c4 LEA	(,%RDX,8),%R8

  (91) 0x20e9cc MOV	0x18(%RSI),%R10

  (91) 0x20e9d0 LEA	(%R8,%R8,2),%R8

  (91) 0x20e9d4 MOV	0x10(%R10,%R8,1),%R11

  (91) 0x20e9d9 MOV	%R11,0x10(%R10,%RCX,1)

  (91) 0x20e9de VMOVUPS	(%R10,%R8,1),%XMM0

  (91) 0x20e9e4 VMOVUPS	%XMM0,(%R10,%RCX,1)

  (91) 0x20e9ea MOV	0x20(%RSI),%R10

  (91) 0x20e9ee MOV	0x10(%R10,%R8,1),%R11

  (91) 0x20e9f3 MOV	%R11,0x10(%R10,%RCX,1)

  (91) 0x20e9f8 VMOVUPS	(%R10,%R8,1),%XMM0

  (91) 0x20e9fe VMOVUPS	%XMM0,(%R10,%RCX,1)

  (91) 0x20ea04 MOV	0x28(%RSI),%R10

  (91) 0x20ea08 MOV	0x10(%R10,%R8,1),%R11

  (91) 0x20ea0d MOV	%R11,0x10(%R10,%RCX,1)

  (91) 0x20ea12 VMOVUPD	(%R10,%R8,1),%XMM0

  (91) 0x20ea18 VMOVUPD	%XMM0,(%R10,%RCX,1)

  (91) 0x20ea1e MOV	0x30(%RSI),%RCX

  (91) 0x20ea22 MOV	(%RCX,%RDX,8),%RDX

  (91) 0x20ea26 MOV	%RDX,(%RCX,%R9,8)

  (91) 0x20ea2a MOV	0xc(%RDI),%R8D

  (91) 0x20ea2e CMP	%R14D,%R8D

  (91) 0x20ea31 JGE	20ea35

  (91) 0x20ea33 DECL	(%RSI)

  (91) 0x20ea35 MOV	-0x30(%RBP),%RDX

  (91) 0x20ea39 MOV	0x78(%RDI),%R10

  (91) 0x20ea3d CMP	(%R10,%RAX,4),%EDX

  (91) 0x20ea41 JL	20e700

(90) 0x20ea47 JMP	20e6c0

0x20ea4c ADD	$0x18,%RSP

0x20ea50 POP	%RBX

0x20ea51 POP	%R12

0x20ea53 POP	%R13

0x20ea55 POP	%R14

0x20ea57 POP	%R15

0x20ea59 POP	%RBP

0x20ea5a RET

0x20ea5b LEA	-0xa5f1(%RIP),%RDI

0x20ea62 LEA	-0xc2e6(%RIP),%RSI

0x20ea69 LEA	-0xa943(%RIP),%RCX

0x20ea70 MOV	$0xf6,%EDX

0x20ea75 CALL	212aa0 <@plt_start@+0xe0>

0x20ea7a LEA	-0xbde1(%RIP),%RDI

0x20ea81 LEA	-0xc305(%RIP),%RSI

0x20ea88 LEA	-0xa962(%RIP),%RCX

0x20ea8f MOV	$0xf7,%EDX

0x20ea94 CALL	212aa0 <@plt_start@+0xe0>

0x20ea99 LEA	-0xc2c1(%RIP),%RDI

0x20eaa0 LEA	-0xc324(%RIP),%RSI

0x20eaa7 LEA	-0xcb03(%RIP),%RCX

0x20eaae MOV	$0x106,%EDX

0x20eab3 CALL	212aa0 <@plt_start@+0xe0>

0x20eab8 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_1

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,258-269,288-304,327-334,352,359-365,371-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.38 to 0.41 cycles (15.43x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	54
nb uops	51
loop length	263
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	5.00
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.38 cycles. At this rate:

1% of peak load performance is reached (4.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.38 to 5.00 cycles (1.27x speedup).

ASM code

In the binary file, the address of the function is: 20e660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP %R8D,0x14(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JLE 20e6a7 <updateLinkCells+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20ea4c <updateLinkCells+0x3ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 20e6cf <updateLinkCells+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
LEA -0xa5f1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc2e6(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa943(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212aa0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xbde1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc305(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa962(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212aa0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xc2c1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc324(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xcb03(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212aa0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_1

Source file and lines	linkCells.c:211-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	54
nb uops	51
loop length	263
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	5.00
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.38 cycles. At this rate:

1% of peak load performance is reached (4.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 20e660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP %R8D,0x14(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JLE 20e6a7 <updateLinkCells+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20ea4c <updateLinkCells+0x3ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 20e6cf <updateLinkCells+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20ea5b <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
LEA -0xa5f1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc2e6(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa943(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212aa0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xbde1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc305(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa962(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212aa0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xc2c1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc324(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xcb03(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 212aa0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.36	0.10
▼Loop 90 - linkCells.c:211-373 - exec–	0.00	0.04
○Loop 91 - linkCells.c:211-373 - exec	0.36	3.22
○Loop 92 - linkCells.c:384-385 - exec	0.00	0.00

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Vectorization

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Vectorization

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Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code