OV - exec - Function computeVcm.omp

	Function: computeVcm.omp_outlined	Module: exec	Source: initAtoms.c:218-228	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 218 - 228

--------------------------------------------------------------------------------

218:    #pragma omp parallel for reduction(+:v0) reduction(+:v1) reduction(+:v2) reduction(+:v3)

219:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

220:    {

221:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

222:       {

223:          v0 += s->atoms->p[iOff][0];

224:          v1 += s->atoms->p[iOff][1];

225:          v2 += s->atoms->p[iOff][2];

226:

227:          int iSpecies = s->atoms->iSpecies[iOff];

228:          v3 += s->species[iSpecies].mass;

0x20ca10 PUSH	%RBP

0x20ca11 MOV	%RSP,%RBP

0x20ca14 PUSH	%R15

0x20ca16 PUSH	%R14

0x20ca18 PUSH	%R13

0x20ca1a PUSH	%R12

0x20ca1c PUSH	%RBX

0x20ca1d SUB	$0xe8,%RSP

0x20ca24 MOV	(%RDX),%RAX

0x20ca27 MOV	0x18(%RAX),%RAX

0x20ca2b MOV	0xc(%RAX),%R14D

0x20ca2f TEST	%R14D,%R14D

0x20ca32 JLE	20d1aa

0x20ca38 MOV	(%RDI),%ESI

0x20ca3a DEC	%R14D

0x20ca3d MOV	%RDX,%RBX

0x20ca40 MOV	%RCX,-0x38(%RBP)

0x20ca44 MOV	%R8,-0x40(%RBP)

0x20ca48 MOV	%R9,-0x48(%RBP)

0x20ca4c MOVL	$0,-0x30(%RBP)

0x20ca53 MOVL	$0x1,-0x78(%RBP)

0x20ca5a MOVL	$0,-0x74(%RBP)

0x20ca61 MOV	%R14D,-0x2c(%RBP)

0x20ca65 SUB	$0x8,%RSP

0x20ca69 LEA	0x73e0(%RIP),%RDI

0x20ca70 LEA	-0x78(%RBP),%RAX

0x20ca74 LEA	-0x74(%RBP),%RCX

0x20ca78 LEA	-0x30(%RBP),%R8

0x20ca7c LEA	-0x2c(%RBP),%R9

0x20ca80 MOV	%ESI,-0x6c(%RBP)

0x20ca83 MOV	$0x22,%EDX

0x20ca88 PUSH	$0x1

0x20ca8a PUSH	$0x1

0x20ca8c PUSH	%RAX

0x20ca8d CALL	212b40 <@plt_start@+0x180>

0x20ca92 ADD	$0x20,%RSP

0x20ca96 MOV	-0x2c(%RBP),%EAX

0x20ca99 MOVSXD	-0x30(%RBP),%RDI

0x20ca9d VPXOR	%XMM10,%XMM10,%XMM10

0x20caa2 VPXOR	%XMM6,%XMM6,%XMM6

0x20caa6 VXORPD	%XMM4,%XMM4,%XMM4

0x20caaa VXORPD	%XMM7,%XMM7,%XMM7

0x20caae CMP	%R14D,%EAX

0x20cab1 CMOVL	%EAX,%R14D

0x20cab5 MOV	%R14D,-0x2c(%RBP)

0x20cab9 CMP	%R14D,%EDI

0x20cabc JLE	20cbcc

0x20cac2 MOV	-0x6c(%RBP),%R14D

0x20cac6 MOV	0x10(%RBP),%RBX

0x20caca LEA	0x7397(%RIP),%RDI

0x20cad1 VMOVSD	%XMM7,-0x68(%RBP)

0x20cad6 VMOVSD	%XMM4,-0x60(%RBP)

0x20cadb VMOVQ	%XMM6,-0x58(%RBP)

0x20cae0 VMOVQ	%XMM10,-0x50(%RBP)

0x20cae5 MOV	%R14D,%ESI

0x20cae8 VZEROUPPER

0x20caeb CALL	212b50 <@plt_start@+0x190>

0x20caf0 LEA	-0x68(%RBP),%RAX

0x20caf4 LEA	-0x60(%RBP),%R11

0x20caf8 LEA	-0x58(%RBP),%R10

0x20cafc MOV	%RAX,-0x108(%RBP)

0x20cb03 LEA	-0x50(%RBP),%RAX

0x20cb07 MOV	%R11,-0x100(%RBP)

0x20cb0e MOV	%R10,-0xf8(%RBP)

0x20cb15 MOV	%RAX,-0xf0(%RBP)

0x20cb1c SUB	$0x8,%RSP

0x20cb20 LEA	0x8a49(%RIP),%RAX

0x20cb27 LEA	0x7352(%RIP),%RDI

0x20cb2e LEA	-0x185(%RIP),%R9

0x20cb35 LEA	-0x108(%RBP),%R8

0x20cb3c MOV	$0x20,%ECX

0x20cb41 MOV	%R14D,%ESI

0x20cb44 MOV	$0x4,%EDX

0x20cb49 PUSH	%RAX

0x20cb4a CALL	212b60 <@plt_start@+0x1a0>

0x20cb4f ADD	$0x10,%RSP

0x20cb53 CMP	$0x2,%EAX

0x20cb56 JE	20d0e9

0x20cb5c CMP	$0x1,%EAX

0x20cb5f JNE	20d1aa

0x20cb65 MOV	-0x38(%RBP),%RAX

0x20cb69 VMOVSD	-0x68(%RBP),%XMM0

0x20cb6e MOV	-0x40(%RBP),%RDX

0x20cb72 MOV	-0x48(%RBP),%RCX

0x20cb76 LEA	0x7303(%RIP),%RDI

0x20cb7d MOV	%R14D,%ESI

0x20cb80 VADDSD	(%RAX),%XMM0,%XMM0

0x20cb84 MOV	-0x38(%RBP),%RAX

0x20cb88 VMOVSD	%XMM0,(%RAX)

0x20cb8c MOV	-0x40(%RBP),%RAX

0x20cb90 VMOVSD	-0x60(%RBP),%XMM0

0x20cb95 VADDSD	(%RDX),%XMM0,%XMM0

0x20cb99 LEA	0x89d0(%RIP),%RDX

0x20cba0 VMOVSD	%XMM0,(%RAX)

0x20cba4 MOV	-0x48(%RBP),%RAX

0x20cba8 VMOVSD	-0x58(%RBP),%XMM0

0x20cbad VADDSD	(%RCX),%XMM0,%XMM0

0x20cbb1 VMOVSD	%XMM0,(%RAX)

0x20cbb5 VMOVSD	-0x50(%RBP),%XMM0

0x20cbba VADDSD	(%RBX),%XMM0,%XMM0

0x20cbbe VMOVSD	%XMM0,(%RBX)

0x20cbc2 CALL	212b70 <@plt_start@+0x1b0>

0x20cbc7 JMP	20d1aa

0x20cbcc MOV	(%RBX),%R8

0x20cbcf VMOVAPD	-0x82d7(%RIP),%YMM1

0x20cbd7 VMOVAPD	-0x829f(%RIP),%YMM2

0x20cbdf VMOVAPD	-0x8307(%RIP),%YMM3

0x20cbe7 MOV	%EDI,%R11D

0x20cbea MOVSXD	%R14D,%RBX

0x20cbed SAL	$0x6,%R11D

0x20cbf1 VPXOR	%XMM5,%XMM5,%XMM5

0x20cbf5 MOV	%RBX,-0x88(%RBP)

0x20cbfc MOV	0x18(%R8),%RAX

0x20cc00 MOV	%R8,-0x98(%RBP)

0x20cc07 MOV	0x78(%RAX),%R10

0x20cc0b MOV	%R10,-0x90(%RBP)

0x20cc12 JMP	20cc3d

0x20cc14 NOPW	%CS:(%RAX,%RAX,1)

(72) 0x20cc20 VSHUFPD	$0x1,%XMM5,%XMM5,%XMM4

(72) 0x20cc25 VMOVAPD	%XMM5,%XMM7

(72) 0x20cc29 ADD	$0x40,%R11D

(72) 0x20cc2d LEA	0x1(%RDI),%RAX

(72) 0x20cc31 CMP	%RBX,%RDI

(72) 0x20cc34 MOV	%RAX,%RDI

(72) 0x20cc37 JGE	20cac2

(72) 0x20cc3d MOV	(%R10,%RDI,4),%R14D

(72) 0x20cc41 TEST	%R14D,%R14D

(72) 0x20cc44 JLE	20cc29

(72) 0x20cc46 MOV	0x20(%R8),%RCX

(72) 0x20cc4a MOV	0x28(%R8),%R9

(72) 0x20cc4e MOVSXD	%R11D,%RAX

(72) 0x20cc51 XOR	%EDX,%EDX

(72) 0x20cc53 MOV	0x10(%RCX),%R15

(72) 0x20cc57 MOV	0x20(%RCX),%RSI

(72) 0x20cc5b CMP	$0x10,%R14D

(72) 0x20cc5f JB	20d09f

(72) 0x20cc65 LEA	(,%RAX,8),%RCX

(72) 0x20cc6d MOV	%R11D,-0x70(%RBP)

(72) 0x20cc71 MOV	%RDI,-0xc8(%RBP)

(72) 0x20cc78 VMOVQ	%XMM5,%XMM4

(72) 0x20cc7c VMOVQ	%XMM6,%XMM6

(72) 0x20cc80 VMOVQ	%XMM10,%XMM10

(72) 0x20cc85 VXORPD	%XMM7,%XMM7,%XMM7

(72) 0x20cc89 VXORPD	%XMM8,%XMM8,%XMM8

(72) 0x20cc8e VXORPD	%XMM9,%XMM9,%XMM9

(72) 0x20cc93 VXORPD	%XMM11,%XMM11,%XMM11

(72) 0x20cc98 VXORPD	%XMM12,%XMM12,%XMM12

(72) 0x20cc9d VXORPD	%XMM13,%XMM13,%XMM13

(72) 0x20cca2 VXORPD	%XMM14,%XMM14,%XMM14

(72) 0x20cca7 VXORPD	%XMM15,%XMM15,%XMM15

(72) 0x20ccac VXORPD	%XMM16,%XMM16,%XMM16

(72) 0x20ccb2 VXORPD	%XMM17,%XMM17,%XMM17

(72) 0x20ccb8 VXORPD	%XMM18,%XMM18,%XMM18

(72) 0x20ccbe VXORPD	%XMM19,%XMM19,%XMM19

(72) 0x20ccc4 LEA	(%RCX,%RCX,2),%RDX

(72) 0x20ccc8 MOV	%R14D,%ECX

(72) 0x20cccb AND	$-0x10,%ECX

(72) 0x20ccce MOV	%RCX,-0xa8(%RBP)

(72) 0x20ccd5 ADD	%RAX,%RCX

(72) 0x20ccd8 SAL	$0x2,%RAX

(72) 0x20ccdc MOV	%RCX,-0xa0(%RBP)

(72) 0x20cce3 MOV	%R14D,%ECX

(72) 0x20cce6 SHR	$0x4,%ECX

(72) 0x20cce9 ADD	%RSI,%RDX

(72) 0x20ccec VPUNPCKHQDQ	-0x8064(%RIP),%XMM5,%XMM5

(72) 0x20ccf4 SAL	$0x5,%RCX

(72) 0x20ccf8 MOV	%R14,-0xc0(%RBP)

(72) 0x20ccff LEA	0x30(%R15,%RAX,1),%R14

(72) 0x20cd04 MOV	%R15,-0xb0(%RBP)

(72) 0x20cd0b XOR	%R15D,%R15D

(72) 0x20cd0e MOV	%RSI,-0xb8(%RBP)

(72) 0x20cd15 LEA	(%RCX,%RCX,2),%RCX

(72) 0x20cd19 MOV	%RCX,-0xd0(%RBP)

  (74) 0x20cd20 VMOVUPD	(%RDX,%R15,4),%ZMM20

  (74) 0x20cd27 VMOVUPD	0x40(%RDX,%R15,4),%YMM21

  (74) 0x20cd2f VMOVUPD	0x60(%RDX,%R15,4),%ZMM22

  (74) 0x20cd3a VMOVUPD	0xa0(%RDX,%R15,4),%YMM23

  (74) 0x20cd42 VMOVUPD	0xc0(%RDX,%R15,4),%ZMM24

  (74) 0x20cd4a VMOVUPD	0x120(%RDX,%R15,4),%ZMM26

  (74) 0x20cd55 VMOVUPD	0x100(%RDX,%R15,4),%YMM25

  (74) 0x20cd5d VMOVUPD	0x160(%RDX,%R15,4),%YMM27

  (74) 0x20cd65 ADD	$0x60,%R15

  (74) 0x20cd69 VMOVAPD	%ZMM20,%ZMM0

  (74) 0x20cd6f VPERMT2PD	%ZMM21,%ZMM2,%ZMM0

  (74) 0x20cd75 VMOVAPD	%ZMM20,%ZMM28

  (74) 0x20cd7b VPERMT2PD	%ZMM21,%ZMM3,%ZMM20

  (74) 0x20cd81 VPERMT2PD	%ZMM21,%ZMM1,%ZMM28

  (74) 0x20cd87 VMOVAPD	%ZMM22,%ZMM21

  (74) 0x20cd8d VPERMT2PD	%ZMM23,%ZMM2,%ZMM21

  (74) 0x20cd93 VMOVAPD	%ZMM22,%ZMM29

  (74) 0x20cd99 VPERMT2PD	%ZMM23,%ZMM1,%ZMM29

  (74) 0x20cd9f VPERMT2PD	%ZMM23,%ZMM3,%ZMM22

  (74) 0x20cda5 VMOVAPD	%ZMM24,%ZMM30

  (74) 0x20cdab VMOVAPD	%ZMM24,%ZMM23

  (74) 0x20cdb1 VPERMT2PD	%ZMM25,%ZMM1,%ZMM30

  (74) 0x20cdb7 VMOVAPD	%ZMM26,%ZMM31

  (74) 0x20cdbd VPERMT2PD	%ZMM27,%ZMM1,%ZMM31

  (74) 0x20cdc3 VPERMT2PD	%ZMM25,%ZMM2,%ZMM23

  (74) 0x20cdc9 VPERMT2PD	%ZMM25,%ZMM3,%ZMM24

  (74) 0x20cdcf VMOVAPD	%ZMM26,%ZMM25

  (74) 0x20cdd5 VPERMT2PD	%ZMM27,%ZMM2,%ZMM25

  (74) 0x20cddb VPERMT2PD	%ZMM27,%ZMM3,%ZMM26

  (74) 0x20cde1 VADDPD	%YMM5,%YMM0,%YMM5

  (74) 0x20cde5 VPMOVSXDQ	-0x30(%R14),%YMM0

  (74) 0x20cdeb VADDPD	%YMM6,%YMM20,%YMM6

  (74) 0x20cdf1 VPMOVSXDQ	-0x20(%R14),%YMM20

  (74) 0x20cdf8 VADDPD	%YMM11,%YMM21,%YMM11

  (74) 0x20cdfe VPMOVSXDQ	-0x10(%R14),%YMM21

  (74) 0x20ce05 VADDPD	%YMM4,%YMM28,%YMM4

  (74) 0x20ce0b VADDPD	%YMM7,%YMM29,%YMM7

  (74) 0x20ce11 VADDPD	%YMM8,%YMM30,%YMM8

  (74) 0x20ce17 VADDPD	%YMM9,%YMM31,%YMM9

  (74) 0x20ce1d VADDPD	%YMM12,%YMM23,%YMM12

  (74) 0x20ce23 VADDPD	%YMM13,%YMM25,%YMM13

  (74) 0x20ce29 VADDPD	%YMM14,%YMM22,%YMM14

  (74) 0x20ce2f VADDPD	%YMM15,%YMM24,%YMM15

  (74) 0x20ce35 VADDPD	%YMM16,%YMM26,%YMM16

  (74) 0x20ce3b VMOVQ	%XMM0,%RAX

  (74) 0x20ce40 VPEXTRQ	$0x1,%XMM0,-0x80(%RBP)

  (74) 0x20ce47 VEXTRACTI128	$0x1,%YMM0,%XMM0

  (74) 0x20ce4d SALQ	$0x4,-0x80(%RBP)

  (74) 0x20ce52 VMOVQ	%XMM20,-0xe8(%RBP)

  (74) 0x20ce59 VPEXTRQ	$0x1,%XMM20,-0xe0(%RBP)

  (74) 0x20ce61 VEXTRACTI32X4	$0x1,%YMM20,%XMM20

  (74) 0x20ce68 VPEXTRQ	$0x1,%XMM21,%R11

  (74) 0x20ce6f VMOVQ	%XMM21,-0xd8(%RBP)

  (74) 0x20ce76 VPEXTRQ	$0x1,%XMM0,%RBX

  (74) 0x20ce7c VMOVQ	%XMM0,%R13

  (74) 0x20ce81 VPMOVSXDQ	(%R14),%YMM0

  (74) 0x20ce86 MOV	-0x80(%RBP),%R12

  (74) 0x20ce8a VMOVQ	%XMM20,%R10

  (74) 0x20ce90 VPEXTRQ	$0x1,%XMM20,%R8

  (74) 0x20ce97 VEXTRACTI32X4	$0x1,%YMM21,%XMM20

  (74) 0x20ce9e SAL	$0x4,%RAX

  (74) 0x20cea2 SAL	$0x4,%R11

  (74) 0x20cea6 ADD	$0x40,%R14

  (74) 0x20ceaa SAL	$0x4,%R13

  (74) 0x20ceae VPEXTRQ	$0x1,%XMM20,%RSI

  (74) 0x20ceb5 VMOVQ	%XMM20,%RCX

  (74) 0x20cebb SAL	$0x4,%RBX

  (74) 0x20cebf VMOVSD	0x8(%R9,%RAX,1),%XMM21

  (74) 0x20cec7 SAL	$0x4,%R10

  (74) 0x20cecb SAL	$0x4,%R8

  (74) 0x20cecf VMOVSD	0x8(%R9,%R13,1),%XMM20

  (74) 0x20ced7 SAL	$0x4,%RCX

  (74) 0x20cedb SAL	$0x4,%RSI

  (74) 0x20cedf VMOVHPD	0x8(%R9,%RBX,1),%XMM20,%XMM20

  (74) 0x20cee7 VMOVQ	%XMM0,%RDI

  (74) 0x20ceec VPEXTRQ	$0x1,%XMM0,%R13

  (74) 0x20cef2 VEXTRACTI128	$0x1,%YMM0,%XMM0

  (74) 0x20cef8 VMOVQ	%XMM0,%RBX

  (74) 0x20cefd VPEXTRQ	$0x1,%XMM0,%RAX

  (74) 0x20cf03 VMOVHPD	0x8(%R9,%R12,1),%XMM21,%XMM0

  (74) 0x20cf0b SAL	$0x4,%RDI

  (74) 0x20cf0f SAL	$0x4,%R13

  (74) 0x20cf13 SAL	$0x4,%RBX

  (74) 0x20cf17 SAL	$0x4,%RAX

  (74) 0x20cf1b VINSERTF32X4	$0x1,%XMM20,%YMM0,%YMM0

  (74) 0x20cf22 VMOVSD	0x8(%R9,%R10,1),%XMM20

  (74) 0x20cf2a VMOVHPD	0x8(%R9,%R8,1),%XMM20,%XMM20

  (74) 0x20cf32 MOV	-0xe8(%RBP),%R8

  (74) 0x20cf39 VADDPD	%YMM0,%YMM10,%YMM10

  (74) 0x20cf3d SAL	$0x4,%R8

  (74) 0x20cf41 VMOVSD	0x8(%R9,%R8,1),%XMM0

  (74) 0x20cf48 MOV	-0xe0(%RBP),%R8

  (74) 0x20cf4f SAL	$0x4,%R8

  (74) 0x20cf53 VMOVHPD	0x8(%R9,%R8,1),%XMM0,%XMM0

  (74) 0x20cf5a VINSERTF32X4	$0x1,%XMM20,%YMM0,%YMM0

  (74) 0x20cf61 VMOVSD	0x8(%R9,%RCX,1),%XMM20

  (74) 0x20cf69 MOV	-0xd8(%RBP),%RCX

  (74) 0x20cf70 VMOVHPD	0x8(%R9,%RSI,1),%XMM20,%XMM20

  (74) 0x20cf78 VADDPD	%YMM17,%YMM0,%YMM17

  (74) 0x20cf7e SAL	$0x4,%RCX

  (74) 0x20cf82 VMOVSD	0x8(%R9,%RCX,1),%XMM0

  (74) 0x20cf89 VMOVHPD	0x8(%R9,%R11,1),%XMM0,%XMM0

  (74) 0x20cf90 VINSERTF32X4	$0x1,%XMM20,%YMM0,%YMM0

  (74) 0x20cf97 VMOVSD	0x8(%R9,%RBX,1),%XMM20

  (74) 0x20cf9f VMOVHPD	0x8(%R9,%RAX,1),%XMM20,%XMM20

  (74) 0x20cfa7 VADDPD	%YMM18,%YMM0,%YMM18

  (74) 0x20cfad VMOVSD	0x8(%R9,%RDI,1),%XMM0

  (74) 0x20cfb4 VMOVHPD	0x8(%R9,%R13,1),%XMM0,%XMM0

  (74) 0x20cfbb VINSERTF32X4	$0x1,%XMM20,%YMM0,%YMM0

  (74) 0x20cfc2 VADDPD	%YMM19,%YMM0,%YMM19

  (74) 0x20cfc8 CMP	%R15,-0xd0(%RBP)

  (74) 0x20cfcf JNE	20cd20

(72) 0x20cfd5 VADDPD	%YMM10,%YMM17,%YMM0

(72) 0x20cfdb VADDPD	%YMM4,%YMM7,%YMM4

(72) 0x20cfdf MOV	-0xc0(%RBP),%R14

(72) 0x20cfe6 MOV	-0xa8(%RBP),%RDX

(72) 0x20cfed MOV	-0xc8(%RBP),%RDI

(72) 0x20cff4 MOV	-0x98(%RBP),%R8

(72) 0x20cffb MOV	-0x90(%RBP),%R10

(72) 0x20d002 MOV	-0x70(%RBP),%R11D

(72) 0x20d006 MOV	-0x88(%RBP),%RBX

(72) 0x20d00d MOV	-0xb8(%RBP),%RSI

(72) 0x20d014 MOV	-0xb0(%RBP),%R15

(72) 0x20d01b MOV	-0xa0(%RBP),%RAX

(72) 0x20d022 VADDPD	%YMM0,%YMM18,%YMM0

(72) 0x20d028 VADDPD	%YMM4,%YMM8,%YMM4

(72) 0x20d02c VADDPD	%YMM0,%YMM19,%YMM0

(72) 0x20d032 VADDPD	%YMM4,%YMM9,%YMM4

(72) 0x20d036 VEXTRACTF128	$0x1,%YMM0,%XMM10

(72) 0x20d03c VADDPD	%XMM0,%XMM10,%XMM0

(72) 0x20d040 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM10

(72) 0x20d045 VADDSD	%XMM0,%XMM10,%XMM10

(72) 0x20d049 VADDPD	%YMM6,%YMM14,%YMM0

(72) 0x20d04d VADDPD	%YMM0,%YMM15,%YMM0

(72) 0x20d051 VADDPD	%YMM0,%YMM16,%YMM0

(72) 0x20d057 VEXTRACTF128	$0x1,%YMM0,%XMM6

(72) 0x20d05d VADDPD	%XMM6,%XMM0,%XMM0

(72) 0x20d061 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM6

(72) 0x20d066 VADDSD	%XMM6,%XMM0,%XMM6

(72) 0x20d06a VADDPD	%YMM5,%YMM11,%YMM0

(72) 0x20d06e VADDPD	%YMM0,%YMM12,%YMM0

(72) 0x20d072 VADDPD	%YMM0,%YMM13,%YMM0

(72) 0x20d076 VEXTRACTF128	$0x1,%YMM0,%XMM5

(72) 0x20d07c VADDPD	%XMM5,%XMM0,%XMM0

(72) 0x20d080 VEXTRACTF128	$0x1,%YMM4,%XMM5

(72) 0x20d086 VADDPD	%XMM5,%XMM4,%XMM4

(72) 0x20d08a VUNPCKHPD	%XMM0,%XMM4,%XMM5

(72) 0x20d08e VUNPCKLPD	%XMM0,%XMM4,%XMM0

(72) 0x20d092 VADDPD	%XMM5,%XMM0,%XMM5

(72) 0x20d096 CMP	%R14,%RDX

(72) 0x20d099 JE	20cc20

(72) 0x20d09f LEA	(%R15,%RAX,4),%RCX

(72) 0x20d0a3 LEA	(%RAX,%RAX,2),%RAX

(72) 0x20d0a7 SUB	%EDX,%R14D

(72) 0x20d0aa XOR	%EDX,%EDX

(72) 0x20d0ac LEA	0x10(%RSI,%RAX,8),%RAX

(72) 0x20d0b1 NOPW	%CS:(%RAX,%RAX,1)

  (73) 0x20d0c0 MOVSXD	(%RCX,%RDX,4),%RSI

  (73) 0x20d0c4 VADDPD	-0x10(%RAX),%XMM5,%XMM5

  (73) 0x20d0c9 VADDSD	(%RAX),%XMM6,%XMM6

  (73) 0x20d0cd INC	%RDX

  (73) 0x20d0d0 ADD	$0x18,%RAX

  (73) 0x20d0d4 SAL	$0x4,%RSI

  (73) 0x20d0d8 VADDSD	0x8(%R9,%RSI,1),%XMM10,%XMM10

  (73) 0x20d0df CMP	%EDX,%R14D

  (73) 0x20d0e2 JNE	20d0c0

(72) 0x20d0e4 JMP	20cc20

0x20d0e9 MOV	-0x38(%RBP),%RAX

0x20d0ed VMOVSD	-0x68(%RBP),%XMM0

0x20d0f2 MOV	-0x38(%RBP),%RCX

0x20d0f6 VMOVSD	(%RAX),%XMM1

0x20d0fa NOPW	(%RAX,%RAX,1)

(68) 0x20d100 VADDSD	%XMM0,%XMM1,%XMM2

(68) 0x20d104 VMOVQ	%XMM1,%RAX

(68) 0x20d109 VMOVQ	%XMM2,%RDX

(68) 0x20d10e LOCK CMPXCHG	%RDX,(%RCX)

(68) 0x20d113 VMOVQ	%RAX,%XMM1

(68) 0x20d118 JNE	20d100

0x20d11a MOV	-0x40(%RBP),%RAX

0x20d11e VMOVSD	-0x60(%RBP),%XMM0

0x20d123 MOV	-0x40(%RBP),%RCX

0x20d127 VMOVSD	(%RAX),%XMM1

0x20d12b NOPL	(%RAX,%RAX,1)

(69) 0x20d130 VADDSD	%XMM0,%XMM1,%XMM2

(69) 0x20d134 VMOVQ	%XMM1,%RAX

(69) 0x20d139 VMOVQ	%XMM2,%RDX

(69) 0x20d13e LOCK CMPXCHG	%RDX,(%RCX)

(69) 0x20d143 VMOVQ	%RAX,%XMM1

(69) 0x20d148 JNE	20d130

0x20d14a MOV	-0x48(%RBP),%RAX

0x20d14e VMOVSD	-0x58(%RBP),%XMM0

0x20d153 MOV	-0x48(%RBP),%RCX

0x20d157 VMOVSD	(%RAX),%XMM1

0x20d15b NOPL	(%RAX,%RAX,1)

(70) 0x20d160 VADDSD	%XMM0,%XMM1,%XMM2

(70) 0x20d164 VMOVQ	%XMM1,%RAX

(70) 0x20d169 VMOVQ	%XMM2,%RDX

(70) 0x20d16e LOCK CMPXCHG	%RDX,(%RCX)

(70) 0x20d173 VMOVQ	%RAX,%XMM1

(70) 0x20d178 JNE	20d160

0x20d17a VMOVSD	-0x50(%RBP),%XMM0

0x20d17f VMOVSD	(%RBX),%XMM1

0x20d183 NOPW	%CS:(%RAX,%RAX,1)

(71) 0x20d190 VADDSD	%XMM0,%XMM1,%XMM2

(71) 0x20d194 VMOVQ	%XMM1,%RAX

(71) 0x20d199 VMOVQ	%XMM2,%RCX

(71) 0x20d19e LOCK CMPXCHG	%RCX,(%RBX)

(71) 0x20d1a3 VMOVQ	%RAX,%XMM1

(71) 0x20d1a8 JNE	20d190

0x20d1aa ADD	$0xe8,%RSP

0x20d1b1 POP	%RBX

0x20d1b2 POP	%R12

0x20d1b4 POP	%R13

0x20d1b6 POP	%R14

0x20d1b8 POP	%R15

0x20d1ba POP	%RBP

0x20d1bb RET

0x20d1bc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_1

Source file and lines	initAtoms.c:218-228
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218-228.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 7.00 cycles (2.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 388 bytes (48 double precision FP elements). The binary function is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	145
nb uops	144
loop length	639
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	3
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	17.50	17.50	17.50	17.50	0.00	0.00	2.00	2.00	4.00	4.00
cycles	7.83	7.83	7.83	7.83	7.83	7.83	17.50	17.50	17.50	17.50	0.00	0.00	2.00	2.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	17.50
Overall L1	18.00

Vectorization ratios

INT

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	18%
load	15%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	13%
load	13%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Vector efficiency ratios

INT

all	10%
load	7%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	17%
load	18%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	16%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

8% of peak load performance is reached (21.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 20ca10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0xc(%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 20d1aa <computeVcm.omp_outlined+0x79a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
DEC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x74(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x73e0(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x78(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x74(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x6c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212b40 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSXD -0x30(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 20cbcc <computeVcm.omp_outlined+0x1bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x6c(%RBP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x10(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x7397(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM7,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM6,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM10,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 212b50 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
LEA -0x68(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x60(%RBP),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x58(%RBP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x50(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x8a49(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x7352(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x185(%RIP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x108(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212b60 <@plt_start@+0x1a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 20d0e9 <computeVcm.omp_outlined+0x6d9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JNE 20d1aa <computeVcm.omp_outlined+0x79a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x68(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x7303(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VADDSD (%RAX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x60(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RDX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA 0x89d0(%RIP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x58(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x50(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RBX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 212b70 <@plt_start@+0x1b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
JMP 20d1aa <computeVcm.omp_outlined+0x79a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV (%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVAPD -0x82d7(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x829f(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x8307(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
MOV %EDI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVSXD %R14D,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%R11D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RBX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%R8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 20cc3d <computeVcm.omp_outlined+0x22d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x68(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x60(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x58(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD -0x50(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_1

Source file and lines	initAtoms.c:218-228
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218-228.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 7.00 cycles (2.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 388 bytes (48 double precision FP elements). The binary function is storing 168 bytes (21 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	145
nb uops	144
loop length	639
used x86 registers	16
used mmx registers	0
used xmm registers	7
used ymm registers	3
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	17.50	17.50	17.50	17.50	0.00	0.00	2.00	2.00	4.00	4.00
cycles	7.83	7.83	7.83	7.83	7.83	7.83	17.50	17.50	17.50	17.50	0.00	0.00	2.00	2.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	17.50
Overall L1	18.00

Vectorization ratios

INT

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	18%
load	15%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	13%
load	13%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Vector efficiency ratios

INT

all	10%
load	7%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	17%
load	18%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	16%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

8% of peak load performance is reached (21.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 20ca10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0xc(%RAX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 20d1aa <computeVcm.omp_outlined+0x79a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
DEC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x74(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x73e0(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x78(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x74(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x6c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212b40 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSXD -0x30(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM7,%XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 20cbcc <computeVcm.omp_outlined+0x1bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x6c(%RBP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x10(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x7397(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM7,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM6,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM10,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 212b50 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
LEA -0x68(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x60(%RBP),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x58(%RBP),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x50(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x8a49(%RIP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x7352(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x185(%RIP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x108(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212b60 <@plt_start@+0x1a0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 20d0e9 <computeVcm.omp_outlined+0x6d9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JNE 20d1aa <computeVcm.omp_outlined+0x79a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x68(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x7303(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VADDSD (%RAX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x60(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RDX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA 0x89d0(%RIP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x58(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RCX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD -0x50(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RBX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 212b70 <@plt_start@+0x1b0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
JMP 20d1aa <computeVcm.omp_outlined+0x79a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV (%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVAPD -0x82d7(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x829f(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPD -0x8307(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.50	vect (50.0%)
MOV %EDI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOVSXD %R14D,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%R11D	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RBX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%R8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R10,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 20cc3d <computeVcm.omp_outlined+0x22d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x68(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x60(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x58(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD -0x50(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼computeVcm.omp_outlined–	0.02	0.00
▼Loop 72 - initAtoms.c:219-228 - exec–	0.00	0.00
○Loop 73 - initAtoms.c:221-228 - exec	0.01	0.00
○Loop 74 - initAtoms.c:221-228 - exec	0.01	0.00
○Loop 70 - initAtoms.c:218-218 - exec	0.00	0.00
○Loop 69 - initAtoms.c:218-218 - exec	0.00	0.00
○Loop 71 - initAtoms.c:218-218 - exec	0.00	0.00
○Loop 68 - initAtoms.c:218-218 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code