OV - exec - Loop 65

	Loop Id: 65	Module: exec	Source: initAtoms.c:221-228 [...]	Coverage: 0.01%

0x40b01c MOVSXD	(%RDI),%RSI    [1]

0x40b01f MOVSXD	0x4(%RDI),%RDX    [1]

0x40b023 MOVSXD	0x8(%RDI),%RCX    [1]

0x40b027 VMOVSD	0x8(%RAX),%XMM1    [4]

0x40b02c VMOVHPD	(%RAX),%XMM1,%XMM2    [4]

0x40b030 VMOVSD	0x20(%RAX),%XMM7    [4]

0x40b035 VMOVHPD	0x18(%RAX),%XMM7,%XMM8    [4]

0x40b03a VMOVSD	0x38(%RAX),%XMM13    [4]

0x40b03f VMOVHPD	0x30(%RAX),%XMM13,%XMM14    [4]

0x40b044 ADD	$0x10,%RDI

0x40b048 ADD	$0x60,%RAX

0x40b04c SAL	$0x4,%RSI

0x40b050 VMOVSD	0x8(%R10,%RSI,1),%XMM3    [2]

0x40b057 VMOVHPD	-0x50(%RAX),%XMM3,%XMM4    [3]

0x40b05c MOVSXD	-0x4(%RDI),%RSI    [5]

0x40b060 VINSERTF64X2	$0x1,%XMM2,%YMM4,%YMM5

0x40b067 VMOVSD	-0x10(%RAX),%XMM2    [3]

0x40b06c VMOVHPD	-0x18(%RAX),%XMM2,%XMM4    [3]

0x40b071 SAL	$0x4,%RDX

0x40b075 VADDPD	%YMM5,%YMM0,%YMM6

0x40b079 VMOVSD	0x8(%R10,%RDX,1),%XMM9    [2]

0x40b080 VMOVHPD	-0x38(%RAX),%XMM9,%XMM10    [3]

0x40b085 SAL	$0x4,%RCX

0x40b089 VINSERTF64X2	$0x1,%XMM8,%YMM10,%YMM11

0x40b090 VADDPD	%YMM11,%YMM6,%YMM12

0x40b095 VMOVSD	0x8(%R10,%RCX,1),%XMM15    [2]

0x40b09c VMOVHPD	-0x20(%RAX),%XMM15,%XMM0    [3]

0x40b0a1 VINSERTF64X2	$0x1,%XMM14,%YMM0,%YMM1

0x40b0a8 SAL	$0x4,%RSI

0x40b0ac VADDPD	%YMM1,%YMM12,%YMM3

0x40b0b0 VMOVSD	0x8(%R10,%RSI,1),%XMM5    [2]

0x40b0b7 VMOVHPD	-0x8(%RAX),%XMM5,%XMM6    [3]

0x40b0bc VINSERTF64X2	$0x1,%XMM4,%YMM6,%YMM7

0x40b0c3 VADDPD	%YMM7,%YMM3,%YMM0

0x40b0c7 CMP	%RDI,%R11

0x40b0ca JNE	40b01c

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 221 - 228

--------------------------------------------------------------------------------

221:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

[...]

228:          v3 += s->species[iSpecies].mass;

Coverage (%)	Name	Source Location	Module
►95.80+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►4.20+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	setVcm	initAtoms.c:234	exec
○	setTemperature	initAtoms.c:170	exec
○	main	CoMD.c:200	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	5.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks
Function	computeVcm._omp_fn.0
Source	initAtoms.c:221-221,initAtoms.c:228-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	6.22
CQA cycles if fully vectorized	1.44
Front-end cycles	4.38
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	5.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks
Function	computeVcm._omp_fn.0
Source	initAtoms.c:221-221,initAtoms.c:228-228
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	6.22
CQA cycles if fully vectorized	1.44
Front-end cycles	4.38
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	computeVcm._omp_fn.0
Source file and lines	initAtoms.c:221-228
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:221,228.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VINSERTF64X2: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:228
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:228
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:228
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:228

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	36
nb uops	35
loop length	180
used x86 registers	7
used mmx registers	0
used xmm registers	14
used ymm registers	10
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.38 cycles
front end	4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	4.00	4.00	4.00	4.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	4.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.38
Dispatch	5.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	20%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

7% of peak load performance is reached (18.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b01c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOVSXD (%RDI),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVSXD 0x4(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVSXD 0x8(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VMOVSD 0x8(%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RAX),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VMOVSD 0x20(%RAX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD 0x18(%RAX),%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VMOVSD 0x38(%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD 0x30(%RAX),%XMM13,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
ADD $0x10,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R10,%RSI,1),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x50(%RAX),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOVSXD -0x4(%RDI),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VINSERTF64X2 $0x1,%XMM2,%YMM4,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VMOVSD -0x10(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x18(%RAX),%XMM2,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
SAL $0x4,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDPD %YMM5,%YMM0,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVSD 0x8(%R10,%RDX,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x38(%RAX),%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VINSERTF64X2 $0x1,%XMM8,%YMM10,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VADDPD %YMM11,%YMM6,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVSD 0x8(%R10,%RCX,1),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x20(%RAX),%XMM15,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VINSERTF64X2 $0x1,%XMM14,%YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDPD %YMM1,%YMM12,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVSD 0x8(%R10,%RSI,1),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x8(%RAX),%XMM5,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VINSERTF64X2 $0x1,%XMM4,%YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VADDPD %YMM7,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
CMP %RDI,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40b01c <computeVcm._omp_fn.0+0x16c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	computeVcm._omp_fn.0
Source file and lines	initAtoms.c:221-228
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VINSERTF64X2: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:228
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:228
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:228
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:228

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	36
nb uops	35
loop length	180
used x86 registers	7
used mmx registers	0
used xmm registers	14
used ymm registers	10
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.38 cycles
front end	4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	4.00	4.00	4.00	4.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	5.00	5.00	5.00	5.00	4.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.38
Dispatch	5.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	20%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

7% of peak load performance is reached (18.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b01c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOVSXD (%RDI),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVSXD 0x4(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOVSXD 0x8(%RDI),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VMOVSD 0x8(%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RAX),%XMM1,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VMOVSD 0x20(%RAX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD 0x18(%RAX),%XMM7,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VMOVSD 0x38(%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD 0x30(%RAX),%XMM13,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
ADD $0x10,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x60,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VMOVSD 0x8(%R10,%RSI,1),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x50(%RAX),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOVSXD -0x4(%RDI),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
VINSERTF64X2 $0x1,%XMM2,%YMM4,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VMOVSD -0x10(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x18(%RAX),%XMM2,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
SAL $0x4,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDPD %YMM5,%YMM0,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVSD 0x8(%R10,%RDX,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x38(%RAX),%XMM9,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VINSERTF64X2 $0x1,%XMM8,%YMM10,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VADDPD %YMM11,%YMM6,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVSD 0x8(%R10,%RCX,1),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x20(%RAX),%XMM15,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VINSERTF64X2 $0x1,%XMM14,%YMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
VADDPD %YMM1,%YMM12,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
VMOVSD 0x8(%R10,%RSI,1),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD -0x8(%RAX),%XMM5,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VINSERTF64X2 $0x1,%XMM4,%YMM6,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VADDPD %YMM7,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (50.0%)
CMP %RDI,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 40b01c <computeVcm._omp_fn.0+0x16c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code