OV - exec - Loop 109

	Loop Id: 109	Module: exec	Source: timestep.c:110-116	Coverage: 0.02%

0x411f60 MOVSXD	(%R9),%RCX

0x411f63 TEST	%ECX,%ECX

0x411f65 JLE	412133

0x411f6b MOV	0x20(%RBX),%R14

0x411f6f ADD	%R8,%RCX

0x411f72 MOVSXD	%R8D,%RAX

0x411f75 MOV	0x28(%RBX),%RDI

0x411f79 MOV	0x10(%R14),%RSI

0x411f7d LEA	(%RSI,%RCX,4),%R11

0x411f81 LEA	(%RSI,%RAX,4),%RDX

0x411f85 MOV	0x20(%R14),%RAX

0x411f89 MOV	%R11,%RCX

0x411f8c SUB	%RDX,%RCX

0x411f8f SUB	$0x4,%RCX

0x411f93 SHR	$0x2,%RCX

0x411f97 INC	%RCX

0x411f9a ADD	%R13,%RAX

0x411f9d AND	$0x3,%ECX

0x411fa0 JE	412060

0x411fa6 CMP	$0x1,%RCX

0x411faa JE	412020

0x411fac CMP	$0x2,%RCX

0x411fb0 JE	411fe9

0x411fb2 VMOVSD	(%RAX),%XMM1

0x411fb6 VMOVSD	0x8(%RAX),%XMM2

0x411fbb VMULSD	%XMM2,%XMM2,%XMM5

0x411fbf VFMADD231SD	%XMM1,%XMM1,%XMM5

0x411fc4 MOVSXD	(%RDX),%R14

0x411fc7 VMOVSD	0x10(%RAX),%XMM6

0x411fcc ADD	$0x4,%RDX

0x411fd0 ADD	$0x18,%RAX

0x411fd4 VFMADD132SD	%XMM6,%XMM5,%XMM6

0x411fd9 SAL	$0x4,%R14

0x411fdd VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM4

0x411fe4 VFMADD231SD	%XMM6,%XMM4,%XMM0

0x411fe9 VMOVSD	(%RAX),%XMM8

0x411fed VMOVSD	0x8(%RAX),%XMM9

0x411ff2 VMULSD	%XMM9,%XMM9,%XMM10

0x411ff7 VFMADD231SD	%XMM8,%XMM8,%XMM10

0x411ffc MOVSXD	(%RDX),%RSI

0x411fff VMOVSD	0x10(%RAX),%XMM11

0x412004 ADD	$0x4,%RDX

0x412008 ADD	$0x18,%RAX

0x41200c VFMADD132SD	%XMM11,%XMM10,%XMM11

0x412011 SAL	$0x4,%RSI

0x412015 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM7

0x41201b VFMADD231SD	%XMM11,%XMM7,%XMM0

0x412020 VMOVSD	(%RAX),%XMM13

0x412024 VMOVSD	0x8(%RAX),%XMM14

0x412029 VMULSD	%XMM14,%XMM14,%XMM15

0x41202e VFMADD231SD	%XMM13,%XMM13,%XMM15

0x412033 MOVSXD	(%RDX),%RCX

0x412036 VMOVSD	0x10(%RAX),%XMM4

0x41203b ADD	$0x4,%RDX

0x41203f ADD	$0x18,%RAX

0x412043 VFMADD132SD	%XMM4,%XMM15,%XMM4

0x412048 SAL	$0x4,%RCX

0x41204c VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM12

0x412052 VFMADD231SD	%XMM4,%XMM12,%XMM0

0x412057 CMP	%RDX,%R11

0x41205a JE	412133

  (110) 0x412060 VMOVSD	(%RAX),%XMM1

  (110) 0x412064 VMOVSD	0x8(%RAX),%XMM2

  (110) 0x412069 VMULSD	%XMM2,%XMM2,%XMM6

  (110) 0x41206d VFMADD231SD	%XMM1,%XMM1,%XMM6

  (110) 0x412072 MOVSXD	(%RDX),%R14

  (110) 0x412075 VMOVSD	0x10(%RAX),%XMM7

  (110) 0x41207a VMOVSD	0x20(%RAX),%XMM9

  (110) 0x41207f VMULSD	%XMM9,%XMM9,%XMM10

  (110) 0x412084 MOVSXD	0x4(%RDX),%RSI

  (110) 0x412088 VMOVSD	0x28(%RAX),%XMM11

  (110) 0x41208d VMOVSD	0x30(%RAX),%XMM13

  (110) 0x412092 VMOVSD	0x38(%RAX),%XMM14

  (110) 0x412097 VMULSD	%XMM14,%XMM14,%XMM15

  (110) 0x41209c VFMADD231SD	%XMM13,%XMM13,%XMM15

  (110) 0x4120a1 MOVSXD	0x8(%RDX),%RCX

  (110) 0x4120a5 VMOVSD	0x40(%RAX),%XMM4

  (110) 0x4120aa VFMADD132SD	%XMM7,%XMM6,%XMM7

  (110) 0x4120af VMOVSD	0x50(%RAX),%XMM1

  (110) 0x4120b4 VMULSD	%XMM1,%XMM1,%XMM2

  (110) 0x4120b8 VMOVSD	0x58(%RAX),%XMM6

  (110) 0x4120bd ADD	$0x10,%RDX

  (110) 0x4120c1 ADD	$0x60,%RAX

  (110) 0x4120c5 SAL	$0x4,%R14

  (110) 0x4120c9 VFMADD132SD	%XMM4,%XMM15,%XMM4

  (110) 0x4120ce VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM5

  (110) 0x4120d5 VFMADD132SD	%XMM7,%XMM0,%XMM5

  (110) 0x4120da VMOVSD	-0x48(%RAX),%XMM0

  (110) 0x4120df VFMADD231SD	%XMM0,%XMM0,%XMM10

  (110) 0x4120e4 SAL	$0x4,%RSI

  (110) 0x4120e8 VDIVSD	0x8(%RDI,%RSI,1),%XMM3,%XMM8

  (110) 0x4120ee MOVSXD	-0x4(%RDX),%R14

  (110) 0x4120f2 VFMADD132SD	%XMM11,%XMM10,%XMM11

  (110) 0x4120f7 SAL	$0x4,%RCX

  (110) 0x4120fb VDIVSD	0x8(%RDI,%RCX,1),%XMM3,%XMM12

  (110) 0x412101 VFMADD132SD	%XMM11,%XMM5,%XMM8

  (110) 0x412106 VMOVSD	-0x18(%RAX),%XMM5

  (110) 0x41210b VFMADD231SD	%XMM5,%XMM5,%XMM2

  (110) 0x412110 SAL	$0x4,%R14

  (110) 0x412114 VDIVSD	0x8(%RDI,%R14,1),%XMM3,%XMM0

  (110) 0x41211b VFMADD132SD	%XMM4,%XMM8,%XMM12

  (110) 0x412120 VFMADD132SD	%XMM6,%XMM2,%XMM6

  (110) 0x412125 VFMADD132SD	%XMM6,%XMM12,%XMM0

  (110) 0x41212a CMP	%RDX,%R11

  (110) 0x41212d JNE	412060

0x412133 ADD	$0x600,%R13

0x41213a ADD	$0x4,%R9

0x41213e ADD	$0x40,%R8

0x412142 CMP	%R13,%R10

0x412145 JNE	411f60

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Coverage (%)	Name	Source Location	Module
►97.87+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.13+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	timestep	timestep.c:123	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.69
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P10, P11,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	1.50
Front-end cycles	8.13
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	65.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.28
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	10.94

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	3.69
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P10, P11,
Function	kineticEnergy._omp_fn.0
Source	timestep.c:110-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	3.25
CQA cycles if fully vectorized	1.50
Front-end cycles	8.13
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	6.00
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	12.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	66.00
Nb uops	65.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	9.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.28
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	10.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.13 cycles (1.48x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 8.13 cycles (1.48x speedup).

FMA

Detected 9 FMA (fused multiply-add) operations.

Type of elements and instruction set

15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
12: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	66
nb uops	65
loop length	280
used x86 registers	12
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	5.00	7.50	7.50	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	5.00	7.50	7.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.13
Dispatch	7.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

4% of peak load performance is reached (12.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 411f60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD (%R9),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 412133 <kineticEnergy._omp_fn.0+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x10(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%RSI,%RCX,4),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RAX,4),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV 0x20(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 412060 <kineticEnergy._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 412020 <kineticEnergy._omp_fn.0+0x140>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411fe9 <kineticEnergy._omp_fn.0+0x109>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM6,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%R14,1),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM6,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM8,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM11,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RSI,1),%XMM3,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM11,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM14,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM13,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM4,%XMM15,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RCX,1),%XMM3,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM4,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 412133 <kineticEnergy._omp_fn.0+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x600,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R13,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 411f60 <kineticEnergy._omp_fn.0+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	kineticEnergy._omp_fn.0
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 8.13 cycles (1.48x speedup).

FMA

Detected 9 FMA (fused multiply-add) operations.

Type of elements and instruction set

15 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

9: addition or subtraction (all inside FMA instructions)
12: multiply (9 inside FMA instructions)
3: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	66
nb uops	65
loop length	280
used x86 registers	12
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	5.00	7.50	7.50	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	5.00	5.00	5.00	5.00	7.50	7.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.13
Dispatch	7.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	12%
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

4% of peak load performance is reached (12.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 411f60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOVSXD (%R9),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
TEST %ECX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 412133 <kineticEnergy._omp_fn.0+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x10(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%RSI,%RCX,4),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RAX,4),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV 0x20(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R11,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SHR $0x2,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
AND $0x3,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JE 412060 <kineticEnergy._omp_fn.0+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 412020 <kineticEnergy._omp_fn.0+0x140>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 411fe9 <kineticEnergy._omp_fn.0+0x109>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM2,%XMM2,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM1,%XMM1,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM6,%XMM5,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%R14,1),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM6,%XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM9,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM8,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM11,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RSI,1),%XMM3,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM11,%XMM7,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RAX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD %XMM14,%XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	0.50	scal (12.5%)
VFMADD231SD %XMM13,%XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
MOVSXD (%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
VMOVSD 0x10(%RAX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
ADD $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x18,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VFMADD132SD %XMM4,%XMM15,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
SAL $0x4,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
VDIVSD 0x8(%RDI,%RCX,1),%XMM3,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	13	4	scal (12.5%)
VFMADD231SD %XMM4,%XMM12,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	4	0.50	scal (12.5%)
CMP %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 412133 <kineticEnergy._omp_fn.0+0x253>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x600,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $0x40,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R13,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JNE 411f60 <kineticEnergy._omp_fn.0+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code