OV - exec - Function advanceVelocity._omp

	Function: advanceVelocity._omp_fn.0	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 2.42% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x411630 PUSH	%RBP

0x411631 MOV	%RSP,%RBP

0x411634 PUSH	%R15

0x411636 PUSH	%R14

0x411638 PUSH	%R13

0x41163a PUSH	%R12

0x41163c PUSH	%RBX

0x41163d MOV	%RDI,%RBX

0x411640 AND	$-0x40,%RSP

0x411644 SUB	$0x40,%RSP

0x411648 CALL	403060 <omp_get_num_threads@plt>

0x41164d MOV	%EAX,%R12D

0x411650 CALL	403160 <omp_get_thread_num@plt>

0x411655 MOV	%EAX,%EDI

0x411657 MOV	0x10(%RBX),%EAX

0x41165a CLTD

0x41165b IDIV	%R12D

0x41165e CMP	%EDX,%EDI

0x411660 JL	411e95

0x411666 IMUL	%EAX,%EDI

0x411669 ADD	%EDI,%EDX

0x41166b ADD	%EDX,%EAX

0x41166d MOV	%EAX,0x3c(%RSP)

0x411671 CMP	%EAX,%EDX

0x411673 JGE	411aa8

0x411679 MOV	(%RBX),%R11

0x41167c MOVSXD	%EDX,%RDI

0x41167f VMOVSD	0x8(%RBX),%XMM1

0x411684 VBROADCASTSD	%XMM1,%YMM3

0x411689 LEA	(%RDI,%RDI,2),%R9

0x41168d VBROADCASTSD	%XMM1,%ZMM0

0x411693 SAL	$0x9,%R9

0x411697 MOV	0x18(%R11),%RCX

0x41169b VMOVQ	0x78(%RCX),%XMM7

(105) 0x4116a0 VMOVQ	%XMM7,%RSI

(105) 0x4116a5 MOVSXD	(%RSI,%RDI,4),%RCX

(105) 0x4116a9 TEST	%ECX,%ECX

(105) 0x4116ab JLE	411a91

(105) 0x4116b1 MOV	0x20(%R11),%R8

(105) 0x4116b5 LEA	-0x1(%RCX),%R15D

(105) 0x4116b9 MOV	%ECX,%R14D

(105) 0x4116bc MOV	0x20(%R8),%R10

(105) 0x4116c0 MOV	0x28(%R8),%R13

(105) 0x4116c4 LEA	(%R10,%R9,1),%RBX

(105) 0x4116c8 LEA	(%R13,%R9,1),%R12

(105) 0x4116cd CMP	$0x2,%R15D

(105) 0x4116d1 JBE	411ac0

(105) 0x4116d7 LEA	(%R13,%R9,1),%R12

(105) 0x4116dc LEA	0xc0(%R10,%R9,1),%RDX

(105) 0x4116e4 LEA	0xc0(%R9),%RAX

(105) 0x4116eb LEA	(%R10,%R9,1),%RBX

(105) 0x4116ef CMP	%RDX,%R12

(105) 0x4116f2 JAE	411700

(105) 0x4116f4 ADD	%R13,%RAX

(105) 0x4116f7 CMP	%RAX,%RBX

(105) 0x4116fa JB	411ac0

(105) 0x411700 MOV	%EDI,%R8D

(105) 0x411703 SAL	$0x6,%R8D

(105) 0x411707 CMP	$0x6,%R15D

(105) 0x41170b JBE	411e8b

(105) 0x411711 MOV	%ECX,%ESI

(105) 0x411713 MOV	$0x2aaaaaaaaaaaaab,%R15

(105) 0x41171d MOV	%RBX,%RAX

(105) 0x411720 MOV	%R12,%RDX

(105) 0x411723 SHR	$0x3,%ESI

(105) 0x411726 LEA	(%RSI,%RSI,2),%RSI

(105) 0x41172a SAL	$0x6,%RSI

(105) 0x41172e LEA	(%RBX,%RSI,1),%R14

(105) 0x411732 SUB	$0xc0,%RSI

(105) 0x411739 SHR	$0x6,%RSI

(105) 0x41173d IMUL	%R15,%RSI

(105) 0x411741 INC	%RSI

(105) 0x411744 AND	$0x3,%ESI

(105) 0x411747 JE	411844

(105) 0x41174d CMP	$0x1,%RSI

(105) 0x411751 JE	4117f2

(105) 0x411757 CMP	$0x2,%RSI

(105) 0x41175b JE	4117a9

(105) 0x41175d VMOVUPD	(%R12),%ZMM6

(105) 0x411764 VMOVUPD	0x40(%R12),%ZMM5

(105) 0x41176c VMOVUPD	0x80(%R12),%ZMM4

(105) 0x411774 VFMADD213PD	(%RBX),%ZMM0,%ZMM6

(105) 0x41177a VFMADD213PD	0x40(%RBX),%ZMM0,%ZMM5

(105) 0x411781 VFMADD213PD	0x80(%RBX),%ZMM0,%ZMM4

(105) 0x411788 VMOVUPD	%ZMM6,(%RBX)

(105) 0x41178e ADD	$0xc0,%RAX

(105) 0x411794 VMOVUPD	%ZMM5,0x40(%RBX)

(105) 0x41179b ADD	$0xc0,%RDX

(105) 0x4117a2 VMOVUPD	%ZMM4,0x80(%RBX)

(105) 0x4117a9 VMOVUPD	(%RDX),%ZMM2

(105) 0x4117af VMOVUPD	0x40(%RDX),%ZMM8

(105) 0x4117b6 VMOVUPD	0x80(%RDX),%ZMM9

(105) 0x4117bd VFMADD213PD	(%RAX),%ZMM0,%ZMM2

(105) 0x4117c3 VFMADD213PD	0x40(%RAX),%ZMM0,%ZMM8

(105) 0x4117ca VFMADD213PD	0x80(%RAX),%ZMM0,%ZMM9

(105) 0x4117d1 VMOVUPD	%ZMM2,(%RAX)

(105) 0x4117d7 ADD	$0xc0,%RDX

(105) 0x4117de VMOVUPD	%ZMM8,0x40(%RAX)

(105) 0x4117e5 ADD	$0xc0,%RAX

(105) 0x4117eb VMOVUPD	%ZMM9,-0x40(%RAX)

(105) 0x4117f2 VMOVUPD	(%RDX),%ZMM10

(105) 0x4117f8 VMOVUPD	0x40(%RDX),%ZMM11

(105) 0x4117ff VMOVUPD	0x80(%RDX),%ZMM12

(105) 0x411806 VFMADD213PD	(%RAX),%ZMM0,%ZMM10

(105) 0x41180c VFMADD213PD	0x40(%RAX),%ZMM0,%ZMM11

(105) 0x411813 VFMADD213PD	0x80(%RAX),%ZMM0,%ZMM12

(105) 0x41181a VMOVUPD	%ZMM10,(%RAX)

(105) 0x411820 ADD	$0xc0,%RAX

(105) 0x411826 VMOVUPD	%ZMM11,-0x80(%RAX)

(105) 0x41182d ADD	$0xc0,%RDX

(105) 0x411834 VMOVUPD	%ZMM12,-0x40(%RAX)

(105) 0x41183b CMP	%R14,%RAX

(105) 0x41183e JE	411953

  (107) 0x411844 VMOVUPD	(%RDX),%ZMM13

  (107) 0x41184a VMOVUPD	0x40(%RDX),%ZMM14

  (107) 0x411851 VMOVUPD	0x80(%RDX),%ZMM15

  (107) 0x411858 VFMADD213PD	(%RAX),%ZMM0,%ZMM13

  (107) 0x41185e VFMADD213PD	0x40(%RAX),%ZMM0,%ZMM14

  (107) 0x411865 VMOVUPD	%ZMM13,(%RAX)

  (107) 0x41186b VFMADD213PD	0x80(%RAX),%ZMM0,%ZMM15

  (107) 0x411872 ADD	$0x300,%RAX

  (107) 0x411878 VMOVUPD	%ZMM14,-0x2c0(%RAX)

  (107) 0x41187f ADD	$0x300,%RDX

  (107) 0x411886 VMOVUPD	%ZMM15,-0x280(%RAX)

  (107) 0x41188d VMOVUPD	-0x240(%RDX),%ZMM5

  (107) 0x411894 VMOVUPD	-0x200(%RDX),%ZMM6

  (107) 0x41189b VMOVUPD	-0x1c0(%RDX),%ZMM4

  (107) 0x4118a2 VFMADD213PD	-0x240(%RAX),%ZMM0,%ZMM5

  (107) 0x4118a9 VFMADD213PD	-0x200(%RAX),%ZMM0,%ZMM6

  (107) 0x4118b0 VMOVUPD	%ZMM5,-0x240(%RAX)

  (107) 0x4118b7 VFMADD213PD	-0x1c0(%RAX),%ZMM0,%ZMM4

  (107) 0x4118be VMOVUPD	%ZMM6,-0x200(%RAX)

  (107) 0x4118c5 VMOVUPD	%ZMM4,-0x1c0(%RAX)

  (107) 0x4118cc VMOVUPD	-0x180(%RDX),%ZMM8

  (107) 0x4118d3 VMOVUPD	-0x140(%RDX),%ZMM9

  (107) 0x4118da VMOVUPD	-0x100(%RDX),%ZMM2

  (107) 0x4118e1 VFMADD213PD	-0x180(%RAX),%ZMM0,%ZMM8

  (107) 0x4118e8 VFMADD213PD	-0x140(%RAX),%ZMM0,%ZMM9

  (107) 0x4118ef VMOVUPD	%ZMM8,-0x180(%RAX)

  (107) 0x4118f6 VFMADD213PD	-0x100(%RAX),%ZMM0,%ZMM2

  (107) 0x4118fd VMOVUPD	%ZMM9,-0x140(%RAX)

  (107) 0x411904 VMOVUPD	%ZMM2,-0x100(%RAX)

  (107) 0x41190b VMOVUPD	-0xc0(%RDX),%ZMM10

  (107) 0x411912 VMOVUPD	-0x80(%RDX),%ZMM11

  (107) 0x411919 VFMADD213PD	-0xc0(%RAX),%ZMM0,%ZMM10

  (107) 0x411920 VFMADD213PD	-0x80(%RAX),%ZMM0,%ZMM11

  (107) 0x411927 VMOVUPD	-0x40(%RDX),%ZMM12

  (107) 0x41192e VFMADD213PD	-0x40(%RAX),%ZMM0,%ZMM12

  (107) 0x411935 VMOVUPD	%ZMM10,-0xc0(%RAX)

  (107) 0x41193c VMOVUPD	%ZMM11,-0x80(%RAX)

  (107) 0x411943 VMOVUPD	%ZMM12,-0x40(%RAX)

  (107) 0x41194a CMP	%R14,%RAX

  (107) 0x41194d JNE	411844

(105) 0x411953 MOV	%ECX,%EAX

(105) 0x411955 AND	$-0x8,%EAX

(105) 0x411958 MOV	%EAX,%R15D

(105) 0x41195b ADD	%EAX,%R8D

(105) 0x41195e CMP	%EAX,%ECX

(105) 0x411960 JE	411a91

(105) 0x411966 MOV	%ECX,%R14D

(105) 0x411969 SUB	%EAX,%R14D

(105) 0x41196c LEA	-0x1(%R14),%EBX

(105) 0x411970 CMP	$0x2,%EBX

(105) 0x411973 JBE	4119c8

(105) 0x411975 LEA	(%R15,%R15,2),%R12

(105) 0x411979 MOV	%R14D,%R15D

(105) 0x41197c AND	$-0x4,%R15D

(105) 0x411980 LEA	(%R9,%R12,8),%RSI

(105) 0x411984 LEA	(%R10,%RSI,1),%RDX

(105) 0x411988 ADD	%R15D,%EAX

(105) 0x41198b ADD	%R13,%RSI

(105) 0x41198e ADD	%R15D,%R8D

(105) 0x411991 AND	$0x3,%R14D

(105) 0x411995 VMOVUPD	(%RSI),%YMM13

(105) 0x411999 VMOVUPD	0x20(%RSI),%YMM14

(105) 0x41199e VMOVUPD	0x40(%RSI),%YMM15

(105) 0x4119a3 VFMADD213PD	(%RDX),%YMM3,%YMM13

(105) 0x4119a8 VFMADD213PD	0x20(%RDX),%YMM3,%YMM14

(105) 0x4119ae VFMADD213PD	0x40(%RDX),%YMM3,%YMM15

(105) 0x4119b4 VMOVUPD	%YMM13,(%RDX)

(105) 0x4119b8 VMOVUPD	%YMM14,0x20(%RDX)

(105) 0x4119bd VMOVUPD	%YMM15,0x40(%RDX)

(105) 0x4119c2 JE	411a91

(105) 0x4119c8 MOVSXD	%R8D,%R8

(105) 0x4119cb LEA	0x1(%RAX),%ESI

(105) 0x4119ce LEA	(%R8,%R8,2),%R14

(105) 0x4119d2 SAL	$0x3,%R14

(105) 0x4119d6 LEA	(%R10,%R14,1),%RBX

(105) 0x4119da LEA	(%R13,%R14,1),%R12

(105) 0x4119df VMOVSD	(%R12),%XMM5

(105) 0x4119e5 VFMADD213SD	(%RBX),%XMM1,%XMM5

(105) 0x4119ea VMOVSD	%XMM5,(%RBX)

(105) 0x4119ee VMOVSD	0x8(%R12),%XMM6

(105) 0x4119f5 VFMADD213SD	0x8(%RBX),%XMM1,%XMM6

(105) 0x4119fb VMOVSD	%XMM6,0x8(%RBX)

(105) 0x411a00 VMOVSD	0x10(%R12),%XMM4

(105) 0x411a07 VFMADD213SD	0x10(%RBX),%XMM1,%XMM4

(105) 0x411a0d VMOVSD	%XMM4,0x10(%RBX)

(105) 0x411a12 CMP	%ESI,%ECX

(105) 0x411a14 JLE	411a91

(105) 0x411a16 LEA	0x18(%R10,%R14,1),%RDX

(105) 0x411a1b LEA	0x18(%R13,%R14,1),%R15

(105) 0x411a20 ADD	$0x2,%EAX

(105) 0x411a23 VMOVSD	(%R15),%XMM8

(105) 0x411a28 VFMADD213SD	(%RDX),%XMM1,%XMM8

(105) 0x411a2d VMOVSD	%XMM8,(%RDX)

(105) 0x411a31 VMOVSD	0x8(%R15),%XMM9

(105) 0x411a37 VFMADD213SD	0x8(%RDX),%XMM1,%XMM9

(105) 0x411a3d VMOVSD	%XMM9,0x8(%RDX)

(105) 0x411a42 VMOVSD	0x10(%R15),%XMM2

(105) 0x411a48 VFMADD213SD	0x10(%RDX),%XMM1,%XMM2

(105) 0x411a4e VMOVSD	%XMM2,0x10(%RDX)

(105) 0x411a53 CMP	%EAX,%ECX

(105) 0x411a55 JLE	411a91

(105) 0x411a57 LEA	0x30(%R10,%R14,1),%RCX

(105) 0x411a5c LEA	0x30(%R13,%R14,1),%R10

(105) 0x411a61 VMOVSD	(%R10),%XMM10

(105) 0x411a66 VFMADD213SD	(%RCX),%XMM1,%XMM10

(105) 0x411a6b VMOVSD	%XMM10,(%RCX)

(105) 0x411a6f VMOVSD	0x8(%R10),%XMM11

(105) 0x411a75 VFMADD213SD	0x8(%RCX),%XMM1,%XMM11

(105) 0x411a7b VMOVSD	%XMM11,0x8(%RCX)

(105) 0x411a80 VMOVSD	0x10(%R10),%XMM12

(105) 0x411a86 VFMADD213SD	0x10(%RCX),%XMM1,%XMM12

(105) 0x411a8c VMOVSD	%XMM12,0x10(%RCX)

(105) 0x411a91 INC	%RDI

(105) 0x411a94 ADD	$0x600,%R9

(105) 0x411a9b CMP	%EDI,0x3c(%RSP)

(105) 0x411a9f JG	4116a0

0x411aa5 VZEROUPPER

0x411aa8 LEA	-0x28(%RBP),%RSP

0x411aac POP	%RBX

0x411aad POP	%R12

0x411aaf POP	%R13

0x411ab1 POP	%R14

0x411ab3 POP	%R15

0x411ab5 POP	%RBP

0x411ab6 RET

0x411ab7 NOPW	(%RAX,%RAX,1)

(105) 0x411ac0 LEA	(%RCX,%RCX,2),%R8

(105) 0x411ac4 MOV	$0xaaaaaaaaaaaaaab,%RDX

(105) 0x411ace MOV	%RBX,%R13

(105) 0x411ad1 MOV	%R12,%RAX

(105) 0x411ad4 LEA	-0x18(,%R8,8),%RSI

(105) 0x411adc LEA	(%RBX,%R8,8),%R14

(105) 0x411ae0 SHR	$0x3,%RSI

(105) 0x411ae4 IMUL	%RDX,%RSI

(105) 0x411ae8 INC	%RSI

(105) 0x411aeb AND	$0x7,%ESI

(105) 0x411aee JE	411c91

(105) 0x411af4 CMP	$0x1,%RSI

(105) 0x411af8 JE	411c4e

(105) 0x411afe CMP	$0x2,%RSI

(105) 0x411b02 JE	411c14

(105) 0x411b08 CMP	$0x3,%RSI

(105) 0x411b0c JE	411bda

(105) 0x411b12 CMP	$0x4,%RSI

(105) 0x411b16 JE	411ba0

(105) 0x411b1c CMP	$0x5,%RSI

(105) 0x411b20 JE	411b66

(105) 0x411b22 CMP	$0x6,%RSI

(105) 0x411b26 JNE	411e9e

(105) 0x411b2c VMOVSD	(%RAX),%XMM5

(105) 0x411b30 ADD	$0x18,%R13

(105) 0x411b34 VFMADD213SD	-0x18(%R13),%XMM1,%XMM5

(105) 0x411b3a ADD	$0x18,%RAX

(105) 0x411b3e VMOVSD	%XMM5,-0x18(%R13)

(105) 0x411b44 VMOVSD	-0x10(%RAX),%XMM6

(105) 0x411b49 VFMADD213SD	-0x10(%R13),%XMM1,%XMM6

(105) 0x411b4f VMOVSD	%XMM6,-0x10(%R13)

(105) 0x411b55 VMOVSD	-0x8(%RAX),%XMM4

(105) 0x411b5a VFMADD213SD	-0x8(%R13),%XMM1,%XMM4

(105) 0x411b60 VMOVSD	%XMM4,-0x8(%R13)

(105) 0x411b66 VMOVSD	(%RAX),%XMM8

(105) 0x411b6a ADD	$0x18,%R13

(105) 0x411b6e VFMADD213SD	-0x18(%R13),%XMM1,%XMM8

(105) 0x411b74 ADD	$0x18,%RAX

(105) 0x411b78 VMOVSD	%XMM8,-0x18(%R13)

(105) 0x411b7e VMOVSD	-0x10(%RAX),%XMM9

(105) 0x411b83 VFMADD213SD	-0x10(%R13),%XMM1,%XMM9

(105) 0x411b89 VMOVSD	%XMM9,-0x10(%R13)

(105) 0x411b8f VMOVSD	-0x8(%RAX),%XMM2

(105) 0x411b94 VFMADD213SD	-0x8(%R13),%XMM1,%XMM2

(105) 0x411b9a VMOVSD	%XMM2,-0x8(%R13)

(105) 0x411ba0 VMOVSD	(%RAX),%XMM10

(105) 0x411ba4 ADD	$0x18,%R13

(105) 0x411ba8 VFMADD213SD	-0x18(%R13),%XMM1,%XMM10

(105) 0x411bae ADD	$0x18,%RAX

(105) 0x411bb2 VMOVSD	%XMM10,-0x18(%R13)

(105) 0x411bb8 VMOVSD	-0x10(%RAX),%XMM11

(105) 0x411bbd VFMADD213SD	-0x10(%R13),%XMM1,%XMM11

(105) 0x411bc3 VMOVSD	%XMM11,-0x10(%R13)

(105) 0x411bc9 VMOVSD	-0x8(%RAX),%XMM12

(105) 0x411bce VFMADD213SD	-0x8(%R13),%XMM1,%XMM12

(105) 0x411bd4 VMOVSD	%XMM12,-0x8(%R13)

(105) 0x411bda VMOVSD	(%RAX),%XMM13

(105) 0x411bde ADD	$0x18,%R13

(105) 0x411be2 VFMADD213SD	-0x18(%R13),%XMM1,%XMM13

(105) 0x411be8 ADD	$0x18,%RAX

(105) 0x411bec VMOVSD	%XMM13,-0x18(%R13)

(105) 0x411bf2 VMOVSD	-0x10(%RAX),%XMM14

(105) 0x411bf7 VFMADD213SD	-0x10(%R13),%XMM1,%XMM14

(105) 0x411bfd VMOVSD	%XMM14,-0x10(%R13)

(105) 0x411c03 VMOVSD	-0x8(%RAX),%XMM15

(105) 0x411c08 VFMADD213SD	-0x8(%R13),%XMM1,%XMM15

(105) 0x411c0e VMOVSD	%XMM15,-0x8(%R13)

(105) 0x411c14 VMOVSD	(%RAX),%XMM5

(105) 0x411c18 ADD	$0x18,%R13

(105) 0x411c1c VFMADD213SD	-0x18(%R13),%XMM1,%XMM5

(105) 0x411c22 ADD	$0x18,%RAX

(105) 0x411c26 VMOVSD	%XMM5,-0x18(%R13)

(105) 0x411c2c VMOVSD	-0x10(%RAX),%XMM6

(105) 0x411c31 VFMADD213SD	-0x10(%R13),%XMM1,%XMM6

(105) 0x411c37 VMOVSD	%XMM6,-0x10(%R13)

(105) 0x411c3d VMOVSD	-0x8(%RAX),%XMM4

(105) 0x411c42 VFMADD213SD	-0x8(%R13),%XMM1,%XMM4

(105) 0x411c48 VMOVSD	%XMM4,-0x8(%R13)

(105) 0x411c4e VMOVSD	(%RAX),%XMM8

(105) 0x411c52 ADD	$0x18,%R13

(105) 0x411c56 VFMADD213SD	-0x18(%R13),%XMM1,%XMM8

(105) 0x411c5c VMOVSD	%XMM8,-0x18(%R13)

(105) 0x411c62 VMOVSD	0x8(%RAX),%XMM9

(105) 0x411c67 VFMADD213SD	-0x10(%R13),%XMM1,%XMM9

(105) 0x411c6d VMOVSD	%XMM9,-0x10(%R13)

(105) 0x411c73 VMOVSD	0x10(%RAX),%XMM2

(105) 0x411c78 ADD	$0x18,%RAX

(105) 0x411c7c VFMADD213SD	-0x8(%R13),%XMM1,%XMM2

(105) 0x411c82 VMOVSD	%XMM2,-0x8(%R13)

(105) 0x411c88 CMP	%R13,%R14

(105) 0x411c8b JE	411a91

  (106) 0x411c91 VMOVSD	(%RAX),%XMM10

  (106) 0x411c95 ADD	$0xc0,%R13

  (106) 0x411c9c VFMADD213SD	-0xc0(%R13),%XMM1,%XMM10

  (106) 0x411ca5 VMOVSD	%XMM10,-0xc0(%R13)

  (106) 0x411cae VMOVSD	0x8(%RAX),%XMM11

  (106) 0x411cb3 VFMADD213SD	-0xb8(%R13),%XMM1,%XMM11

  (106) 0x411cbc VMOVSD	%XMM11,-0xb8(%R13)

  (106) 0x411cc5 VMOVSD	0x10(%RAX),%XMM12

  (106) 0x411cca VFMADD213SD	-0xb0(%R13),%XMM1,%XMM12

  (106) 0x411cd3 VMOVSD	%XMM12,-0xb0(%R13)

  (106) 0x411cdc VMOVSD	0x18(%RAX),%XMM13

  (106) 0x411ce1 VFMADD213SD	-0xa8(%R13),%XMM1,%XMM13

  (106) 0x411cea VMOVSD	%XMM13,-0xa8(%R13)

  (106) 0x411cf3 VMOVSD	0x20(%RAX),%XMM14

  (106) 0x411cf8 VFMADD213SD	-0xa0(%R13),%XMM1,%XMM14

  (106) 0x411d01 VMOVSD	%XMM14,-0xa0(%R13)

  (106) 0x411d0a VMOVSD	0x28(%RAX),%XMM15

  (106) 0x411d0f VFMADD213SD	-0x98(%R13),%XMM1,%XMM15

  (106) 0x411d18 VMOVSD	%XMM15,-0x98(%R13)

  (106) 0x411d21 VMOVSD	0x30(%RAX),%XMM5

  (106) 0x411d26 VFMADD213SD	-0x90(%R13),%XMM1,%XMM5

  (106) 0x411d2f VMOVSD	%XMM5,-0x90(%R13)

  (106) 0x411d38 VMOVSD	0x38(%RAX),%XMM6

  (106) 0x411d3d VFMADD213SD	-0x88(%R13),%XMM1,%XMM6

  (106) 0x411d46 VMOVSD	%XMM6,-0x88(%R13)

  (106) 0x411d4f VMOVSD	0x40(%RAX),%XMM4

  (106) 0x411d54 VFMADD213SD	-0x80(%R13),%XMM1,%XMM4

  (106) 0x411d5a VMOVSD	%XMM4,-0x80(%R13)

  (106) 0x411d60 VMOVSD	0x48(%RAX),%XMM8

  (106) 0x411d65 VFMADD213SD	-0x78(%R13),%XMM1,%XMM8

  (106) 0x411d6b VMOVSD	%XMM8,-0x78(%R13)

  (106) 0x411d71 VMOVSD	0x50(%RAX),%XMM9

  (106) 0x411d76 VFMADD213SD	-0x70(%R13),%XMM1,%XMM9

  (106) 0x411d7c VMOVSD	%XMM9,-0x70(%R13)

  (106) 0x411d82 VMOVSD	0x58(%RAX),%XMM2

  (106) 0x411d87 VFMADD213SD	-0x68(%R13),%XMM1,%XMM2

  (106) 0x411d8d VMOVSD	%XMM2,-0x68(%R13)

  (106) 0x411d93 VMOVSD	0x60(%RAX),%XMM10

  (106) 0x411d98 VFMADD213SD	-0x60(%R13),%XMM1,%XMM10

  (106) 0x411d9e VMOVSD	%XMM10,-0x60(%R13)

  (106) 0x411da4 VMOVSD	0x68(%RAX),%XMM11

  (106) 0x411da9 VFMADD213SD	-0x58(%R13),%XMM1,%XMM11

  (106) 0x411daf VMOVSD	%XMM11,-0x58(%R13)

  (106) 0x411db5 VMOVSD	0x70(%RAX),%XMM12

  (106) 0x411dba VFMADD213SD	-0x50(%R13),%XMM1,%XMM12

  (106) 0x411dc0 VMOVSD	%XMM12,-0x50(%R13)

  (106) 0x411dc6 VMOVSD	0x78(%RAX),%XMM13

  (106) 0x411dcb VFMADD213SD	-0x48(%R13),%XMM1,%XMM13

  (106) 0x411dd1 VMOVSD	%XMM13,-0x48(%R13)

  (106) 0x411dd7 VMOVSD	0x80(%RAX),%XMM14

  (106) 0x411ddf VFMADD213SD	-0x40(%R13),%XMM1,%XMM14

  (106) 0x411de5 VMOVSD	%XMM14,-0x40(%R13)

  (106) 0x411deb VMOVSD	0x88(%RAX),%XMM15

  (106) 0x411df3 VFMADD213SD	-0x38(%R13),%XMM1,%XMM15

  (106) 0x411df9 VMOVSD	%XMM15,-0x38(%R13)

  (106) 0x411dff VMOVSD	0x90(%RAX),%XMM5

  (106) 0x411e07 VFMADD213SD	-0x30(%R13),%XMM1,%XMM5

  (106) 0x411e0d VMOVSD	%XMM5,-0x30(%R13)

  (106) 0x411e13 VMOVSD	0x98(%RAX),%XMM6

  (106) 0x411e1b VFMADD213SD	-0x28(%R13),%XMM1,%XMM6

  (106) 0x411e21 VMOVSD	%XMM6,-0x28(%R13)

  (106) 0x411e27 VMOVSD	0xa0(%RAX),%XMM4

  (106) 0x411e2f VFMADD213SD	-0x20(%R13),%XMM1,%XMM4

  (106) 0x411e35 VMOVSD	%XMM4,-0x20(%R13)

  (106) 0x411e3b VMOVSD	0xa8(%RAX),%XMM8

  (106) 0x411e43 VFMADD213SD	-0x18(%R13),%XMM1,%XMM8

  (106) 0x411e49 VMOVSD	%XMM8,-0x18(%R13)

  (106) 0x411e4f VMOVSD	0xb0(%RAX),%XMM9

  (106) 0x411e57 VFMADD213SD	-0x10(%R13),%XMM1,%XMM9

  (106) 0x411e5d VMOVSD	%XMM9,-0x10(%R13)

  (106) 0x411e63 VMOVSD	0xb8(%RAX),%XMM2

  (106) 0x411e6b ADD	$0xc0,%RAX

  (106) 0x411e71 VFMADD213SD	-0x8(%R13),%XMM1,%XMM2

  (106) 0x411e77 VMOVSD	%XMM2,-0x8(%R13)

  (106) 0x411e7d CMP	%R13,%R14

  (106) 0x411e80 JNE	411c91

(105) 0x411e86 JMP	411a91

(105) 0x411e8b XOR	%R15D,%R15D

(105) 0x411e8e XOR	%EAX,%EAX

(105) 0x411e90 JMP	411975

0x411e95 INC	%EAX

0x411e97 XOR	%EDX,%EDX

0x411e99 JMP	411666

(105) 0x411e9e VMOVSD	(%R12),%XMM13

(105) 0x411ea4 ADD	$0x18,%R13

(105) 0x411ea8 VFMADD213SD	(%RBX),%XMM1,%XMM13

(105) 0x411ead ADD	$0x18,%RAX

(105) 0x411eb1 VMOVSD	%XMM13,(%RBX)

(105) 0x411eb5 VMOVSD	0x8(%R12),%XMM14

(105) 0x411ebc VFMADD213SD	0x8(%RBX),%XMM1,%XMM14

(105) 0x411ec2 VMOVSD	%XMM14,0x8(%RBX)

(105) 0x411ec7 VMOVSD	0x10(%R12),%XMM15

(105) 0x411ece VFMADD213SD	0x10(%RBX),%XMM1,%XMM15

(105) 0x411ed4 VMOVSD	%XMM15,0x10(%RBX)

(105) 0x411ed9 JMP	411b2c

0x411ede XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►96.87+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.30+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	timestep	timestep.c:39	exec
○	main	CoMD.c:125	exec
►1.27+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	timestep	timestep.c:71	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 1.38 cycles (4.36x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.00 to 0.44 cycles (13.71x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 3.33 cycles (1.80x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 4 bytes.

General properties

nb instructions	48
nb uops	48
loop length	150
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.33	3.33	3.33	3.33	3.33	2.00	2.00	2.00	2.00	0.00	1.00	1.00	0.00	0.00	0.00
cycles	3.33	3.33	3.33	3.33	3.33	3.33	2.00	2.00	2.00	2.00	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	6.00
Dispatch	3.33
DIV/SQRT	6.00
Overall L1	6.00

Vectorization ratios

INT

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	9%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 3.33 cycles (1.80x speedup).

ASM code

In the binary file, the address of the function is: 411630

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 411e95 <advanceVelocity._omp_fn.0+0x865>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 411aa8 <advanceVelocity._omp_fn.0+0x478>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RDI,2),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SAL $0x9,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x18(%R11),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x78(%RCX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 411666 <advanceVelocity._omp_fn.0+0x36>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 1.38 cycles (4.36x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 36 bytes. The binary function is storing 4 bytes.

General properties

nb instructions	48
nb uops	48
loop length	150
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.33	3.33	3.33	3.33	3.33	2.00	2.00	2.00	2.00	0.00	1.00	1.00	0.00	0.00	0.00
cycles	3.33	3.33	3.33	3.33	3.33	3.33	2.00	2.00	2.00	2.00	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	6.00
Dispatch	3.33
DIV/SQRT	6.00
Overall L1	6.00

Vectorization ratios

INT

all	9%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	9%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

2% of peak load performance is reached (6.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 411630

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 411e95 <advanceVelocity._omp_fn.0+0x865>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %EDX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 411aa8 <advanceVelocity._omp_fn.0+0x478>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x8(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RDI,2),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SAL $0x9,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x18(%R11),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ 0x78(%RCX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 411666 <advanceVelocity._omp_fn.0+0x36>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity._omp_fn.0–	2.42	0.62
▼Loop 105 - timestep.c:71-78 - exec–	2.41	0.51
○Loop 107 - timestep.c:74-78 - exec	0.01	0.01
○Loop 106 - timestep.c:74-78 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code