OV - exec - Function advancePosition._omp

	Function: advancePosition._omp_fn.0	Module: exec	Source: timestep.c:85-94	Coverage (incl. loops): 2.06% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

0x411330 PUSH	%RBP

0x411331 MOV	%RSP,%RBP

0x411334 PUSH	%R13

0x411336 PUSH	%R12

0x411338 PUSH	%RBX

0x411339 SUB	$0x8,%RSP

0x41133d MOV	%RDI,%RBX

0x411340 CALL	403060 <omp_get_num_threads@plt>

0x411345 MOV	%EAX,%R12D

0x411348 CALL	403160 <omp_get_thread_num@plt>

0x41134d MOV	%EAX,%ECX

0x41134f MOV	0x10(%RBX),%EAX

0x411352 CLTD

0x411353 IDIV	%R12D

0x411356 CMP	%EDX,%ECX

0x411358 JL	411623

0x41135e IMUL	%EAX,%ECX

0x411361 ADD	%ECX,%EDX

0x411363 LEA	(%RAX,%RDX,1),%ESI

0x411366 CMP	%ESI,%EDX

0x411368 JGE	411618

0x41136e MOV	(%RBX),%R13

0x411371 MOVSXD	%EDX,%R8

0x411374 MOV	%EAX,%R11D

0x411377 VMOVSD	0x8(%RBX),%XMM0

0x41137c ADD	%R8,%R11

0x41137f VMOVSD	0x2c89(%RIP),%XMM2

0x411387 LEA	(%R11,%R11,2),%R11

0x41138b SAL	$0x9,%R11

0x41138f MOV	0x18(%R13),%RDI

0x411393 MOV	0x78(%RDI),%R9

0x411397 LEA	(%R8,%R8,2),%RDI

0x41139b SAL	$0x9,%RDI

0x41139f LEA	(%R9,%R8,4),%R10

0x4113a3 MOV	%R8,%R9

0x4113a6 SAL	$0x6,%R9

0x4113aa NOPW	(%RAX,%RAX,1)

(103) 0x4113b0 MOVSXD	(%R10),%RSI

(103) 0x4113b3 TEST	%ESI,%ESI

(103) 0x4113b5 JLE	411600

(103) 0x4113bb MOV	0x20(%R13),%R12

(103) 0x4113bf ADD	%R9,%RSI

(103) 0x4113c2 MOVSXD	%R9D,%RCX

(103) 0x4113c5 MOV	0x28(%R13),%RBX

(103) 0x4113c9 MOV	0x10(%R12),%R8

(103) 0x4113ce MOV	0x18(%R12),%RAX

(103) 0x4113d3 MOV	0x20(%R12),%RDX

(103) 0x4113d8 LEA	(%R8,%RCX,4),%RCX

(103) 0x4113dc LEA	(%R8,%RSI,4),%R8

(103) 0x4113e0 ADD	%RDI,%RAX

(103) 0x4113e3 ADD	%RDI,%RDX

(103) 0x4113e6 MOV	%R8,%RSI

(103) 0x4113e9 SUB	%RCX,%RSI

(103) 0x4113ec SUB	$0x4,%RSI

(103) 0x4113f0 SHR	$0x2,%RSI

(103) 0x4113f4 INC	%RSI

(103) 0x4113f7 AND	$0x3,%ESI

(103) 0x4113fa JE	4114f3

(103) 0x411400 CMP	$0x1,%RSI

(103) 0x411404 JE	4114a1

(103) 0x41140a CMP	$0x2,%RSI

(103) 0x41140e JE	411459

(103) 0x411410 MOVSXD	(%RCX),%R12

(103) 0x411413 VMULSD	(%RDX),%XMM0,%XMM3

(103) 0x411417 ADD	$0x4,%RCX

(103) 0x41141b ADD	$0x18,%RAX

(103) 0x41141f ADD	$0x18,%RDX

(103) 0x411423 SAL	$0x4,%R12

(103) 0x411427 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM1

(103) 0x41142e VFMADD213SD	-0x18(%RAX),%XMM1,%XMM3

(103) 0x411434 VMOVSD	%XMM3,-0x18(%RAX)

(103) 0x411439 VMULSD	-0x10(%RDX),%XMM0,%XMM4

(103) 0x41143e VFMADD213SD	-0x10(%RAX),%XMM1,%XMM4

(103) 0x411444 VMOVSD	%XMM4,-0x10(%RAX)

(103) 0x411449 VMULSD	-0x8(%RDX),%XMM0,%XMM5

(103) 0x41144e VFMADD213SD	-0x8(%RAX),%XMM5,%XMM1

(103) 0x411454 VMOVSD	%XMM1,-0x8(%RAX)

(103) 0x411459 MOVSXD	(%RCX),%RSI

(103) 0x41145c VMULSD	(%RDX),%XMM0,%XMM7

(103) 0x411460 ADD	$0x4,%RCX

(103) 0x411464 ADD	$0x18,%RAX

(103) 0x411468 ADD	$0x18,%RDX

(103) 0x41146c SAL	$0x4,%RSI

(103) 0x411470 VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM6

(103) 0x411476 VFMADD213SD	-0x18(%RAX),%XMM6,%XMM7

(103) 0x41147c VMOVSD	%XMM7,-0x18(%RAX)

(103) 0x411481 VMULSD	-0x10(%RDX),%XMM0,%XMM8

(103) 0x411486 VFMADD213SD	-0x10(%RAX),%XMM6,%XMM8

(103) 0x41148c VMOVSD	%XMM8,-0x10(%RAX)

(103) 0x411491 VMULSD	-0x8(%RDX),%XMM0,%XMM9

(103) 0x411496 VFMADD213SD	-0x8(%RAX),%XMM9,%XMM6

(103) 0x41149c VMOVSD	%XMM6,-0x8(%RAX)

(103) 0x4114a1 MOVSXD	(%RCX),%R12

(103) 0x4114a4 ADD	$0x4,%RCX

(103) 0x4114a8 VMULSD	(%RDX),%XMM0,%XMM11

(103) 0x4114ac ADD	$0x18,%RAX

(103) 0x4114b0 ADD	$0x18,%RDX

(103) 0x4114b4 SAL	$0x4,%R12

(103) 0x4114b8 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM10

(103) 0x4114bf VFMADD213SD	-0x18(%RAX),%XMM10,%XMM11

(103) 0x4114c5 VMOVSD	%XMM11,-0x18(%RAX)

(103) 0x4114ca VMULSD	-0x10(%RDX),%XMM0,%XMM12

(103) 0x4114cf VFMADD213SD	-0x10(%RAX),%XMM10,%XMM12

(103) 0x4114d5 VMOVSD	%XMM12,-0x10(%RAX)

(103) 0x4114da VMULSD	-0x8(%RDX),%XMM0,%XMM13

(103) 0x4114df VFMADD213SD	-0x8(%RAX),%XMM13,%XMM10

(103) 0x4114e5 VMOVSD	%XMM10,-0x8(%RAX)

(103) 0x4114ea CMP	%RCX,%R8

(103) 0x4114ed JE	411600

  (104) 0x4114f3 MOVSXD	(%RCX),%RSI

  (104) 0x4114f6 MOVSXD	0x4(%RCX),%R12

  (104) 0x4114fa VMULSD	(%RDX),%XMM0,%XMM15

  (104) 0x4114fe ADD	$0x10,%RCX

  (104) 0x411502 ADD	$0x60,%RAX

  (104) 0x411506 ADD	$0x60,%RDX

  (104) 0x41150a SAL	$0x4,%RSI

  (104) 0x41150e VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM14

  (104) 0x411514 MOVSXD	-0x8(%RCX),%RSI

  (104) 0x411518 VFMADD213SD	-0x60(%RAX),%XMM14,%XMM15

  (104) 0x41151e VMOVSD	%XMM15,-0x60(%RAX)

  (104) 0x411523 VMULSD	-0x58(%RDX),%XMM0,%XMM1

  (104) 0x411528 VFMADD213SD	-0x58(%RAX),%XMM14,%XMM1

  (104) 0x41152e VMOVSD	%XMM1,-0x58(%RAX)

  (104) 0x411533 VMULSD	-0x50(%RDX),%XMM0,%XMM3

  (104) 0x411538 SAL	$0x4,%R12

  (104) 0x41153c VFMADD213SD	-0x50(%RAX),%XMM3,%XMM14

  (104) 0x411542 VMOVSD	%XMM14,-0x50(%RAX)

  (104) 0x411547 VMULSD	-0x48(%RDX),%XMM0,%XMM5

  (104) 0x41154c VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM4

  (104) 0x411553 VFMADD213SD	-0x48(%RAX),%XMM4,%XMM5

  (104) 0x411559 VMOVSD	%XMM5,-0x48(%RAX)

  (104) 0x41155e VMULSD	-0x40(%RDX),%XMM0,%XMM6

  (104) 0x411563 SAL	$0x4,%RSI

  (104) 0x411567 VFMADD213SD	-0x40(%RAX),%XMM4,%XMM6

  (104) 0x41156d VMOVSD	%XMM6,-0x40(%RAX)

  (104) 0x411572 VMULSD	-0x38(%RDX),%XMM0,%XMM7

  (104) 0x411577 VFMADD213SD	-0x38(%RAX),%XMM7,%XMM4

  (104) 0x41157d VMOVSD	%XMM4,-0x38(%RAX)

  (104) 0x411582 VMULSD	-0x30(%RDX),%XMM0,%XMM9

  (104) 0x411587 VDIVSD	0x8(%RBX,%RSI,1),%XMM2,%XMM8

  (104) 0x41158d VFMADD213SD	-0x30(%RAX),%XMM8,%XMM9

  (104) 0x411593 VMOVSD	%XMM9,-0x30(%RAX)

  (104) 0x411598 VMULSD	-0x28(%RDX),%XMM0,%XMM10

  (104) 0x41159d VFMADD213SD	-0x28(%RAX),%XMM8,%XMM10

  (104) 0x4115a3 VMOVSD	%XMM10,-0x28(%RAX)

  (104) 0x4115a8 VMULSD	-0x20(%RDX),%XMM0,%XMM11

  (104) 0x4115ad VFMADD213SD	-0x20(%RAX),%XMM11,%XMM8

  (104) 0x4115b3 VMOVSD	%XMM8,-0x20(%RAX)

  (104) 0x4115b8 MOVSXD	-0x4(%RCX),%R12

  (104) 0x4115bc VMULSD	-0x18(%RDX),%XMM0,%XMM13

  (104) 0x4115c1 SAL	$0x4,%R12

  (104) 0x4115c5 VDIVSD	0x8(%RBX,%R12,1),%XMM2,%XMM12

  (104) 0x4115cc VFMADD213SD	-0x18(%RAX),%XMM12,%XMM13

  (104) 0x4115d2 VMOVSD	%XMM13,-0x18(%RAX)

  (104) 0x4115d7 VMULSD	-0x10(%RDX),%XMM0,%XMM14

  (104) 0x4115dc VFMADD213SD	-0x10(%RAX),%XMM12,%XMM14

  (104) 0x4115e2 VMOVSD	%XMM14,-0x10(%RAX)

  (104) 0x4115e7 VMULSD	-0x8(%RDX),%XMM0,%XMM15

  (104) 0x4115ec VFMADD213SD	-0x8(%RAX),%XMM15,%XMM12

  (104) 0x4115f2 VMOVSD	%XMM12,-0x8(%RAX)

  (104) 0x4115f7 CMP	%RCX,%R8

  (104) 0x4115fa JNE	4114f3

(103) 0x411600 ADD	$0x600,%RDI

(103) 0x411607 ADD	$0x4,%R10

(103) 0x41160b ADD	$0x40,%R9

(103) 0x41160f CMP	%RDI,%R11

(103) 0x411612 JNE	4113b0

0x411618 ADD	$0x8,%RSP

0x41161c POP	%RBX

0x41161d POP	%R12

0x41161f POP	%R13

0x411621 POP	%RBP

0x411622 RET

0x411623 INC	%EAX

0x411625 XOR	%EDX,%EDX

0x411627 JMP	41135e

0x41162c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.85+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.66+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	timestep	timestep.c:85	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 0.88 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.00 to 0.40 cycles (15.06x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	47
nb uops	47
loop length	152
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	5.88
Dispatch	4.00
DIV/SQRT	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

2% of peak load performance is reached (7.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411330

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 411623 <advancePosition._omp_fn.0+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 411618 <advancePosition._omp_fn.0+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x2c89(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R11,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x18(%R13),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R8,%R8,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R9,%R8,4),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 41135e <advancePosition._omp_fn.0+0x2e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 0.88 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:86

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes.

General properties

nb instructions	47
nb uops	47
loop length	152
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.88 cycles
front end	5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	5.88
Dispatch	4.00
DIV/SQRT	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

2% of peak load performance is reached (7.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411330

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x10(%RBX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 411623 <advancePosition._omp_fn.0+0x2f3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 411618 <advancePosition._omp_fn.0+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD 0x8(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSD 0x2c89(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R11,2),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV 0x18(%R13),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%R8,%R8,2),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R9,%R8,4),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 41135e <advancePosition._omp_fn.0+0x2e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advancePosition._omp_fn.0–	2.06	0.53
▼Loop 103 - timestep.c:88-94 - exec–	0.31	0.07
○Loop 104 - timestep.c:88-94 - exec	1.75	0.37

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code