OV - exec - Function mkSeed

	Function: mkSeed	Module: exec	Source: random.c:45-75 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 45 - 75

--------------------------------------------------------------------------------

45:    *seed *= UINT64_C(437799614237992725);

46:    *seed %= UINT64_C(2305843009213693951);

[...]

68:    uint32_t s2 = (id+callSite) * UINT32_C(2654435761);

69:

70:    uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2;

71:    for (unsigned jj=0; jj<10; ++jj)

72:       lcg61(&iSeed);

73:

74:    return iSeed;

75: }

0x411180 IMUL	$-0x61c8864f,%EDI,%ECX

0x411186 ADD	%ESI,%EDI

0x411188 MOV	$0x613606df9756715,%R8

0x411192 MOV	$0x9,%ESI

0x411197 IMUL	$-0x61c8864f,%EDI,%EDI

0x41119d SAL	$0x20,%RCX

0x4111a1 ADD	%RDI,%RCX

0x4111a4 IMUL	%R8,%RCX

0x4111a8 MOV	%RCX,%RAX

0x4111ab MOV	%RCX,%R9

0x4111ae MUL	%RSI

0x4111b1 SUB	%RDX,%R9

0x4111b4 SHR	$0x1,%R9

0x4111b7 ADD	%R9,%RDX

0x4111ba SHR	$0x3c,%RDX

0x4111be MOV	%RDX,%R10

0x4111c1 SAL	$0x3d,%R10

0x4111c5 SUB	%RDX,%R10

0x4111c8 SUB	%R10,%RCX

0x4111cb IMUL	%R8,%RCX

0x4111cf MOV	%RCX,%RAX

0x4111d2 MOV	%RCX,%R11

0x4111d5 MUL	%RSI

0x4111d8 SUB	%RDX,%R11

0x4111db SHR	$0x1,%R11

0x4111de ADD	%R11,%RDX

0x4111e1 SHR	$0x3c,%RDX

0x4111e5 MOV	%RDX,%RDI

0x4111e8 SAL	$0x3d,%RDI

0x4111ec SUB	%RDX,%RDI

0x4111ef SUB	%RDI,%RCX

0x4111f2 IMUL	%R8,%RCX

0x4111f6 MOV	%RCX,%RAX

0x4111f9 MOV	%RCX,%R9

0x4111fc MUL	%RSI

0x4111ff SUB	%RDX,%R9

0x411202 SHR	$0x1,%R9

0x411205 ADD	%R9,%RDX

0x411208 SHR	$0x3c,%RDX

0x41120c MOV	%RDX,%R10

0x41120f SAL	$0x3d,%R10

0x411213 SUB	%RDX,%R10

0x411216 SUB	%R10,%RCX

0x411219 IMUL	%R8,%RCX

0x41121d MOV	%RCX,%RAX

0x411220 MOV	%RCX,%R11

0x411223 MUL	%RSI

0x411226 SUB	%RDX,%R11

0x411229 SHR	$0x1,%R11

0x41122c ADD	%R11,%RDX

0x41122f SHR	$0x3c,%RDX

0x411233 MOV	%RDX,%RDI

0x411236 SAL	$0x3d,%RDI

0x41123a SUB	%RDX,%RDI

0x41123d SUB	%RDI,%RCX

0x411240 IMUL	%R8,%RCX

0x411244 MOV	%RCX,%RAX

0x411247 MOV	%RCX,%R9

0x41124a MUL	%RSI

0x41124d SUB	%RDX,%R9

0x411250 SHR	$0x1,%R9

0x411253 ADD	%R9,%RDX

0x411256 SHR	$0x3c,%RDX

0x41125a MOV	%RDX,%R10

0x41125d SAL	$0x3d,%R10

0x411261 SUB	%RDX,%R10

0x411264 SUB	%R10,%RCX

0x411267 IMUL	%R8,%RCX

0x41126b MOV	%RCX,%RAX

0x41126e MOV	%RCX,%R11

0x411271 MUL	%RSI

0x411274 SUB	%RDX,%R11

0x411277 SHR	$0x1,%R11

0x41127a ADD	%R11,%RDX

0x41127d SHR	$0x3c,%RDX

0x411281 MOV	%RDX,%RDI

0x411284 SAL	$0x3d,%RDI

0x411288 SUB	%RDX,%RDI

0x41128b SUB	%RDI,%RCX

0x41128e IMUL	%R8,%RCX

0x411292 MOV	%RCX,%RAX

0x411295 MOV	%RCX,%R9

0x411298 MUL	%RSI

0x41129b SUB	%RDX,%R9

0x41129e SHR	$0x1,%R9

0x4112a1 ADD	%R9,%RDX

0x4112a4 SHR	$0x3c,%RDX

0x4112a8 MOV	%RDX,%R10

0x4112ab SAL	$0x3d,%R10

0x4112af SUB	%RDX,%R10

0x4112b2 SUB	%R10,%RCX

0x4112b5 IMUL	%R8,%RCX

0x4112b9 MOV	%RCX,%RAX

0x4112bc MOV	%RCX,%R11

0x4112bf MUL	%RSI

0x4112c2 SUB	%RDX,%R11

0x4112c5 SHR	$0x1,%R11

0x4112c8 ADD	%R11,%RDX

0x4112cb SHR	$0x3c,%RDX

0x4112cf MOV	%RDX,%RDI

0x4112d2 SAL	$0x3d,%RDI

0x4112d6 SUB	%RDX,%RDI

0x4112d9 SUB	%RDI,%RCX

0x4112dc IMUL	%R8,%RCX

0x4112e0 MOV	%RCX,%RAX

0x4112e3 MOV	%RCX,%R9

0x4112e6 MUL	%RSI

0x4112e9 SUB	%RDX,%R9

0x4112ec SHR	$0x1,%R9

0x4112ef ADD	%R9,%RDX

0x4112f2 SHR	$0x3c,%RDX

0x4112f6 MOV	%RDX,%R10

0x4112f9 SAL	$0x3d,%R10

0x4112fd SUB	%RDX,%R10

0x411300 SUB	%R10,%RCX

0x411303 IMUL	%R8,%RCX

0x411307 MOV	%RCX,%RAX

0x41130a MOV	%RCX,%R8

0x41130d MUL	%RSI

0x411310 MOV	%RCX,%RAX

0x411313 SUB	%RDX,%R8

0x411316 SHR	$0x1,%R8

0x411319 ADD	%R8,%RDX

0x41131c SHR	$0x3c,%RDX

0x411320 MOV	%RDX,%RSI

0x411323 SAL	$0x3d,%RSI

0x411327 SUB	%RDX,%RSI

0x41132a SUB	%RSI,%RAX

0x41132d RET

0x41132e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►66.67+	randomDisplacements._omp_fn.0	initAtoms.c:200	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►30.34+	setTemperature._omp_fn.0	initAtoms.c:160	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.25+	randomDisplacements._omp_fn.0	initAtoms.c:200	exec
○	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	randomDisplacements	initAtoms.c:194	exec
○	main	CoMD.c:202	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_0

Source file and lines	random.c:45-75
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-46,68-75.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.00 to 2.16 cycles (8.35x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	139
loop length	430
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.38 cycles
front end	17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.38
Dispatch	18.00
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
IMUL $-0x61c8864f,%EDI,%ECX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
ADD %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV $0x613606df9756715,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
MOV $0x9,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL $-0x61c8864f,%EDI,%EDI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
SAL $0x20,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R8	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SUB %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
RET	1	0	0	0	0.33	0.33	0.33	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_0

Source file and lines	random.c:45-75
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:45-46,68-75.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	129
nb uops	139
loop length	430
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.38 cycles
front end	17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.38
Dispatch	18.00
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 411180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
IMUL $-0x61c8864f,%EDI,%ECX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
ADD %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV $0x613606df9756715,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
MOV $0x9,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL $-0x61c8864f,%EDI,%EDI	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
SAL $0x20,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R11	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R11,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
SUB %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R9	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%R10	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SUB %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %R8,%RCX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MUL %RSI	2	0.67	0.67	0.67	0	0	0	3-4	3	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x1,%R8	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
ADD %R8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3d,%RSI	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
SUB %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SUB %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
RET	1	0	0	0	0.33	0.33	0.33	1	0.50	N/A

Name	Coverage (%)	Time (s)
○mkSeed	0.02	0.01

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Vectorization

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Matching between your function (in the source code) and the binary function

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Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code