OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.59% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

366:    {

367:       if (iy == gridSize[1]) iy = gridSize[1] - 1;

368:    }

369:    else

370:       iy = gridSize[1];

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40d670 PUSH	%RBP

0x40d671 MOV	%RSP,%RBP

0x40d674 PUSH	%R15

0x40d676 PUSH	%R14

0x40d678 PUSH	%R13

0x40d67a PUSH	%R12

0x40d67c PUSH	%RBX

0x40d67d MOV	%RDI,%R14

0x40d680 SUB	$0x28,%RSP

0x40d684 MOVSXD	0xc(%RDI),%RAX

0x40d688 MOV	%RSI,-0x48(%RBP)

0x40d68c CMP	0x14(%RDI),%EAX

0x40d68f JGE	40d6b4

0x40d691 MOV	0x78(%RDI),%RDX

0x40d695 NOPW	%CS:(%RAX,%RAX,1)

(86) 0x40d6a0 MOVL	$0,(%RDX,%RAX,4)

(86) 0x40d6a7 INC	%RAX

(86) 0x40d6aa CMP	%EAX,0x14(%R14)

(86) 0x40d6ae JG	40d6a0

0x40d6b0 MOV	0xc(%R14),%EAX

0x40d6b4 TEST	%EAX,%EAX

0x40d6b6 JLE	40d85e

0x40d6bc MOV	0x78(%R14),%R10

0x40d6c0 XOR	%R15D,%R15D

0x40d6c3 NOPW	%CS:(%RAX,%RAX,1)

0x40d6ce XCHG	%AX,%AX

(83) 0x40d6d0 MOV	(%R10,%R15,4),%ECX

(83) 0x40d6d4 MOV	%R15D,%R12D

(83) 0x40d6d7 LEA	(,%R15,4),%RBX

(83) 0x40d6df MOV	%R15D,-0x3c(%RBP)

(83) 0x40d6e3 MOV	%RBX,-0x38(%RBP)

(83) 0x40d6e7 SAL	$0x6,%R12D

(83) 0x40d6eb MOV	%R12D,-0x40(%RBP)

(83) 0x40d6ef TEST	%ECX,%ECX

(83) 0x40d6f1 JLE	40d852

(83) 0x40d6f7 MOV	-0x48(%RBP),%R13

(83) 0x40d6fb XOR	%EBX,%EBX

  (85) 0x40d6fd MOV	0x18(%R13),%R13

  (85) 0x40d701 MOV	(%R14),%ESI

  (85) 0x40d704 MOV	0x4(%R14),%ECX

  (85) 0x40d708 MOV	0x8(%R14),%EAX

  (85) 0x40d70c VMOVSD	0x30(%R14),%XMM7

  (85) 0x40d712 VMOVSD	0x38(%R14),%XMM6

  (85) 0x40d718 VMOVSD	0x40(%R14),%XMM5

  (84) 0x40d71e MOVSXD	%R12D,%RDI

  (84) 0x40d721 MOV	%ESI,%EDX

  (84) 0x40d723 LEA	(%RDI,%RDI,2),%R8

  (84) 0x40d727 LEA	(%R13,%R8,8),%R9

  (84) 0x40d72c VMOVSD	(%R9),%XMM2

  (84) 0x40d731 VMOVSD	0x8(%R9),%XMM1

  (84) 0x40d737 VMOVSD	0x10(%R9),%XMM0

  (84) 0x40d73d VCOMISD	%XMM2,%XMM7

  (84) 0x40d741 JBE	40d767

  (84) 0x40d743 XOR	%R11D,%R11D

  (84) 0x40d746 VSUBSD	0x18(%R14),%XMM2,%XMM3

  (84) 0x40d74c VMULSD	0x60(%R14),%XMM3,%XMM4

  (84) 0x40d752 VRNDSCALESD	$0x9,%XMM4,%XMM4,%XMM8

  (84) 0x40d759 VCVTTSD2SI	%XMM8,%EDX

  (84) 0x40d75e CMP	%ESI,%EDX

  (84) 0x40d760 SETE	%R11B

  (84) 0x40d764 SUB	%R11D,%EDX

  (84) 0x40d767 MOV	%ECX,%R8D

  (84) 0x40d76a VCOMISD	%XMM1,%XMM6

  (84) 0x40d76e JBE	40d794

  (84) 0x40d770 XOR	%EDI,%EDI

  (84) 0x40d772 VSUBSD	0x20(%R14),%XMM1,%XMM9

  (84) 0x40d778 VMULSD	0x68(%R14),%XMM9,%XMM10

  (84) 0x40d77e VRNDSCALESD	$0x9,%XMM10,%XMM10,%XMM11

  (84) 0x40d785 VCVTTSD2SI	%XMM11,%R8D

  (84) 0x40d78a CMP	%ECX,%R8D

  (84) 0x40d78d SETE	%DIL

  (84) 0x40d791 SUB	%EDI,%R8D

  (84) 0x40d794 VCOMISD	%XMM0,%XMM5

  (84) 0x40d798 JBE	40d890

  (84) 0x40d79e XOR	%R9D,%R9D

  (84) 0x40d7a1 VSUBSD	0x28(%R14),%XMM0,%XMM12

  (84) 0x40d7a7 VMULSD	0x70(%R14),%XMM12,%XMM13

  (84) 0x40d7ad VRNDSCALESD	$0x9,%XMM13,%XMM13,%XMM14

  (84) 0x40d7b4 VCVTTSD2SI	%XMM14,%EDI

  (84) 0x40d7b9 CMP	%EAX,%EDI

  (84) 0x40d7bb SETE	%R9B

  (84) 0x40d7bf SUB	%R9D,%EDI

  (84) 0x40d7c2 CMP	$-0x1,%EDI

  (84) 0x40d7c5 JE	40d8d0

  (84) 0x40d7cb CMP	%ECX,%R8D

  (84) 0x40d7ce JE	40d910

  (84) 0x40d7d4 CMP	$-0x1,%R8D

  (84) 0x40d7d8 JE	40d940

  (84) 0x40d7de CMP	%ESI,%EDX

  (84) 0x40d7e0 JE	40d970

  (84) 0x40d7e6 CMP	$-0x1,%EDX

  (84) 0x40d7e9 JE	40d990

  (84) 0x40d7ef IMUL	%ESI,%R8D

  (84) 0x40d7f3 ADD	%EDX,%R8D

  (84) 0x40d7f6 MOV	%ECX,%EDX

  (84) 0x40d7f8 IMUL	%ESI,%EDX

  (84) 0x40d7fb IMUL	%EDI,%EDX

  (84) 0x40d7fe ADD	%EDX,%R8D

  (84) 0x40d801 NOPW	%CS:(%RAX,%RAX,1)

  (84) 0x40d80c NOPL	(%RAX)

  (84) 0x40d810 TEST	%R8D,%R8D

  (84) 0x40d813 JS	40d99f

  (84) 0x40d819 CMP	0x14(%R14),%R8D

  (84) 0x40d81d JGE	40d9b8

  (84) 0x40d823 CMP	%R15D,%R8D

  (84) 0x40d826 JE	40d870

  (85) 0x40d828 MOV	-0x48(%RBP),%R13

  (85) 0x40d82c MOV	-0x3c(%RBP),%ECX

  (85) 0x40d82f MOV	%EBX,%EDX

  (85) 0x40d831 MOV	%R14,%RDI

  (85) 0x40d834 MOV	%R13,%RSI

  (85) 0x40d837 CALL	40d4a0 <moveAtom>

  (85) 0x40d83c MOV	0x78(%R14),%R10

  (85) 0x40d840 MOV	-0x38(%RBP),%RSI

  (85) 0x40d844 CMP	(%R10,%RSI,1),%EBX

  (85) 0x40d848 JL	40d6fd

(83) 0x40d84e MOV	0xc(%R14),%EAX

(83) 0x40d852 INC	%R15

(83) 0x40d855 CMP	%R15D,%EAX

(83) 0x40d858 JG	40d6d0

0x40d85e ADD	$0x28,%RSP

0x40d862 POP	%RBX

0x40d863 POP	%R12

0x40d865 POP	%R13

0x40d867 POP	%R14

0x40d869 POP	%R15

0x40d86b POP	%RBP

0x40d86c RET

0x40d86d NOPL	(%RAX)

  (84) 0x40d870 MOV	-0x38(%RBP),%R12

  (84) 0x40d874 INC	%EBX

  (84) 0x40d876 CMP	%EBX,(%R10,%R12,1)

  (84) 0x40d87a JLE	40d84e

  (84) 0x40d87c MOV	-0x40(%RBP),%EDX

  (84) 0x40d87f LEA	(%RDX,%RBX,1),%R12D

  (84) 0x40d883 JMP	40d71e

0x40d888 NOPL	(%RAX,%RAX,1)

  (84) 0x40d890 MOV	0xc(%R14),%EDI

  (84) 0x40d894 MOV	%EAX,%R11D

  (84) 0x40d897 LEA	0x2(%RSI),%R9D

  (84) 0x40d89b INC	%R8D

  (84) 0x40d89e IMUL	%ECX,%R11D

  (84) 0x40d8a2 IMUL	%R9D,%R8D

  (84) 0x40d8a6 LEA	(%RDI,%R11,2),%EDI

  (84) 0x40d8aa MOV	%R9D,%R11D

  (84) 0x40d8ad IMUL	%EAX,%R11D

  (84) 0x40d8b1 LEA	(%RDI,%R11,2),%R11D

  (84) 0x40d8b5 LEA	0x2(%RCX),%EDI

  (84) 0x40d8b8 IMUL	%R9D,%EDI

  (84) 0x40d8bc ADD	%R11D,%EDI

  (84) 0x40d8bf ADD	%EDI,%R8D

  (84) 0x40d8c2 LEA	0x1(%R8,%RDX,1),%R8D

  (84) 0x40d8c7 JMP	40d810

0x40d8cc NOPL	(%RAX)

  (84) 0x40d8d0 MOV	0xc(%R14),%EDI

  (84) 0x40d8d4 MOV	%EAX,%R11D

  (84) 0x40d8d7 LEA	0x2(%RSI),%R9D

  (84) 0x40d8db INC	%R8D

  (84) 0x40d8de IMUL	%ECX,%R11D

  (84) 0x40d8e2 IMUL	%R9D,%R8D

  (84) 0x40d8e6 LEA	(%RDI,%R11,2),%EDI

  (84) 0x40d8ea MOV	%R9D,%R11D

  (84) 0x40d8ed IMUL	%EAX,%R11D

  (84) 0x40d8f1 LEA	(%RDI,%R11,2),%EDI

  (84) 0x40d8f5 ADD	%EDI,%R8D

  (84) 0x40d8f8 LEA	0x1(%R8,%RDX,1),%R8D

  (84) 0x40d8fd JMP	40d810

0x40d902 NOPW	%CS:(%RAX,%RAX,1)

0x40d90d NOPL	(%RAX)

  (84) 0x40d910 MOV	0xc(%R14),%R8D

  (84) 0x40d914 MOV	%EAX,%R11D

  (84) 0x40d917 LEA	0x2(%RSI),%R9D

  (84) 0x40d91b IMUL	%ECX,%R11D

  (84) 0x40d91f LEA	(%R8,%R11,2),%R8D

  (84) 0x40d923 MOV	%R9D,%R11D

  (84) 0x40d926 IMUL	%EAX,%R11D

  (84) 0x40d92a IMUL	%EDI,%R9D

  (84) 0x40d92e ADD	%R11D,%R8D

  (84) 0x40d931 LEA	(%R8,%R9,1),%EDI

  (84) 0x40d935 LEA	0x1(%RDI,%RDX,1),%R8D

  (84) 0x40d93a JMP	40d810

0x40d93f NOP

  (84) 0x40d940 MOV	0xc(%R14),%R8D

  (84) 0x40d944 MOV	%EAX,%R9D

  (84) 0x40d947 IMUL	%ECX,%R9D

  (84) 0x40d94b LEA	(%R8,%R9,2),%R11D

  (84) 0x40d94f LEA	0x2(%RSI),%R9D

  (84) 0x40d953 IMUL	%R9D,%EDI

  (84) 0x40d957 ADD	%R11D,%EDI

  (84) 0x40d95a LEA	0x1(%RDI,%RDX,1),%R8D

  (84) 0x40d95f JMP	40d810

0x40d964 NOPW	%CS:(%RAX,%RAX,1)

0x40d96f NOP

  (84) 0x40d970 MOV	%EAX,%R11D

  (84) 0x40d973 IMUL	%ECX,%EDI

  (84) 0x40d976 IMUL	%ECX,%R11D

  (84) 0x40d97a ADD	0xc(%R14),%R11D

  (84) 0x40d97e ADD	%R11D,%EDI

  (84) 0x40d981 ADD	%EDI,%R8D

  (84) 0x40d984 JMP	40d810

0x40d989 NOPL	(%RAX)

  (84) 0x40d990 IMUL	%ECX,%EDI

  (84) 0x40d993 ADD	0xc(%R14),%EDI

  (84) 0x40d997 ADD	%EDI,%R8D

  (84) 0x40d99a JMP	40d810

0x40d99f MOV	$0x413ff0,%ECX

0x40d9a4 MOV	$0xf6,%EDX

0x40d9a9 MOV	$0x413ed8,%ESI

0x40d9ae MOV	$0x413fa7,%EDI

0x40d9b3 CALL	4030c0 <__assert_fail@plt>

0x40d9b8 MOV	$0x413ff0,%ECX

0x40d9bd MOV	$0xf7,%EDX

0x40d9c2 MOV	$0x413ed8,%ESI

0x40d9c7 MOV	$0x413fb1,%EDI

0x40d9cc CALL	4030c0 <__assert_fail@plt>

0x40d9d1 NOPW	%CS:(%RAX,%RAX,1)

0x40d9dc NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►85.00+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►14.08+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,288-304,352-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 4.88 to 0.32 cycles (15.11x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	51
nb uops	39
loop length	209
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Dispatch	3.00
Overall L1	4.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.88 cycles. At this rate:

2% of peak load performance is reached (5.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.88 to 3.00 cycles (1.63x speedup).

ASM code

In the binary file, the address of the function is: 40d670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD 0xc(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JGE 40d6b4 <updateLinkCells+0x44>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 40d85e <updateLinkCells+0x1ee>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x413ff0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x413ed8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x413fa7,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV $0x413ff0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x413ed8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x413fb1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,288-304,352-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	51
nb uops	39
loop length	209
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Dispatch	3.00
Overall L1	4.88

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.88 cycles. At this rate:

2% of peak load performance is reached (5.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40d670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD 0xc(%RDI),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JGE 40d6b4 <updateLinkCells+0x44>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 40d85e <updateLinkCells+0x1ee>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%R14),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV $0x413ff0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x413ed8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x413fa7,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV $0x413ff0,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x413ed8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x413fb1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CALL 4030c0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.59	0.15
▼Loop 83 - linkCells.c:211-373 - exec–	0.01	0.05
○Loop 84 - linkCells.c:211-373 - exec	0.57	3.93
○Loop 85 - linkCells.c:294-299 - exec	0.01	0.04
○Loop 86 - linkCells.c:384-385 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code