OV - exec - Function computeVcm._omp

	Function: computeVcm._omp_fn.0	Module: exec	Source: initAtoms.c:218-228	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 218 - 228

--------------------------------------------------------------------------------

218:    #pragma omp parallel for reduction(+:v0) reduction(+:v1) reduction(+:v2) reduction(+:v3)

219:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

220:    {

221:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

222:       {

223:          v0 += s->atoms->p[iOff][0];

224:          v1 += s->atoms->p[iOff][1];

225:          v2 += s->atoms->p[iOff][2];

226:

227:          int iSpecies = s->atoms->iSpecies[iOff];

228:          v3 += s->species[iSpecies].mass;

0x40aeb0 PUSH	%RBP

0x40aeb1 MOV	%RSP,%RBP

0x40aeb4 PUSH	%R14

0x40aeb6 PUSH	%R13

0x40aeb8 PUSH	%R12

0x40aeba PUSH	%RBX

0x40aebb MOV	%RDI,%RBX

0x40aebe AND	$-0x20,%RSP

0x40aec2 SUB	$0x20,%RSP

0x40aec6 MOV	(%RDI),%R12

0x40aec9 CALL	403060 <omp_get_num_threads@plt>

0x40aece MOV	%EAX,%R13D

0x40aed1 CALL	403160 <omp_get_thread_num@plt>

0x40aed6 MOV	%EAX,%ECX

0x40aed8 MOV	0x18(%R12),%R14

0x40aedd MOV	0xc(%R14),%EAX

0x40aee1 CLTD

0x40aee2 IDIV	%R13D

0x40aee5 CMP	%EDX,%ECX

0x40aee7 JL	40b118

0x40aeed IMUL	%EAX,%ECX

0x40aef0 VXORPD	%XMM0,%XMM0,%XMM0

0x40aef4 ADD	%ECX,%EDX

0x40aef6 LEA	(%RAX,%RDX,1),%ESI

0x40aef9 CMP	%ESI,%EDX

0x40aefb JGE	40b0e8

0x40af01 MOV	0x78(%R14),%RDI

0x40af05 MOVSXD	%EDX,%R10

0x40af08 MOV	%EAX,%R11D

0x40af0b ADD	%R10,%R11

0x40af0e LEA	(%R10,%R10,2),%R14

0x40af12 MOV	%R10,%R8

0x40af15 LEA	(%R11,%R11,2),%R13

0x40af19 SAL	$0x9,%R14

0x40af1d SAL	$0x6,%R8

0x40af21 SAL	$0x9,%R13

0x40af25 LEA	(%RDI,%R10,4),%R9

0x40af29 NOPL	(%RAX)

(64) 0x40af30 MOVSXD	(%R9),%RCX

(64) 0x40af33 TEST	%ECX,%ECX

(64) 0x40af35 JLE	40b0d0

(64) 0x40af3b MOV	0x20(%R12),%RAX

(64) 0x40af40 ADD	%R8,%RCX

(64) 0x40af43 MOVSXD	%R8D,%RDX

(64) 0x40af46 MOV	0x28(%R12),%R10

(64) 0x40af4b MOV	0x10(%RAX),%RSI

(64) 0x40af4f MOV	0x20(%RAX),%RAX

(64) 0x40af53 LEA	(%RSI,%RCX,4),%R11

(64) 0x40af57 LEA	(%RSI,%RDX,4),%RDI

(64) 0x40af5b ADD	%R14,%RAX

(64) 0x40af5e MOV	%R11,%RCX

(64) 0x40af61 SUB	%RDI,%RCX

(64) 0x40af64 SUB	$0x4,%RCX

(64) 0x40af68 SHR	$0x2,%RCX

(64) 0x40af6c INC	%RCX

(64) 0x40af6f AND	$0x3,%ECX

(64) 0x40af72 JE	40b01c

(64) 0x40af78 CMP	$0x1,%RCX

(64) 0x40af7c JE	40afe3

(64) 0x40af7e CMP	$0x2,%RCX

(64) 0x40af82 JE	40afb3

(64) 0x40af84 MOVSXD	(%RDI),%RSI

(64) 0x40af87 VMOVSD	0x8(%RAX),%XMM1

(64) 0x40af8c VMOVHPD	(%RAX),%XMM1,%XMM2

(64) 0x40af90 ADD	$0x4,%RDI

(64) 0x40af94 ADD	$0x18,%RAX

(64) 0x40af98 SAL	$0x4,%RSI

(64) 0x40af9c VMOVSD	0x8(%R10,%RSI,1),%XMM3

(64) 0x40afa3 VMOVHPD	-0x8(%RAX),%XMM3,%XMM4

(64) 0x40afa8 VINSERTF64X2	$0x1,%XMM2,%YMM4,%YMM5

(64) 0x40afaf VADDPD	%YMM5,%YMM0,%YMM0

(64) 0x40afb3 MOVSXD	(%RDI),%RDX

(64) 0x40afb6 VMOVSD	0x8(%RAX),%XMM6

(64) 0x40afbb VMOVHPD	(%RAX),%XMM6,%XMM7

(64) 0x40afbf ADD	$0x4,%RDI

(64) 0x40afc3 ADD	$0x18,%RAX

(64) 0x40afc7 SAL	$0x4,%RDX

(64) 0x40afcb VMOVSD	0x8(%R10,%RDX,1),%XMM8

(64) 0x40afd2 VMOVHPD	-0x8(%RAX),%XMM8,%XMM9

(64) 0x40afd7 VINSERTF64X2	$0x1,%XMM7,%YMM9,%YMM10

(64) 0x40afde VADDPD	%YMM10,%YMM0,%YMM0

(64) 0x40afe3 MOVSXD	(%RDI),%RCX

(64) 0x40afe6 VMOVSD	0x8(%RAX),%XMM11

(64) 0x40afeb VMOVHPD	(%RAX),%XMM11,%XMM12

(64) 0x40afef ADD	$0x4,%RDI

(64) 0x40aff3 ADD	$0x18,%RAX

(64) 0x40aff7 SAL	$0x4,%RCX

(64) 0x40affb VMOVSD	0x8(%R10,%RCX,1),%XMM13

(64) 0x40b002 VMOVHPD	-0x8(%RAX),%XMM13,%XMM14

(64) 0x40b007 VINSERTF64X2	$0x1,%XMM12,%YMM14,%YMM15

(64) 0x40b00e VADDPD	%YMM15,%YMM0,%YMM0

(64) 0x40b013 CMP	%RDI,%R11

(64) 0x40b016 JE	40b0d0

  (65) 0x40b01c MOVSXD	(%RDI),%RSI

  (65) 0x40b01f MOVSXD	0x4(%RDI),%RDX

  (65) 0x40b023 MOVSXD	0x8(%RDI),%RCX

  (65) 0x40b027 VMOVSD	0x8(%RAX),%XMM1

  (65) 0x40b02c VMOVHPD	(%RAX),%XMM1,%XMM2

  (65) 0x40b030 VMOVSD	0x20(%RAX),%XMM7

  (65) 0x40b035 VMOVHPD	0x18(%RAX),%XMM7,%XMM8

  (65) 0x40b03a VMOVSD	0x38(%RAX),%XMM13

  (65) 0x40b03f VMOVHPD	0x30(%RAX),%XMM13,%XMM14

  (65) 0x40b044 ADD	$0x10,%RDI

  (65) 0x40b048 ADD	$0x60,%RAX

  (65) 0x40b04c SAL	$0x4,%RSI

  (65) 0x40b050 VMOVSD	0x8(%R10,%RSI,1),%XMM3

  (65) 0x40b057 VMOVHPD	-0x50(%RAX),%XMM3,%XMM4

  (65) 0x40b05c MOVSXD	-0x4(%RDI),%RSI

  (65) 0x40b060 VINSERTF64X2	$0x1,%XMM2,%YMM4,%YMM5

  (65) 0x40b067 VMOVSD	-0x10(%RAX),%XMM2

  (65) 0x40b06c VMOVHPD	-0x18(%RAX),%XMM2,%XMM4

  (65) 0x40b071 SAL	$0x4,%RDX

  (65) 0x40b075 VADDPD	%YMM5,%YMM0,%YMM6

  (65) 0x40b079 VMOVSD	0x8(%R10,%RDX,1),%XMM9

  (65) 0x40b080 VMOVHPD	-0x38(%RAX),%XMM9,%XMM10

  (65) 0x40b085 SAL	$0x4,%RCX

  (65) 0x40b089 VINSERTF64X2	$0x1,%XMM8,%YMM10,%YMM11

  (65) 0x40b090 VADDPD	%YMM11,%YMM6,%YMM12

  (65) 0x40b095 VMOVSD	0x8(%R10,%RCX,1),%XMM15

  (65) 0x40b09c VMOVHPD	-0x20(%RAX),%XMM15,%XMM0

  (65) 0x40b0a1 VINSERTF64X2	$0x1,%XMM14,%YMM0,%YMM1

  (65) 0x40b0a8 SAL	$0x4,%RSI

  (65) 0x40b0ac VADDPD	%YMM1,%YMM12,%YMM3

  (65) 0x40b0b0 VMOVSD	0x8(%R10,%RSI,1),%XMM5

  (65) 0x40b0b7 VMOVHPD	-0x8(%RAX),%XMM5,%XMM6

  (65) 0x40b0bc VINSERTF64X2	$0x1,%XMM4,%YMM6,%YMM7

  (65) 0x40b0c3 VADDPD	%YMM7,%YMM3,%YMM0

  (65) 0x40b0c7 CMP	%RDI,%R11

  (65) 0x40b0ca JNE	40b01c

(64) 0x40b0d0 ADD	$0x600,%R14

(64) 0x40b0d7 ADD	$0x4,%R9

(64) 0x40b0db ADD	$0x40,%R8

(64) 0x40b0df CMP	%R14,%R13

(64) 0x40b0e2 JNE	40af30

0x40b0e8 VMOVAPD	%YMM0,(%RSP)

0x40b0ed VZEROUPPER

0x40b0f0 CALL	4031c0 <GOMP_atomic_start@plt>

0x40b0f5 VMOVAPD	(%RSP),%YMM8

0x40b0fa VADDPD	0x8(%RBX),%YMM8,%YMM9

0x40b0ff VMOVUPD	%YMM9,0x8(%RBX)

0x40b104 VZEROUPPER

0x40b107 LEA	-0x20(%RBP),%RSP

0x40b10b POP	%RBX

0x40b10c POP	%R12

0x40b10e POP	%R13

0x40b110 POP	%R14

0x40b112 POP	%RBP

0x40b113 JMP	403190

0x40b118 INC	%EAX

0x40b11a XOR	%EDX,%EDX

0x40b11c JMP	40aeed

0x40b121 NOPW	%CS:(%RAX,%RAX,1)

0x40b12c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.58+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.42+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	setVcm	initAtoms.c:234	exec
○	setTemperature	initAtoms.c:170	exec
○	main	CoMD.c:200	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	initAtoms.c:218-228
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218-228.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.13 to 1.50 cycles (4.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
27% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_atomic_start@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:221
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 92 bytes (11 double precision FP elements). The binary function is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	57
loop length	200
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	3
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	2.75	2.75	2.75	2.75	0.00	0.00	0.50	0.50	1.00	1.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	2.75	2.75	2.75	2.75	0.00	0.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	7.13
Dispatch	4.33
DIV/SQRT	6.00
Overall L1	7.13

Vectorization ratios

INT

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	41%
load	100%
store	100%
mul	0%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	27%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	45%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	20%
load	50%
store	50%
mul	6%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.13 cycles. At this rate:

5% of peak load performance is reached (12.91 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (8.98 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 40aeb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x18(%R12),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40b118 <computeVcm._omp_fn.0+0x268>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40b0e8 <computeVcm._omp_fn.0+0x238>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R10,2),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA (%R11,%R11,2),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x6,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x9,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RDI,%R10,4),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVAPD %YMM0,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4031c0 <GOMP_atomic_start@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
VMOVAPD (%RSP),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD 0x8(%RBX),%YMM8,%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD %YMM9,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403190 <GOMP_atomic_end@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40aeed <computeVcm._omp_fn.0+0x3d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	initAtoms.c:218-228
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:218-228.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.13 to 1.50 cycles (4.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
27% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

GOMP_atomic_start@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:221
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:219

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 4 FP arithmetical operations:

4: addition or subtraction

The binary function is loading 92 bytes (11 double precision FP elements). The binary function is storing 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	57
nb uops	57
loop length	200
used x86 registers	15
used mmx registers	0
used xmm registers	1
used ymm registers	3
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	2.75	2.75	2.75	2.75	0.00	0.00	0.50	0.50	1.00	1.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	2.75	2.75	2.75	2.75	0.00	0.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	7.13
Dispatch	4.33
DIV/SQRT	6.00
Overall L1	7.13

Vectorization ratios

INT

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	41%
load	100%
store	100%
mul	0%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	27%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	45%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	20%
load	50%
store	50%
mul	6%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.13 cycles. At this rate:

5% of peak load performance is reached (12.91 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (8.98 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 40aeb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CALL 403060 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 403160 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x18(%R12),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTD																				scal (6.3%)
IDIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JL 40b118 <computeVcm._omp_fn.0+0x268>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EAX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 40b0e8 <computeVcm._omp_fn.0+0x238>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%R14),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %EDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R10,%R10,2),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA (%R11,%R11,2),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x9,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x6,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SAL $0x9,%R13	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%RDI,%R10,4),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVAPD %YMM0,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4031c0 <GOMP_atomic_start@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
VMOVAPD (%RSP),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD 0x8(%RBX),%YMM8,%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVUPD %YMM9,0x8(%RBX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x20(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 403190 <GOMP_atomic_end@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40aeed <computeVcm._omp_fn.0+0x3d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼computeVcm._omp_fn.0–	0.01	0.00
▼Loop 64 - initAtoms.c:221-228 - exec–	0.00	0.00
○Loop 65 - initAtoms.c:221-228 - exec	0.01	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code