OV - exec - Function loadAtomsBuffer

	Function: loadAtomsBuffer	Module: exec	Source: haloExchange.c:362-394	Coverage (incl. loops): 0.06% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 362 - 394

--------------------------------------------------------------------------------

362: {

363:    AtomExchangeParms* parms = (AtomExchangeParms*) vparms;

364:    SimFlat* s = (SimFlat*) data;

365:    AtomMsg* buf = (AtomMsg*) charBuf;

366:

367:    real_t* pbcFactor = parms->pbcFactor[face];

368:    real3 shift;

369:    shift[0] = pbcFactor[0] * s->domain->globalExtent[0];

370:    shift[1] = pbcFactor[1] * s->domain->globalExtent[1];

371:    shift[2] = pbcFactor[2] * s->domain->globalExtent[2];

372:

373:    int nCells = parms->nCells[face];

374:    int* cellList = parms->cellList[face];

375:    int nBuf = 0;

376:    for (int iCell=0; iCell<nCells; ++iCell)

377:    {

378:       int iBox = cellList[iCell];

379:       int iOff = iBox*MAXATOMS;

380:       for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii)

381:       {

382:          buf[nBuf].gid  = s->atoms->gid[ii];

383:          buf[nBuf].type = s->atoms->iSpecies[ii];

384:          buf[nBuf].rx = s->atoms->r[ii][0] + shift[0];

385:          buf[nBuf].ry = s->atoms->r[ii][1] + shift[1];

386:          buf[nBuf].rz = s->atoms->r[ii][2] + shift[2];

387:          buf[nBuf].px = s->atoms->p[ii][0];

388:          buf[nBuf].py = s->atoms->p[ii][1];

389:          buf[nBuf].pz = s->atoms->p[ii][2];

390:          ++nBuf;

391:       }

392:    }

393:    return nBuf*sizeof(AtomMsg);

394: }

0x407d20 PUSH	%RBP

0x407d21 MOVSXD	%EDX,%RDX

0x407d24 MOV	%RSP,%RBP

0x407d27 PUSH	%R15

0x407d29 PUSH	%R14

0x407d2b PUSH	%R13

0x407d2d PUSH	%R12

0x407d2f PUSH	%RBX

0x407d30 MOV	%RCX,-0x38(%RBP)

0x407d34 MOV	0x10(%RSI),%RAX

0x407d38 MOV	0x48(%RDI,%RDX,8),%RCX

0x407d3d MOVSXD	(%RDI,%RDX,4),%R8

0x407d41 MOV	0x18(%RDI,%RDX,8),%R11

0x407d46 VMOVSD	(%RCX),%XMM2

0x407d4a VMOVSD	0x8(%RCX),%XMM3

0x407d4f VMOVSD	0x10(%RCX),%XMM4

0x407d54 VMULSD	0x48(%RAX),%XMM2,%XMM1

0x407d59 VMULSD	0x50(%RAX),%XMM3,%XMM5

0x407d5e VMULSD	0x58(%RAX),%XMM4,%XMM6

0x407d63 TEST	%R8D,%R8D

0x407d66 JLE	407e67

0x407d6c MOV	%RSI,%RBX

0x407d6f MOV	0x18(%RSI),%RSI

0x407d73 LEA	(%R11,%R8,4),%RDI

0x407d77 XOR	%R8D,%R8D

0x407d7a MOV	%RDI,-0x30(%RBP)

0x407d7e MOV	0x78(%RSI),%R12

0x407d82 NOPW	%CS:(%RAX,%RAX,1)

0x407d8d NOPL	(%RAX)

(35) 0x407d90 MOVSXD	(%R11),%RDX

(35) 0x407d93 LEA	(%R12,%RDX,4),%R15

(35) 0x407d97 MOV	%EDX,%R10D

(35) 0x407d9a MOV	(%R15),%R9D

(35) 0x407d9d SAL	$0x6,%R10D

(35) 0x407da1 TEST	%R9D,%R9D

(35) 0x407da4 JLE	407e4a

(35) 0x407daa MOV	0x20(%RBX),%RCX

(35) 0x407dae MOV	-0x38(%RBP),%R9

(35) 0x407db2 MOVSXD	%R8D,%RAX

(35) 0x407db5 LEA	(%RDX,%RDX,2),%RDX

(35) 0x407db9 IMUL	$0x38,%RAX,%RAX

(35) 0x407dbd SAL	$0x9,%RDX

(35) 0x407dc1 MOV	0x8(%RCX),%R14

(35) 0x407dc5 MOV	0x10(%RCX),%R13

(35) 0x407dc9 MOV	0x18(%RCX),%RDI

(35) 0x407dcd MOV	0x20(%RCX),%RSI

(35) 0x407dd1 ADD	%R9,%RAX

(35) 0x407dd4 MOVSXD	%R10D,%RCX

(35) 0x407dd7 NOPW	(%RAX,%RAX,1)

  (36) 0x407de0 MOV	(%R14,%RCX,4),%R9D

  (36) 0x407de4 VADDSD	(%RDI,%RDX,1),%XMM1,%XMM0

  (36) 0x407de9 INC	%R8D

  (36) 0x407dec ADD	$0x38,%RAX

  (36) 0x407df0 MOV	%R9D,-0x38(%RAX)

  (36) 0x407df4 MOV	(%R13,%RCX,4),%R9D

  (36) 0x407df9 INC	%RCX

  (36) 0x407dfc VMOVSD	%XMM0,-0x30(%RAX)

  (36) 0x407e01 VADDSD	0x8(%RDI,%RDX,1),%XMM5,%XMM7

  (36) 0x407e07 VMOVSD	%XMM7,-0x28(%RAX)

  (36) 0x407e0c VADDSD	0x10(%RDI,%RDX,1),%XMM6,%XMM8

  (36) 0x407e12 VMOVSD	%XMM8,-0x20(%RAX)

  (36) 0x407e17 VMOVSD	(%RSI,%RDX,1),%XMM9

  (36) 0x407e1c VMOVSD	%XMM9,-0x18(%RAX)

  (36) 0x407e21 VMOVSD	0x8(%RSI,%RDX,1),%XMM10

  (36) 0x407e27 VMOVSD	%XMM10,-0x10(%RAX)

  (36) 0x407e2c VMOVSD	0x10(%RSI,%RDX,1),%XMM11

  (36) 0x407e32 ADD	$0x18,%RDX

  (36) 0x407e36 VMOVSD	%XMM11,-0x8(%RAX)

  (36) 0x407e3b MOV	%R9D,-0x34(%RAX)

  (36) 0x407e3f MOV	(%R15),%R9D

  (36) 0x407e42 ADD	%R10D,%R9D

  (36) 0x407e45 CMP	%ECX,%R9D

  (36) 0x407e48 JG	407de0

(35) 0x407e4a ADD	$0x4,%R11

(35) 0x407e4e CMP	%R11,-0x30(%RBP)

(35) 0x407e52 JNE	407d90

0x407e58 IMUL	$0x38,%R8D,%EAX

0x407e5c POP	%RBX

0x407e5d POP	%R12

0x407e5f POP	%R13

0x407e61 POP	%R14

0x407e63 POP	%R15

0x407e65 POP	%RBP

0x407e66 RET

0x407e67 POP	%RBX

0x407e68 XOR	%EAX,%EAX

0x407e6a POP	%R12

0x407e6c POP	%R13

0x407e6e POP	%R14

0x407e70 POP	%R15

0x407e72 POP	%RBP

0x407e73 RET

0x407e74 NOPW	%CS:(%RAX,%RAX,1)

0x407e7f NOP

Coverage (%)	Name	Source Location	Module
►41.97+	haloExchange	haloExchange.c:291	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►41.65+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
►8.27+	haloExchange	haloExchange.c:291	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec
►7.02+	haloExchange	haloExchange.c:289	exec
○	timestep	timestep.c:150	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	CoMD.c:266	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	haloExchange.c:362-394
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:362-394.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.38 to 1.75 cycles (3.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your function, you can lower the cost of an iteration from 5.38 to 0.67 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: multiply

The binary function is loading 92 bytes (11 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	43
loop length	152
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	3.50	3.50	3.50	3.50	1.50	1.50	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.33	1.33	1.33	3.50	3.50	3.50	3.50	1.50	1.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.38
Dispatch	3.50
Overall L1	5.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.38 cycles. At this rate:

6% of peak load performance is reached (17.12 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.98 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.38 to 3.50 cycles (1.54x speedup).

ASM code

In the binary file, the address of the function is: 407d20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVSXD %EDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x48(%RDI,%RDX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSXD (%RDI,%RDX,4),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
MOV 0x18(%RDI,%RDX,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVSD (%RCX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RCX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RCX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD 0x48(%RAX),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	3	0.50	scal (12.5%)
VMULSD 0x50(%RAX),%XMM3,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	3	0.50	scal (12.5%)
VMULSD 0x58(%RAX),%XMM4,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	3	0.50	scal (12.5%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JLE 407e67 <loadAtomsBuffer+0x147>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x18(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%R11,%R8,4),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RSI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
IMUL $0x38,%R8D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	haloExchange.c:362-394
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:362-394.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.38 to 1.75 cycles (3.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your function, you can lower the cost of an iteration from 5.38 to 0.67 cycles (8.00x speedup).

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: multiply

The binary function is loading 92 bytes (11 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	47
nb uops	43
loop length	152
used x86 registers	14
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.38 cycles
front end	5.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.33	1.33	1.33	3.50	3.50	3.50	3.50	1.50	1.50	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.33	1.33	1.33	3.50	3.50	3.50	3.50	1.50	1.50	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.38
Dispatch	3.50
Overall L1	5.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.38 cycles. At this rate:

6% of peak load performance is reached (17.12 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.98 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 407d20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVSXD %EDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x48(%RDI,%RDX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSXD (%RDI,%RDX,4),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
MOV 0x18(%RDI,%RDX,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVSD (%RCX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RCX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x10(%RCX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMULSD 0x48(%RAX),%XMM2,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	3	0.50	scal (12.5%)
VMULSD 0x50(%RAX),%XMM3,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	3	0.50	scal (12.5%)
VMULSD 0x58(%RAX),%XMM4,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	3	0.50	scal (12.5%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JLE 407e67 <loadAtomsBuffer+0x147>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x18(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%R11,%R8,4),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RSI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
IMUL $0x38,%R8D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼loadAtomsBuffer–	0.06	0.02
▼Loop 35 - haloExchange.c:376-390 - exec–	0.01	0.06
○Loop 36 - haloExchange.c:380-390 - exec	0.05	0.34

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code