OV - exec - Loop 94

0x40bed0 LEA	0x1(%RBX),%RAX

0x40bed4 CMP	%R9,%RBX

0x40bed7 MOV	%RAX,%RBX

0x40beda JE	40be70

0x40bedc LEA	(%RBX,%RDI,1),%RSI

0x40bee0 LEA	(%RSI,%RSI,2),%RCX

0x40bee4 LEA	(%R12,%RCX,8),%RAX

0x40bee8 MOV	%R15,%R13

0x40beeb MOV	%RDX,%R11

0x40beee JMP	40bef9

  (95) 0x40bef0 ADD	$0x18,%R13

  (95) 0x40bef4 DEC	%R11

  (95) 0x40bef7 JE	40bed0

  (95) 0x40bef9 VMOVUPD	(%RAX),%XMM11

  (95) 0x40befd VSUBPD	-0x10(%R13),%XMM11,%XMM11

  (95) 0x40bf03 VMULPD	%XMM11,%XMM11,%XMM12

  (95) 0x40bf08 VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

  (95) 0x40bf0e VADDSD	%XMM12,%XMM13,%XMM13

  (95) 0x40bf13 VMOVSD	0x10(%RAX),%XMM12

  (95) 0x40bf18 VSUBSD	(%R13),%XMM12,%XMM12

  (95) 0x40bf1e VFMADD231SD	%XMM12,%XMM12,%XMM13

  (95) 0x40bf23 VUCOMISD	%XMM2,%XMM13

  (95) 0x40bf27 JA	40bef0

  (95) 0x40bf29 VUCOMISD	%XMM4,%XMM13

  (95) 0x40bf2d JBE	40bef0

  (95) 0x40bf2f VDIVSD	%XMM13,%XMM6,%XMM13

  (95) 0x40bf34 VMULSD	%XMM13,%XMM13,%XMM14

  (95) 0x40bf39 VMULSD	%XMM1,%XMM13,%XMM15

  (95) 0x40bf3d VMULSD	%XMM15,%XMM14,%XMM14

  (95) 0x40bf42 VADDSD	%XMM7,%XMM14,%XMM15

  (95) 0x40bf46 VFNMADD213SD	%XMM0,%XMM14,%XMM15

  (95) 0x40bf4b VMULSD	%XMM8,%XMM15,%XMM15

  (95) 0x40bf50 MOV	0x30(%R14),%R8

  (95) 0x40bf54 VADDSD	(%R8,%RSI,8),%XMM15,%XMM16

  (95) 0x40bf5b VMOVSD	%XMM16,(%R8,%RSI,8)

  (95) 0x40bf62 VMOVAPD	%XMM9,%XMM16

  (95) 0x40bf68 VFMADD213SD	%XMM10,%XMM14,%XMM16

  (95) 0x40bf6e VMULSD	%XMM3,%XMM13,%XMM13

  (95) 0x40bf72 VMULSD	%XMM14,%XMM16,%XMM14

  (95) 0x40bf78 VMULSD	%XMM13,%XMM14,%XMM13

  (95) 0x40bf7d MOV	0x28(%R14),%R8

  (95) 0x40bf81 VMOVDDUP	%XMM13,%XMM14

  (95) 0x40bf86 VFMADD213PD	(%R8,%RCX,8),%XMM14,%XMM11

  (95) 0x40bf8c VMOVUPD	%XMM11,(%R8,%RCX,8)

  (95) 0x40bf92 VFMADD213SD	0x10(%R8,%RCX,8),%XMM13,%XMM12

  (95) 0x40bf99 VMOVSD	%XMM12,0x10(%R8,%RCX,8)

  (95) 0x40bfa0 VADDSD	%XMM5,%XMM15,%XMM5

  (95) 0x40bfa4 JMP	40bef0

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 187 - 216

--------------------------------------------------------------------------------

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►96.43+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.44+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	ljForce.extracted
Source	ljForce.c:187-187,ljForce.c:197-197
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.25
CQA cycles if no scalar integer	1.25
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.16
Front-end cycles	1.25
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	ljForce.extracted
Source	ljForce.c:187-187,ljForce.c:197-197
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.25
CQA cycles if no scalar integer	1.25
CQA cycles if FP arith vectorized	1.25
CQA cycles if fully vectorized	0.16
Front-end cycles	1.25
P0 cycles	1.17
P1 cycles	1.17
P2 cycles	1.17
P3 cycles	1.17
P4 cycles	1.17
P5 cycles	1.17
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	0.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.extracted
Source file and lines	ljForce.c:187-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187,197.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.25 to 0.16 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
nb uops	10
loop length	32
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.25 cycles
front end	1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.25
Dispatch	1.17
Data deps.	0.00
Overall L1	1.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.25 to 1.17 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 40bedc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
LEA 0x1(%RBX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
CMP %R9,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0.17	N/A
JE 40be70 <ljForce.extracted+0x1c0>	1	0	0	0	0.33	0.33	0.33	1	0.50-1	N/A
LEA (%RBX,%RDI,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
LEA (%RSI,%RSI,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
LEA (%R12,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
MOV %R15,%R13	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 40bef9 <ljForce.extracted+0x249>	1	0	0	0	0.33	0.33	0.33	0	1	N/A

Function	ljForce.extracted
Source file and lines	ljForce.c:187-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187,197.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.25 to 0.16 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
nb uops	10
loop length	32
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.25 cycles
front end	1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.17	1.17	1.17	1.17	1.17	1.17	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.17	1.17	1.17	1.17	1.17	1.17	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.25
Dispatch	1.17
Data deps.	0.00
Overall L1	1.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.25 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.25 to 1.17 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 40bedc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
LEA 0x1(%RBX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
CMP %R9,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0.17	N/A
JE 40be70 <ljForce.extracted+0x1c0>	1	0	0	0	0.33	0.33	0.33	1	0.50-1	N/A
LEA (%RBX,%RDI,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
LEA (%RSI,%RSI,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
LEA (%R12,%RCX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.25	N/A
MOV %R15,%R13	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 40bef9 <ljForce.extracted+0x249>	1	0	0	0	0.33	0.33	0.33	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code