OV - exec - Loop 92

	Loop Id: 92	Module: exec	Source: ljForce.c:172-216 [...]	Coverage: 0.01%

0x40be20 MOV	-0x78(%RBP),%RCX

0x40be24 INC	%RCX

0x40be27 ADD	$0x40,%EDI

0x40be2a CMP	-0x50(%RBP),%RCX

0x40be2e JE	40bd30

0x40be34 MOV	%EDI,%EDI

0x40be36 MOV	-0x60(%RBP),%RAX

0x40be3a MOV	(%RAX,%RCX,4),%EAX

0x40be3d MOV	-0x70(%RBP),%RDX

0x40be41 MOV	(%RDX,%RCX,8),%RDX

0x40be45 TEST	%EAX,%EAX

0x40be47 MOV	%RCX,-0x78(%RBP)

0x40be4b JLE	40bfb0

0x40be51 SAL	$0x6,%ECX

0x40be54 ADD	%ECX,%EAX

0x40be56 LEA	0x1(%RDI),%ECX

0x40be59 CMP	%ECX,%EAX

0x40be5b CMOVLE	%ECX,%EAX

0x40be5e MOV	%EDI,%R9D

0x40be61 NOT	%R9D

0x40be64 ADD	%EAX,%R9D

0x40be67 XOR	%R10D,%R10D

0x40be6a MOV	%RDX,-0x80(%RBP)

0x40be6e JMP	40be7d

  (93) 0x40be70 INC	%R10

  (93) 0x40be73 CMP	$0x1b,%R10

  (93) 0x40be77 MOV	-0x80(%RBP),%RDX

  (93) 0x40be7b JE	40be20

  (93) 0x40be7d MOV	(%RDX,%R10,4),%EAX

  (93) 0x40be81 TEST	%EAX,%EAX

  (93) 0x40be83 JS	40c06d

  (93) 0x40be89 MOV	-0x60(%RBP),%RCX

  (93) 0x40be8d MOVSXD	(%RCX,%RAX,4),%RDX

  (93) 0x40be91 TEST	%RDX,%RDX

  (93) 0x40be94 JLE	40be70

  (93) 0x40be96 SAL	$0x6,%EAX

  (93) 0x40be99 MOV	-0x58(%RBP),%RCX

  (93) 0x40be9d MOV	0x20(%RCX),%R14

  (93) 0x40bea1 MOV	0x18(%R14),%R12

  (93) 0x40bea5 CLTQ

  (93) 0x40bea7 ADD	%RAX,%RDX

  (93) 0x40beaa LEA	0x1(%RAX),%RCX

  (93) 0x40beae CMP	%RCX,%RDX

  (93) 0x40beb1 CMOVLE	%RCX,%RDX

  (93) 0x40beb5 SUB	%RAX,%RDX

  (93) 0x40beb8 LEA	(%RAX,%RAX,2),%RAX

  (93) 0x40bebc LEA	(%R12,%RAX,8),%R15

  (93) 0x40bec0 ADD	$0x10,%R15

  (93) 0x40bec4 XOR	%EBX,%EBX

  (93) 0x40bec6 JMP	40bedc

    (94) 0x40bed0 LEA	0x1(%RBX),%RAX

    (94) 0x40bed4 CMP	%R9,%RBX

    (94) 0x40bed7 MOV	%RAX,%RBX

    (94) 0x40beda JE	40be70

    (94) 0x40bedc LEA	(%RBX,%RDI,1),%RSI

    (94) 0x40bee0 LEA	(%RSI,%RSI,2),%RCX

    (94) 0x40bee4 LEA	(%R12,%RCX,8),%RAX

    (94) 0x40bee8 MOV	%R15,%R13

    (94) 0x40beeb MOV	%RDX,%R11

    (94) 0x40beee JMP	40bef9

      (95) 0x40bef0 ADD	$0x18,%R13

      (95) 0x40bef4 DEC	%R11

      (95) 0x40bef7 JE	40bed0

      (95) 0x40bef9 VMOVUPD	(%RAX),%XMM11

      (95) 0x40befd VSUBPD	-0x10(%R13),%XMM11,%XMM11

      (95) 0x40bf03 VMULPD	%XMM11,%XMM11,%XMM12

      (95) 0x40bf08 VSHUFPD	$0x1,%XMM12,%XMM12,%XMM13

      (95) 0x40bf0e VADDSD	%XMM12,%XMM13,%XMM13

      (95) 0x40bf13 VMOVSD	0x10(%RAX),%XMM12

      (95) 0x40bf18 VSUBSD	(%R13),%XMM12,%XMM12

      (95) 0x40bf1e VFMADD231SD	%XMM12,%XMM12,%XMM13

      (95) 0x40bf23 VUCOMISD	%XMM2,%XMM13

      (95) 0x40bf27 JA	40bef0

      (95) 0x40bf29 VUCOMISD	%XMM4,%XMM13

      (95) 0x40bf2d JBE	40bef0

      (95) 0x40bf2f VDIVSD	%XMM13,%XMM6,%XMM13

      (95) 0x40bf34 VMULSD	%XMM13,%XMM13,%XMM14

      (95) 0x40bf39 VMULSD	%XMM1,%XMM13,%XMM15

      (95) 0x40bf3d VMULSD	%XMM15,%XMM14,%XMM14

      (95) 0x40bf42 VADDSD	%XMM7,%XMM14,%XMM15

      (95) 0x40bf46 VFNMADD213SD	%XMM0,%XMM14,%XMM15

      (95) 0x40bf4b VMULSD	%XMM8,%XMM15,%XMM15

      (95) 0x40bf50 MOV	0x30(%R14),%R8

      (95) 0x40bf54 VADDSD	(%R8,%RSI,8),%XMM15,%XMM16

      (95) 0x40bf5b VMOVSD	%XMM16,(%R8,%RSI,8)

      (95) 0x40bf62 VMOVAPD	%XMM9,%XMM16

      (95) 0x40bf68 VFMADD213SD	%XMM10,%XMM14,%XMM16

      (95) 0x40bf6e VMULSD	%XMM3,%XMM13,%XMM13

      (95) 0x40bf72 VMULSD	%XMM14,%XMM16,%XMM14

      (95) 0x40bf78 VMULSD	%XMM13,%XMM14,%XMM13

      (95) 0x40bf7d MOV	0x28(%R14),%R8

      (95) 0x40bf81 VMOVDDUP	%XMM13,%XMM14

      (95) 0x40bf86 VFMADD213PD	(%R8,%RCX,8),%XMM14,%XMM11

      (95) 0x40bf8c VMOVUPD	%XMM11,(%R8,%RCX,8)

      (95) 0x40bf92 VFMADD213SD	0x10(%R8,%RCX,8),%XMM13,%XMM12

      (95) 0x40bf99 VMOVSD	%XMM12,0x10(%R8,%RCX,8)

      (95) 0x40bfa0 VADDSD	%XMM5,%XMM15,%XMM5

      (95) 0x40bfa4 JMP	40bef0

0x40bfb0 CMPL	$0,(%RDX)

0x40bfb3 JS	40c06d

0x40bfb9 CMPL	$0,0x4(%RDX)

0x40bfbd JS	40c06d

0x40bfc3 CMPL	$0,0x8(%RDX)

0x40bfc7 JS	40c06d

0x40bfcd CMPL	$0,0xc(%RDX)

0x40bfd1 JS	40c06d

0x40bfd7 CMPL	$0,0x10(%RDX)

0x40bfdb JS	40c06d

0x40bfe1 CMPL	$0,0x14(%RDX)

0x40bfe5 JS	40c06d

0x40bfeb CMPL	$0,0x18(%RDX)

0x40bfef JS	40c06d

0x40bff1 CMPL	$0,0x1c(%RDX)

0x40bff5 JS	40c06d

0x40bff7 CMPL	$0,0x20(%RDX)

0x40bffb JS	40c06d

0x40bffd CMPL	$0,0x24(%RDX)

0x40c001 JS	40c06d

0x40c003 CMPL	$0,0x28(%RDX)

0x40c007 JS	40c06d

0x40c009 CMPL	$0,0x2c(%RDX)

0x40c00d JS	40c06d

0x40c00f CMPL	$0,0x30(%RDX)

0x40c013 JS	40c06d

0x40c015 CMPL	$0,0x34(%RDX)

0x40c019 JS	40c06d

0x40c01b CMPL	$0,0x38(%RDX)

0x40c01f JS	40c06d

0x40c021 CMPL	$0,0x3c(%RDX)

0x40c025 JS	40c06d

0x40c027 CMPL	$0,0x40(%RDX)

0x40c02b JS	40c06d

0x40c02d CMPL	$0,0x44(%RDX)

0x40c031 JS	40c06d

0x40c033 CMPL	$0,0x48(%RDX)

0x40c037 JS	40c06d

0x40c039 CMPL	$0,0x4c(%RDX)

0x40c03d JS	40c06d

0x40c03f CMPL	$0,0x50(%RDX)

0x40c043 JS	40c06d

0x40c045 CMPL	$0,0x54(%RDX)

0x40c049 JS	40c06d

0x40c04b CMPL	$0,0x58(%RDX)

0x40c04f JS	40c06d

0x40c051 CMPL	$0,0x5c(%RDX)

0x40c055 JS	40c06d

0x40c057 CMPL	$0,0x60(%RDX)

0x40c05b JS	40c06d

0x40c05d CMPL	$0,0x64(%RDX)

0x40c061 JS	40c06d

0x40c063 CMPL	$0,0x68(%RDX)

0x40c067 JNS	40be20

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216

--------------------------------------------------------------------------------

172:    #pragma omp parallel for reduction(+:ePot)

173:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

174:    {

175:       int nIBox = s->boxes->nAtoms[iBox];

176:

177:       // loop over neighbors of iBox

178:       for (int jTmp=0; jTmp<nNbrBoxes; jTmp++)

179:       {

180:          int jBox = s->boxes->nbrBoxes[iBox][jTmp];

181:

182:          assert(jBox>=0);

183:

184:          int nJBox = s->boxes->nAtoms[jBox];

185:

186:          // loop over atoms in iBox

187:          for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++)

188:          {

189:

190:             // loop over atoms in jBox

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Coverage (%)	Name	Source Location	Module
►96.65+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.35+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	ljForce	ljForce.c:172	exec
○	timestep	timestep.c:51	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.47
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks
Function	ljForce.extracted
Source	ljForce.c:172-175,ljForce.c:180-182,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.25
CQA cycles if no scalar integer	6.25
CQA cycles if FP arith vectorized	6.25
CQA cycles if fully vectorized	0.40
Front-end cycles	5.44
P0 cycles	5.92
P1 cycles	5.92
P2 cycles	5.92
P3 cycles	5.92
P4 cycles	5.92
P5 cycles	5.92
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	43.50
Nb loads	18.50
Nb stores	1.50
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.80
Bytes prefetched	0.00
Bytes loaded	90.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.70
Vector-efficiency ratio load	6.48
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.36

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	micro-operation queue,
Function	ljForce.extracted
Source	ljForce.c:172-175,ljForce.c:180-182,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.17
Front-end cycles	2.50
P0 cycles	1.83
P1 cycles	1.83
P2 cycles	1.83
P3 cycles	1.83
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	20.00
Nb loads	4.00
Nb stores	2.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.60
Bytes prefetched	0.00
Bytes loaded	28.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	15.74
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P0, P1, P2, P3, P4, P5,
Function	ljForce.extracted
Source	ljForce.c:172-175,ljForce.c:180-182,ljForce.c:187-187
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	10.00
CQA cycles if fully vectorized	0.64
Front-end cycles	8.38
P0 cycles	10.00
P1 cycles	10.00
P2 cycles	10.00
P3 cycles	10.00
P4 cycles	10.00
P5 cycles	10.00
P6 cycles	8.50
P7 cycles	8.50
P8 cycles	8.50
P9 cycles	8.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	67.00
Nb uops	67.00
Nb loads	33.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.65
Vector-efficiency ratio load	6.48
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.47

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.extracted
Source file and lines	ljForce.c:172-216
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-191,197-216.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:172-175,180-182,187.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.25 to 0.40 cycles (15.47x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 0 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 90 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	43
nb uops	43.50
loop length	149
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	5.44 cycles
front end	5.44 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.92	5.92	5.92	5.92	5.92	5.92	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.92	5.92	5.92	5.92	5.92	5.92	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.44
Dispatch	5.92
Data deps.	1.00
Overall L1	6.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.25 cycles. At this rate:

5% of peak load performance is reached (13.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	ljForce.extracted
Source file and lines	ljForce.c:172-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.17 cycles (14.48x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVLE: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:187

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 28 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	19
nb uops	20
loop length	60
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.50 cycles
front end	2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.83	1.83	1.83	1.83	1.83	1.83	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.83	1.83	1.83	1.83	1.83	1.83	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.50
Dispatch	1.83
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

4% of peak load performance is reached (11.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 1.83 cycles (1.36x speedup).

ASM code

In the binary file, the address of the loop is: 40be34

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RCX,4),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RCX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JLE 40bfb0 <ljForce.extracted+0x300>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
SAL $0x6,%ECX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
ADD %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDI),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVLE %ECX,%EAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %EDI,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOT %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EAX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 40be7d <ljForce.extracted+0x1cd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	ljForce.extracted
Source file and lines	ljForce.c:172-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 6% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.00 to 0.64 cycles (15.74x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	67
nb uops	67
loop length	238
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.38 cycles
front end	8.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	10.00	10.00	10.00	10.00	10.00	10.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.00	10.00	10.00	10.00	10.00	10.00	8.50	8.50	8.50	8.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.38
Dispatch	10.00
Data deps.	1.00
Overall L1	10.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

5% of peak load performance is reached (15.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40be34

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $0x40,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP -0x50(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 40bd30 <ljForce.extracted+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RCX,4),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RCX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JLE 40bfb0 <ljForce.extracted+0x300>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x4(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x8(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0xc(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x10(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x14(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x18(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x1c(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x20(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x24(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x28(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x2c(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x30(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x34(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x38(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x3c(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x40(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x44(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x48(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x4c(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x50(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x54(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x58(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x5c(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x60(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x64(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JS 40c06d <ljForce.extracted+0x3bd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMPL $0,0x68(%RDX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
JNS 40be20 <ljForce.extracted+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code