OV - exec - Loop 64

0x4089b0 MOV	(%RDI,%R9,4),%R11D    [3]

0x4089b4 MOV	%R11D,(%R13)    [2]

0x4089b8 MOV	(%R8,%R9,4),%R11D    [1]

0x4089bc MOV	%R11D,0x4(%R13)    [2]

0x4089c0 VPBROADCASTQ	0x10(%RAX,%R10,4),%YMM0    [4]

0x4089c7 VMOVDQU	(%RAX,%R10,4),%XMM1    [4]

0x4089cd VPBLENDD	$0x30,%YMM0,%YMM1,%YMM0

0x4089d3 VPBROADCASTQ	(%RCX,%R10,4),%YMM1    [5]

0x4089d9 VPBLENDD	$-0x40,%YMM1,%YMM0,%YMM0

0x4089df VMOVDQU	%YMM0,0x8(%R13)    [2]

0x4089e5 VMOVDQU	0x8(%RCX,%R10,4),%XMM0    [5]

0x4089ec VMOVDQU	%XMM0,0x28(%R13)    [2]

0x4089f2 INC	%R9

0x4089f5 ADD	$0x38,%R13

0x4089f9 ADD	$0x6,%R10

0x4089fd CMP	%R9,%RDX

0x408a00 JNE	4089b0

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 621 - 629

--------------------------------------------------------------------------------

621:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

622:    {

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

629:       tmp[iTmp].py =   atoms->p[ii][1];

Coverage (%)	Name	Source Location	Module
►14.73+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►14.07+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►12.60+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.95+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.95+	redistributeAtoms.extracted	timestep.c:153	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►11.46+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►10.80+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►10.64+	redistributeAtoms.extracted	timestep.c:154	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P6, P7, P8, P9,
Function	sortAtomsInCell
Source	haloExchange.c:621-629
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.44
Front-end cycles	2.00
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	16.00
Nb loads	6.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	44.80
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	50.00
Vectorization ratio load	33.33
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	22.92
Vector-efficiency ratio load	14.58
Vector-efficiency ratio store	21.88
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	31.25

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P6, P7, P8, P9,
Function	sortAtomsInCell
Source	haloExchange.c:621-629
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.44
Front-end cycles	2.00
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	16.00
Nb loads	6.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	44.80
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	56.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	50.00
Vectorization ratio load	33.33
Vectorization ratio store	50.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	22.92
Vector-efficiency ratio load	14.58
Vector-efficiency ratio store	21.88
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	31.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	sortAtomsInCell
Source file and lines	haloExchange.c:621-629
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621-629.

The related source loop is multi-versionned.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.50 to 1.50 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.00 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	17
nb uops	16
loop length	82
used x86 registers	9
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	2.50	2.50	2.50	2.50	1.00	1.00	1.00	1.00	1.00	1.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	2.50	2.50	2.50	2.50	1.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	2.50
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

all	50%
load	33%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	22%
load	14%
store	21%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

8% of peak load performance is reached (22.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (22.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4089b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%RDI,%R9,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %R11D,(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%R8,%R9,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %R11D,0x4(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VPBROADCASTQ 0x10(%RAX,%R10,4),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVDQU (%RAX,%R10,4),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPBLENDD $0x30,%YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPBROADCASTQ (%RCX,%R10,4),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBLENDD $-0x40,%YMM1,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQU %YMM0,0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x8(%RCX,%R10,4),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVDQU %XMM0,0x28(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x38,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x6,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4089b0 <sortAtomsInCell+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	sortAtomsInCell
Source file and lines	haloExchange.c:621-629
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:621-629.

The related source loop is multi-versionned.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.50 to 1.50 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX loads are used in vector version.
50% of SSE/AVX stores are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.00 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 56 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	17
nb uops	16
loop length	82
used x86 registers	9
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.00 cycles
front end	2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	2.50	2.50	2.50	2.50	1.00	1.00	1.00	1.00	1.00	1.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	2.50	2.50	2.50	2.50	1.00	1.00	1.00	1.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Dispatch	2.50
Data deps.	1.00
Overall L1	2.50

Vectorization ratios

all	50%
load	33%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	22%
load	14%
store	21%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

8% of peak load performance is reached (22.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (22.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4089b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%RDI,%R9,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %R11D,(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%R8,%R9,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %R11D,0x4(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VPBROADCASTQ 0x10(%RAX,%R10,4),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVDQU (%RAX,%R10,4),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPBLENDD $0x30,%YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPBROADCASTQ (%RCX,%R10,4),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBLENDD $-0x40,%YMM1,%YMM0,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQU %YMM0,0x8(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQU 0x8(%RCX,%R10,4),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVDQU %XMM0,0x28(%R13)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x38,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x6,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4089b0 <sortAtomsInCell+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code