OV - exec - Loop 108

	Loop Id: 108	Module: exec	Source: timestep.c:107-116	Coverage: 0.03%

0x410490 VPBROADCASTD	%R11D,%YMM16

0x410496 VPBROADCASTQ	%R13,%ZMM15

0x41049c XOR	%R10D,%R10D

0x41049f LEA	(%RDI,%RAX,1),%EDX

0x4104a2 SAL	$0x6,%EDX

0x4104a5 VPBROADCASTD	%R10D,%YMM17

0x4104ab VPSUBD	%YMM17,%YMM16,%YMM16

0x4104b1 VPCMPNLEUD	%YMM1,%YMM16,%K1

0x4104b8 VPBROADCASTQ	%RDX,%ZMM16

0x4104be VPADDD	%YMM1,%YMM17,%YMM17

0x4104c4 VPMOVSXDQ	%YMM17,%ZMM17

0x4104ca VPADDQ	%ZMM17,%ZMM16,%ZMM16

0x4104d0 VPMULLQ	%ZMM2,%ZMM16,%ZMM16

0x4104d6 MOVSXD	%R10D,%R10

0x4104d9 ADD	%RDX,%R10

0x4104dc VMOVDQU32	(%R9,%R10,4),%YMM17{%K1}{z}

0x4104e3 VMOVDQA32	%YMM17,%YMM14{%K1}

0x4104e9 KMOVQ	%K1,%K2

0x4104ee VPXORD	%XMM17,%XMM17,%XMM17

0x4104f4 VGATHERQPD	(%R8,%ZMM16,1),%ZMM17{%K2}

0x4104fb VMOVAPD	%ZMM17,%ZMM13{%K1}

0x410501 VMULPD	%ZMM13,%ZMM13,%ZMM17

0x410507 KMOVQ	%K1,%K2

0x41050c VXORPD	%XMM18,%XMM18,%XMM18

0x410512 VGATHERQPD	0x8(%R8,%ZMM16,1),%ZMM18{%K2}

0x41051a VMOVAPD	%ZMM18,%ZMM12{%K1}

0x410520 VFMADD231PD	%ZMM12,%ZMM12,%ZMM17

0x410526 KMOVQ	%K1,%K2

0x41052b VXORPD	%XMM18,%XMM18,%XMM18

0x410531 VGATHERQPD	0x10(%R8,%ZMM16,1),%ZMM18{%K2}

0x410539 VMOVAPD	%ZMM18,%ZMM11{%K1}

0x41053f VFMADD231PD	%ZMM11,%ZMM11,%ZMM17

0x410545 VMULPD	%ZMM3,%ZMM17,%ZMM16

0x41054b VPMOVSXDQ	%YMM14,%ZMM17

0x410551 VPSLLQ	$0x4,%ZMM17,%ZMM17

0x410558 VPADDQ	%ZMM17,%ZMM15,%ZMM15

0x41055e KMOVQ	%K1,%K2

0x410563 VPXORD	%XMM17,%XMM17,%XMM17

0x410569 VGATHERQPD	0x8(,%ZMM15,1),%ZMM17{%K2}

0x410574 VDIVPD	%ZMM17,%ZMM16,%ZMM15{%K1}{z}

0x41057a VMOVAPD	%ZMM17,%ZMM10{%K1}

0x410580 VEXTRACTF64X4	$0x1,%ZMM15,%YMM16

0x410587 VADDPD	%ZMM16,%ZMM15,%ZMM15

0x41058d VEXTRACTF32X4	$0x1,%YMM15,%XMM16

0x410594 VADDPD	%XMM16,%XMM15,%XMM15

0x41059a VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

0x4105a1 VADDSD	%XMM16,%XMM15,%XMM15

0x4105a7 VADDSD	%XMM0,%XMM15,%XMM0

0x4105ab LEA	0x1(%RDI),%RDX

0x4105af ADD	$0x40,%ESI

0x4105b2 CMP	%R12,%RDI

0x4105b5 MOV	%RDX,%RDI

0x4105b8 JE	410397

0x4105be LEA	(%RDI,%RAX,1),%RDX

0x4105c2 MOV	(%RBX,%RDX,4),%R11D

0x4105c6 TEST	%R11D,%R11D

0x4105c9 JLE	4105ab

0x4105cb MOV	-0x58(%RBP),%R8

0x4105cf MOV	0x20(%R8),%RDX

0x4105d3 MOV	0x28(%R8),%R13

0x4105d7 MOV	0x10(%RDX),%R9

0x4105db MOV	0x20(%RDX),%R8

0x4105df MOV	%R11D,%R10D

0x4105e2 AND	$-0x8,%R10D

0x4105e6 JE	410490

0x4105ec MOV	%RBX,%RCX

0x4105ef MOV	%ESI,%R14D

0x4105f2 LEA	(,%R14,8),%RDX

0x4105fa LEA	(%RDX,%RDX,2),%R15

0x4105fe SAL	$0x2,%R14

0x410602 LEA	-0x1(%R10),%EBX

0x410606 VPBROADCASTQ	%R13,%ZMM15

0x41060c ADD	%R8,%R15

0x41060f ADD	%R9,%R14

0x410612 VXORPD	%XMM16,%XMM16,%XMM16

0x410618 XOR	%EDX,%EDX

0x41061a NOPW	(%RAX,%RAX,1)

  (109) 0x410620 VPMOVSXDQ	(%R14,%RDX,4),%ZMM17

  (109) 0x410627 VMOVUPD	(%R15),%ZMM18

  (109) 0x41062d VMOVUPD	0x40(%R15),%ZMM19

  (109) 0x410634 VMOVUPD	0x80(%R15),%ZMM20

  (109) 0x41063b VMULPD	%ZMM20,%ZMM20,%ZMM20

  (109) 0x410641 VMULPD	%ZMM19,%ZMM19,%ZMM19

  (109) 0x410647 VMULPD	%ZMM18,%ZMM18,%ZMM18

  (109) 0x41064d VMOVAPD	%ZMM18,%ZMM21

  (109) 0x410653 VPERMT2PD	%ZMM19,%ZMM4,%ZMM21

  (109) 0x410659 VPERMT2PD	%ZMM20,%ZMM5,%ZMM21

  (109) 0x41065f VMOVAPD	%ZMM18,%ZMM22

  (109) 0x410665 VPERMT2PD	%ZMM19,%ZMM6,%ZMM22

  (109) 0x41066b VPERMT2PD	%ZMM20,%ZMM7,%ZMM22

  (109) 0x410671 VADDPD	%ZMM21,%ZMM22,%ZMM21

  (109) 0x410677 VPERMT2PD	%ZMM18,%ZMM8,%ZMM19

  (109) 0x41067d VPERMT2PD	%ZMM20,%ZMM9,%ZMM19

  (109) 0x410683 VADDPD	%ZMM19,%ZMM21,%ZMM18

  (109) 0x410689 VPSLLQ	$0x4,%ZMM17,%ZMM17

  (109) 0x410690 VXORPD	%XMM19,%XMM19,%XMM19

  (109) 0x410696 KXNORW	%K0,%K0,%K1

  (109) 0x41069a VMULPD	%ZMM3,%ZMM18,%ZMM18

  (109) 0x4106a0 VGATHERQPD	0x8(%R13,%ZMM17,1),%ZMM19{%K1}

  (109) 0x4106a8 VDIVPD	%ZMM19,%ZMM18,%ZMM17

  (109) 0x4106ae VADDPD	%ZMM16,%ZMM17,%ZMM16

  (109) 0x4106b4 ADD	$0xc0,%R15

  (109) 0x4106bb ADD	$0x8,%RDX

  (109) 0x4106bf CMP	%EBX,%EDX

  (109) 0x4106c1 JLE	410620

0x4106c7 VEXTRACTF64X4	$0x1,%ZMM16,%YMM17

0x4106ce VADDPD	%ZMM17,%ZMM16,%ZMM16

0x4106d4 VEXTRACTF32X4	$0x1,%YMM16,%XMM17

0x4106db VADDPD	%XMM17,%XMM16,%XMM16

0x4106e1 VSHUFPD	$0x1,%XMM16,%XMM16,%XMM17

0x4106e8 VADDSD	%XMM17,%XMM16,%XMM16

0x4106ee VADDSD	%XMM16,%XMM0,%XMM0

0x4106f4 CMP	%R10D,%R11D

0x4106f7 JNE	410701

0x4106f9 MOV	%RCX,%RBX

0x4106fc JMP	4105ab

0x410701 VPBROADCASTD	%R11D,%YMM16

0x410707 MOV	%RCX,%RBX

0x41070a JMP	41049f

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116

--------------------------------------------------------------------------------

107:    #pragma omp parallel for reduction(+:kenergy)

108:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

109:    {

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Coverage (%)	Name	Source Location	Module
►95.07+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.91+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:120	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.51
Bottlenecks
Function	kineticEnergy.extracted
Source	timestep.c:107-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.09
CQA cycles if no scalar integer	16.09
CQA cycles if FP arith vectorized	17.21
CQA cycles if fully vectorized	14.04
Front-end cycles	18.09
P0 cycles	2.42
P1 cycles	2.42
P2 cycles	2.42
P3 cycles	2.42
P4 cycles	2.42
P5 cycles	2.42
P6 cycles	5.31
P7 cycles	5.31
P8 cycles	5.31
P9 cycles	5.31
P10 cycles	11.44
P11 cycles	11.56
P12 cycles	11.94
P13 cycles	11.81
P14 cycles	10.00
P15 cycles	10.00
DIV/SQRT cycles	2.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	144.75
Nb loads	7.25
Nb stores	0.00
Nb stack references	0.75
FLOP/cycle	2.21
Nb FLOP add-sub	12.00
Nb FLOP mul	8.00
Nb FLOP fma	8.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.21
Bytes prefetched	0.00
Bytes loaded	178.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	47.41
Vectorization ratio load	55.56
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	39.29
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	51.85
Vector-efficiency ratio all	35.79
Vector-efficiency ratio load	55.56
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	32.32
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	33.94

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.71
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.00
Bottlenecks	micro-operation queue,
Function	kineticEnergy.extracted
Source	timestep.c:107-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.00
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.00
CQA cycles if fully vectorized	0.07
Front-end cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.25
P9 cycles	0.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	8.00
Nb loads	1.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00
Bytes prefetched	0.00
Bytes loaded	4.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	micro-operation queue,
Function	kineticEnergy.extracted
Source	timestep.c:107-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	31.88
CQA cycles if no scalar integer	29.50
CQA cycles if FP arith vectorized	30.65
CQA cycles if fully vectorized	25.59
Front-end cycles	31.88
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	21.50
P11 cycles	21.50
P12 cycles	21.50
P13 cycles	21.50
P14 cycles	20.00
P15 cycles	20.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	255.00
Nb loads	11.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	2.13
Nb FLOP add-sub	12.00
Nb FLOP mul	16.00
Nb FLOP fma	16.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.42
Bytes prefetched	0.00
Bytes loaded	332.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	78.57
Vectorization ratio load	83.33
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	66.67
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	80.00
Vector-efficiency ratio all	58.78
Vector-efficiency ratio load	77.08
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	50.69
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	54.00

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67
Bottlenecks	micro-operation queue,
Function	kineticEnergy.extracted
Source	timestep.c:107-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	4.69
CQA cycles if fully vectorized	3.66
Front-end cycles	5.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	1.00
P11 cycles	1.50
P12 cycles	3.00
P13 cycles	2.50
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	40.00
Nb loads	6.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	2.40
Nb FLOP add-sub	12.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.80
Bytes prefetched	0.00
Bytes loaded	44.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	37.50
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	33.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	22.66
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	28.13
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.09

Metric	Value
CQA speedup if no scalar integer	1.12
CQA speedup if FP arith vectorized	1.06
CQA speedup if fully vectorized	1.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	micro-operation queue,
Function	kineticEnergy.extracted
Source	timestep.c:107-116
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.50
CQA cycles if no scalar integer	30.88
CQA cycles if FP arith vectorized	32.49
CQA cycles if fully vectorized	26.83
Front-end cycles	34.50
P0 cycles	3.67
P1 cycles	3.67
P2 cycles	3.67
P3 cycles	3.67
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	9.75
P7 cycles	9.75
P8 cycles	9.75
P9 cycles	9.75
P10 cycles	23.25
P11 cycles	23.25
P12 cycles	23.25
P13 cycles	23.25
P14 cycles	20.00
P15 cycles	20.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	86.00
Nb uops	276.00
Nb loads	11.00
Nb stores	0.00
Nb stack references	1.00
FLOP/cycle	2.32
Nb FLOP add-sub	24.00
Nb FLOP mul	16.00
Nb FLOP fma	16.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.62
Bytes prefetched	0.00
Bytes loaded	332.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	1.00
Vectorization ratio all	73.58
Vectorization ratio load	83.33
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	57.14
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	77.42
Vector-efficiency ratio all	52.36
Vector-efficiency ratio load	77.08
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	44.20
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	48.19

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy.extracted
Source file and lines	timestep.c:107-116
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 18.09 to 14.04 cycles (1.29x speedup).

Details

47% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

55% of SSE/AVX loads are used in vector version.
39% of SSE/AVX addition or subtraction instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 18.09x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (8 inside FMA instructions)
16: multiply (8 inside FMA instructions)
4: divide

The binary loop is loading 178 bytes (22 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	50
nb uops	144.75
loop length	251
used x86 registers	12.25
used mmx registers	0
used xmm registers	3.25
used ymm registers	3
used zmm registers	5.75
nb stack references	0.75

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	18.09 cycles
front end	18.09 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.42	2.42	2.42	2.42	2.42	2.42	5.31	5.31	5.31	5.31	11.44	11.56	11.94	11.81	10.00	10.00
cycles	2.42	2.42	2.42	2.42	2.42	2.42	5.31	5.31	5.31	5.31	11.44	11.56	11.94	11.81	10.00	10.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	2.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	18.09
Dispatch	12.19
DIV/SQRT	2.00
Data deps.	0.00
Overall L1	18.09

Vectorization ratios

INT

all	30%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	36%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	84%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	47%
load	55%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	39%
fma	100%
div/sqrt	100%
other	51%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	56%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	55%

INT+FP

all	35%
load	55%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	32%
fma	100%
div/sqrt	100%
other	33%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.09 cycles. At this rate:

3% of peak load performance is reached (8.21 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	kineticEnergy.extracted
Source file and lines	timestep.c:107-116
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.00 to 0.07 cycles (13.71x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 4 bytes.

General properties

nb instructions	9
nb uops	8
loop length	32
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.25	0.25	0.25	0.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.25	0.25	0.25	0.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	1.00
Dispatch	1.00
Data deps.	0.00
Overall L1	1.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.00 cycles. At this rate:

1% of peak load performance is reached (4.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.00 to 0.25 cycles (4.00x speedup).

ASM code

In the binary file, the address of the loop is: 4105be

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD $0x40,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 410397 <kineticEnergy.extracted+0x77>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA (%RDI,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV (%RBX,%RDX,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JLE 4105ab <kineticEnergy.extracted+0x28b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A

Function	kineticEnergy.extracted
Source file and lines	timestep.c:107-116
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.88 to 29.50 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 58% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 31.88 to 25.59 cycles (1.25x speedup).

Details

78% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

83% of SSE/AVX loads are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
80% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:115
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:116
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110
VPBROADCASTQ: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:112

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:115
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:116
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 6 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (16 inside FMA instructions)
32: multiply (16 inside FMA instructions)
8: divide

The binary loop is loading 332 bytes (41 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	255
loop length	348
used x86 registers	12
used mmx registers	0
used xmm registers	5
used ymm registers	5
used zmm registers	10
nb stack references	1
ADD-SUB / MUL ratio	2.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	31.88 cycles
front end	31.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.00	2.00	2.00	2.00	2.00	2.00	9.75	9.75	9.75	9.75	21.50	21.50	21.50	21.50	20.00	20.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	9.75	9.75	9.75	9.75	21.50	21.50	21.50	21.50	20.00	20.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	31.88
Dispatch	21.50
DIV/SQRT	4.00
Data deps.	0.00
Overall L1	31.88

Vectorization ratios

INT

all	65%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	80%
fma	NA (no fma vectorizable/vectorized instructions)
other	58%

all	90%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	78%
load	83%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	66%
fma	100%
div/sqrt	100%
other	80%

Vector efficiency ratios

INT

all	43%
load	31%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	61%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	72%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	73%

INT+FP

all	58%
load	77%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	54%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.88 cycles. At this rate:

4% of peak load performance is reached (10.42 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4105be

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VPBROADCASTD %R11D,%YMM16	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPBROADCASTQ %R13,%ZMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RDI,%RAX,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x6,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VPBROADCASTD %R10D,%YMM17	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPSUBD %YMM17,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPNLEUD %YMM1,%YMM16,%K1																				vect (50.0%)
VPBROADCASTQ %RDX,%ZMM16	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDD %YMM1,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMOVSXDQ %YMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDQ %ZMM17,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPMULLQ %ZMM2,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVSXD %R10D,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU32 (%R9,%R10,4),%YMM17{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA32 %YMM17,%YMM14{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VPXORD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VGATHERQPD (%R8,%ZMM16,1),%ZMM17{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM17,%ZMM13{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMULPD %ZMM13,%ZMM13,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERQPD 0x8(%R8,%ZMM16,1),%ZMM18{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM18,%ZMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM12,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERQPD 0x10(%R8,%ZMM16,1),%ZMM18{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM18,%ZMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM11,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM17,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPMOVSXDQ %YMM14,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPSLLQ $0x4,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM17,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VPXORD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VGATHERQPD 0x8(,%ZMM15,1),%ZMM17{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VDIVPD %ZMM17,%ZMM16,%ZMM15{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMOVAPD %ZMM17,%ZMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM15,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM16,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF32X4 $0x1,%YMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM16,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM15,%XMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM16,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM0,%XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA 0x1(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x40,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 410397 <kineticEnergy.extracted+0x77>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RDI,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RBX,%RDX,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 4105ab <kineticEnergy.extracted+0x28b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 410490 <kineticEnergy.extracted+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	kineticEnergy.extracted
Source file and lines	timestep.c:107-116
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 3.00 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 5.00 to 3.66 cycles (1.37x speedup).

Details

37% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
VEXTRACTF64X4: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

12: addition or subtraction

The binary loop is loading 44 bytes (5 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	40
loop length	175
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	3
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	1.50	1.50	1.50	1.50	1.00	1.50	3.00	2.50	0.00	0.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	1.50	1.50	1.50	1.50	1.00	1.50	3.00	2.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.00
Dispatch	3.00
Data deps.	0.00
Overall L1	5.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	75%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	37%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	34%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	37%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

INT+FP

all	22%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	28%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

3% of peak load performance is reached (8.80 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4105be

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
LEA 0x1(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x40,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 410397 <kineticEnergy.extracted+0x77>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RDI,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RBX,%RDX,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 4105ab <kineticEnergy.extracted+0x28b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x20(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R11D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 410490 <kineticEnergy.extracted+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R14,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDX,%RDX,2),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x2,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x1(%R10),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VPBROADCASTQ %R13,%ZMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
ADD %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R9,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VEXTRACTF64X4 $0x1,%ZMM16,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	4	0.50	vect (50.0%)
VADDPD %ZMM17,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (100.0%)
VEXTRACTF32X4 $0x1,%YMM16,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
VADDPD %XMM17,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM16,%XMM16,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
VADDSD %XMM17,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
VADDSD %XMM16,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
CMP %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 410701 <kineticEnergy.extracted+0x3e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 4105ab <kineticEnergy.extracted+0x28b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A

Function	kineticEnergy.extracted
Source file and lines	timestep.c:107-116
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 34.50 to 30.88 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 52% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 34.50 to 26.83 cycles (1.29x speedup).

Details

73% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

83% of SSE/AVX loads are used in vector version.
57% of SSE/AVX addition or subtraction instructions are used in vector version.
77% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VGATHERQPD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:115
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:116
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110
VPBROADCASTQ: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:112
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF32X4: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERQPD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:115
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:116
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:113

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

40: addition or subtraction (16 inside FMA instructions)
32: multiply (16 inside FMA instructions)
8: divide

The binary loop is loading 332 bytes (41 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	86
nb uops	276
loop length	449
used x86 registers	15
used mmx registers	0
used xmm registers	5
used ymm registers	5
used zmm registers	10
nb stack references	1
ADD-SUB / MUL ratio	4.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	34.50 cycles
front end	34.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.67	3.67	3.67	3.67	3.67	3.67	9.75	9.75	9.75	9.75	23.25	23.25	23.25	23.25	20.00	20.00
cycles	3.67	3.67	3.67	3.67	3.67	3.67	9.75	9.75	9.75	9.75	23.25	23.25	23.25	23.25	20.00	20.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	34.50
Dispatch	23.25
DIV/SQRT	4.00
Data deps.	0.00
Overall L1	34.50

Vectorization ratios

INT

all	56%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	86%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	73%
load	83%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	57%
fma	100%
div/sqrt	100%
other	77%

Vector efficiency ratios

INT

all	39%
load	31%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	53%
fma	NA (no fma vectorizable/vectorized instructions)
other	29%

all	62%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	63%

INT+FP

all	52%
load	77%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	44%
fma	100%
div/sqrt	100%
other	48%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.50 cycles. At this rate:

3% of peak load performance is reached (9.62 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4105be

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
LEA (%RDI,%RAX,1),%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x6,%EDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VPBROADCASTD %R10D,%YMM17	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPSUBD %YMM17,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPNLEUD %YMM1,%YMM16,%K1																				vect (50.0%)
VPBROADCASTQ %RDX,%ZMM16	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDD %YMM1,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMOVSXDQ %YMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDQ %ZMM17,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPMULLQ %ZMM2,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVSXD %R10D,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQU32 (%R9,%R10,4),%YMM17{%K1}{z}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA32 %YMM17,%YMM14{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VPXORD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VGATHERQPD (%R8,%ZMM16,1),%ZMM17{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM17,%ZMM13{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMULPD %ZMM13,%ZMM13,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERQPD 0x8(%R8,%ZMM16,1),%ZMM18{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM18,%ZMM12{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD %ZMM12,%ZMM12,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERQPD 0x10(%R8,%ZMM16,1),%ZMM18{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VMOVAPD %ZMM18,%ZMM11{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VFMADD231PD %ZMM11,%ZMM11,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
VMULPD %ZMM3,%ZMM17,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
VPMOVSXDQ %YMM14,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPSLLQ $0x4,%ZMM17,%ZMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM17,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VPXORD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VGATHERQPD 0x8(,%ZMM15,1),%ZMM17{%K2}	48	0	0	0	0	0	0	2	2	2	2	2.50	4	4.50	3	5	5	0-16	8.94	vect (100.0%)
VDIVPD %ZMM17,%ZMM16,%ZMM15{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (100.0%)
VMOVAPD %ZMM17,%ZMM10{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM15,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM16,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF32X4 $0x1,%YMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM16,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM15,%XMM15,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM16,%XMM15,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM0,%XMM15,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
LEA 0x1(%RDI),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x40,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JE 410397 <kineticEnergy.extracted+0x77>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RDI,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RBX,%RDX,4),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
TEST %R11D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 4105ab <kineticEnergy.extracted+0x28b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%R8),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 410490 <kineticEnergy.extracted+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R14,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDX,%RDX,2),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x2,%R14	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x1(%R10),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VPBROADCASTQ %R13,%ZMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
ADD %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %R9,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VEXTRACTF64X4 $0x1,%ZMM16,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM17,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF32X4 $0x1,%YMM16,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM17,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM16,%XMM16,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM17,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM16,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 410701 <kineticEnergy.extracted+0x3e1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTD %R11D,%YMM16	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 41049f <kineticEnergy.extracted+0x17f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set