OV - exec - Loop 101

	Loop Id: 101	Module: exec	Source: timestep.c:74-78	Coverage: 1.48%

0x40fad0 VMOVUPD	(%R9,%R12,1),%ZMM23    [2]

0x40fad7 VMOVUPD	(%R8,%R12,1),%ZMM24    [1]

0x40fade VMOVUPD	0x40(%R9,%R12,1),%ZMM25    [2]

0x40fae6 VMOVUPD	0x40(%R8,%R12,1),%ZMM26    [1]

0x40faee VMOVUPD	0x80(%R9,%R12,1),%ZMM27    [2]

0x40faf6 VMOVAPD	%ZMM23,%ZMM28

0x40fafc VMOVAPD	%ZMM23,%ZMM29

0x40fb02 VMOVAPD	%ZMM24,%ZMM30

0x40fb08 VPERMT2PD	%ZMM25,%ZMM4,%ZMM28

0x40fb0e VPERMT2PD	%ZMM25,%ZMM6,%ZMM29

0x40fb14 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

0x40fb1a VMOVAPD	%ZMM24,%ZMM23

0x40fb20 VPERMT2PD	%ZMM26,%ZMM4,%ZMM30

0x40fb26 VPERMT2PD	%ZMM26,%ZMM6,%ZMM23

0x40fb2c VPERMT2PD	%ZMM24,%ZMM8,%ZMM26

0x40fb32 VMOVUPD	0x80(%R8,%R12,1),%ZMM24    [1]

0x40fb3a VPERMT2PD	%ZMM27,%ZMM5,%ZMM28

0x40fb40 VPERMT2PD	%ZMM27,%ZMM7,%ZMM29

0x40fb46 VPERMT2PD	%ZMM24,%ZMM5,%ZMM30

0x40fb4c VPERMT2PD	%ZMM24,%ZMM7,%ZMM23

0x40fb52 VFMADD231PD	%ZMM28,%ZMM1,%ZMM30

0x40fb58 VFMADD231PD	%ZMM29,%ZMM1,%ZMM23

0x40fb5e VPERMT2PD	%ZMM27,%ZMM9,%ZMM25

0x40fb64 VPERMT2PD	%ZMM24,%ZMM9,%ZMM26

0x40fb6a VFMADD231PD	%ZMM25,%ZMM1,%ZMM26

0x40fb70 VMOVAPD	%ZMM23,%ZMM24

0x40fb76 VMOVAPD	%ZMM30,%ZMM25

0x40fb7c VPERMT2PD	%ZMM30,%ZMM10,%ZMM24

0x40fb82 VPERMT2PD	%ZMM23,%ZMM11,%ZMM25

0x40fb88 VPERMT2PD	%ZMM23,%ZMM12,%ZMM30

0x40fb8e VPERMT2PD	%ZMM26,%ZMM13,%ZMM30

0x40fb94 VPERMT2PD	%ZMM26,%ZMM14,%ZMM25

0x40fb9a VPERMT2PD	%ZMM26,%ZMM15,%ZMM24

0x40fba0 VMOVUPD	%ZMM24,0x80(%R8,%R12,1)    [1]

0x40fba8 VMOVUPD	%ZMM25,0x40(%R8,%R12,1)    [1]

0x40fbb0 VMOVUPD	%ZMM30,(%R8,%R12,1)    [1]

0x40fbb7 ADD	$0x8,%R14D

0x40fbbb ADD	$0xc0,%R12

0x40fbc2 CMP	%R13D,%R14D

0x40fbc5 JLE	40fad0

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78

--------------------------------------------------------------------------------

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module
►96.42+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.02+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:71	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.85
Bottlenecks	P11, P12,
Function	advanceVelocity.extracted
Source	timestep.c:74-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	4.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	3.00
P11 cycles	9.00
P12 cycles	9.00
P13 cycles	0.00
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	6.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	5.33
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.85
Bottlenecks	P11, P12,
Function	advanceVelocity.extracted
Source	timestep.c:74-78
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	9.00
Front-end cycles	4.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	2.25
P7 cycles	2.25
P8 cycles	2.25
P9 cycles	2.25
P10 cycles	3.00
P11 cycles	9.00
P12 cycles	9.00
P13 cycles	0.00
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	6.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	5.33
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	24.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	192.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity.extracted
Source file and lines	timestep.c:74-78
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74-78.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.00 to 4.88 cycles (1.85x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 24 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 9 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 9 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)

The binary loop is loading 384 bytes (48 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	39
loop length	251
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	21
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	2.25	2.25	2.25	2.25	3.00	9.00	9.00	0.00	1.50	1.50
cycles	0.50	0.50	0.50	0.50	0.50	0.50	2.25	2.25	2.25	2.25	3.00	9.00	9.00	0.00	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.88
Dispatch	9.00
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

16% of peak load performance is reached (42.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40fad0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R9,%R12,1),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R8,%R12,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R9,%R12,1),%ZMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R8,%R12,1),%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R9,%R12,1),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM23,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM23,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM24,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM25,%ZMM4,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM25,%ZMM6,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM24,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM4,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM6,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM8,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD 0x80(%R8,%R12,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VPERMT2PD %ZMM27,%ZMM5,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM27,%ZMM7,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM5,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM7,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM1,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM1,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VPERMT2PD %ZMM27,%ZMM9,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM9,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM1,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM23,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM30,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM30,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM11,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM12,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM13,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM14,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM15,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD %ZMM24,0x80(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM25,0x40(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM30,(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0xc0,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 40fad0 <advanceVelocity.extracted+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	advanceVelocity.extracted
Source file and lines	timestep.c:74-78
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 24 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 9 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 9 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction (all inside FMA instructions)
24: multiply (all inside FMA instructions)

The binary loop is loading 384 bytes (48 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	39
loop length	251
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	21
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	0.50	0.50	0.50	0.50	2.25	2.25	2.25	2.25	3.00	9.00	9.00	0.00	1.50	1.50
cycles	0.50	0.50	0.50	0.50	0.50	0.50	2.25	2.25	2.25	2.25	3.00	9.00	9.00	0.00	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.88
Dispatch	9.00
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

16% of peak load performance is reached (42.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40fad0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P14	P15	Latency	Recip. throughput	Vectorization
VMOVUPD (%R9,%R12,1),%ZMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD (%R8,%R12,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R9,%R12,1),%ZMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x40(%R8,%R12,1),%ZMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x80(%R9,%R12,1),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPD %ZMM23,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM23,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM24,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM25,%ZMM4,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM25,%ZMM6,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM8,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVAPD %ZMM24,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM4,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM6,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM8,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD 0x80(%R8,%R12,1),%ZMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VPERMT2PD %ZMM27,%ZMM5,%ZMM28	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM27,%ZMM7,%ZMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM5,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM7,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VFMADD231PD %ZMM28,%ZMM1,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VFMADD231PD %ZMM29,%ZMM1,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VPERMT2PD %ZMM27,%ZMM9,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM24,%ZMM9,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VFMADD231PD %ZMM25,%ZMM1,%ZMM26	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (100.0%)
VMOVAPD %ZMM23,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VMOVAPD %ZMM30,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (100.0%)
VPERMT2PD %ZMM30,%ZMM10,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM11,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM23,%ZMM12,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM13,%ZMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM14,%ZMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VPERMT2PD %ZMM26,%ZMM15,%ZMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	5	0.50	vect (100.0%)
VMOVUPD %ZMM24,0x80(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM25,0x40(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
VMOVUPD %ZMM30,(%R8,%R12,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	4	1	vect (100.0%)
ADD $0x8,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0xc0,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 40fad0 <advanceVelocity.extracted+0x350>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code