OV - exec - Function advancePosition.extracted

	Function: advancePosition.extracted	Module: exec	Source: timestep.c:85-94	Coverage (incl. loops): 1.15% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 85 - 94

--------------------------------------------------------------------------------

85:    #pragma omp parallel for

86:    for (int iBox=0; iBox<nBoxes; iBox++)

87:    {

88:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

89:       {

90:          int iSpecies = s->atoms->iSpecies[iOff];

91:          real_t invMass = 1.0/s->species[iSpecies].mass;

92:          s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass;

93:          s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass;

94:          s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass;

0x40fbe0 PUSH	%RBP

0x40fbe1 MOV	%RSP,%RBP

0x40fbe4 PUSH	%R15

0x40fbe6 PUSH	%R14

0x40fbe8 PUSH	%R13

0x40fbea PUSH	%R12

0x40fbec PUSH	%RBX

0x40fbed AND	$-0x40,%RSP

0x40fbf1 SUB	$0x100,%RSP

0x40fbf8 MOV	%RCX,%R15

0x40fbfb MOV	%RDX,0x48(%RSP)

0x40fc00 MOVL	$0,0x44(%RSP)

0x40fc08 MOV	(%RDI),%ESI

0x40fc0a MOVL	$0,0x2c(%RSP)

0x40fc12 MOV	%R9D,0x28(%RSP)

0x40fc17 MOVL	$0x1,0x40(%RSP)

0x40fc1f SUB	$0x8,%RSP

0x40fc23 LEA	0x48(%RSP),%RAX

0x40fc28 LEA	0x4c(%RSP),%RCX

0x40fc2d LEA	0x34(%RSP),%R8

0x40fc32 LEA	0x30(%RSP),%R9

0x40fc37 MOV	$0x42e950,%EDI

0x40fc3c MOV	%ESI,0x44(%RSP)

0x40fc40 MOV	$0x22,%EDX

0x40fc45 PUSH	$0x1

0x40fc47 PUSH	$0x1

0x40fc49 PUSH	%RAX

0x40fc4a CALL	403230 <__kmpc_for_static_init_4@plt>

0x40fc4f ADD	$0x20,%RSP

0x40fc53 MOV	0x2c(%RSP),%EDX

0x40fc57 MOV	0x28(%RSP),%EAX

0x40fc5b MOV	%RAX,0x50(%RSP)

0x40fc60 CMP	%EAX,%EDX

0x40fc62 JBE	40fc83

0x40fc64 MOV	$0x42e970,%EDI

0x40fc69 MOV	0x3c(%RSP),%ESI

0x40fc6d LEA	-0x28(%RBP),%RSP

0x40fc71 POP	%RBX

0x40fc72 POP	%R12

0x40fc74 POP	%R13

0x40fc76 POP	%R14

0x40fc78 POP	%R15

0x40fc7a POP	%RBP

0x40fc7b VZEROUPPER

0x40fc7e JMP	4030f0

0x40fc83 VMOVQ	%R15,%XMM0

0x40fc88 MOV	0x48(%RSP),%RAX

0x40fc8d MOV	0x18(%RAX),%RCX

0x40fc91 MOV	0x78(%RCX),%RAX

0x40fc95 MOV	%RAX,0x58(%RSP)

0x40fc9a SUB	%RDX,0x50(%RSP)

0x40fc9f VPBROADCASTQ	%XMM0,%ZMM1

0x40fca5 MOV	%EDX,%ESI

0x40fca7 SAL	$0x6,%ESI

0x40fcaa XOR	%EDI,%EDI

0x40fcac VMOVUPD	0x1598a(%RIP),%ZMM4

0x40fcb6 VMOVUPD	0x159c0(%RIP),%ZMM5

0x40fcc0 VMOVUPD	0x159f6(%RIP),%ZMM6

0x40fcca VMOVUPD	0x15a2c(%RIP),%ZMM7

0x40fcd4 VMOVUPD	0x15a62(%RIP),%ZMM8

0x40fcde VMOVUPD	0x15a98(%RIP),%ZMM9

0x40fce8 VMOVUPD	0x15ace(%RIP),%ZMM10

0x40fcf2 VMOVUPD	0x15b04(%RIP),%ZMM11

0x40fcfc VMOVUPD	0x15b3a(%RIP),%ZMM12

0x40fd06 VMOVUPD	0x15b70(%RIP),%ZMM13

0x40fd10 VMOVUPD	0x15ba6(%RIP),%ZMM14

0x40fd1a VMOVUPD	0x15bdc(%RIP),%ZMM15

0x40fd24 MOV	%RDX,0x30(%RSP)

0x40fd29 JMP	40fea3

(103) 0x40fd2e XOR	%R14D,%R14D

(103) 0x40fd31 MOV	0x30(%RSP),%RDX

(103) 0x40fd36 VPBROADCASTD	%R14D,%YMM26

(103) 0x40fd3c VPSUBD	%YMM26,%YMM25,%YMM25

(103) 0x40fd42 VMOVDQU	0x14656(%RIP),%YMM2

(103) 0x40fd4a VPCMPNLEUD	%YMM2,%YMM25,%K1

(103) 0x40fd51 MOVSXD	%R14D,%RAX

(103) 0x40fd54 ADD	%R15,%RAX

(103) 0x40fd57 VMOVDQU32	(%R10,%RAX,4),%YMM25{%K1}{z}

(103) 0x40fd5e VMOVDQA32	%YMM25,%YMM23{%K1}

(103) 0x40fd64 VPMOVSXDQ	%YMM23,%ZMM25

(103) 0x40fd6a VPSLLQ	$0x4,%ZMM25,%ZMM25

(103) 0x40fd71 VPADDQ	%ZMM25,%ZMM24,%ZMM24

(103) 0x40fd77 VPXORD	%XMM25,%XMM25,%XMM25

(103) 0x40fd7d KMOVQ	%K1,%K2

(103) 0x40fd82 VGATHERQPD	0x8(,%ZMM24,1),%ZMM25{%K2}

(103) 0x40fd8d VPBROADCASTQ	%R15,%ZMM24

(103) 0x40fd93 VPADDD	%YMM2,%YMM26,%YMM26

(103) 0x40fd99 VPMOVSXDQ	%YMM26,%ZMM26

(103) 0x40fd9f VMOVAPD	%ZMM25,%ZMM22{%K1}

(103) 0x40fda5 VDIVPD	%ZMM22,%ZMM1,%ZMM25

(103) 0x40fdab VPADDQ	%ZMM26,%ZMM24,%ZMM24

(103) 0x40fdb1 VPMULLQ	0x1391d(%RIP){1to8},%ZMM24,%ZMM24

(103) 0x40fdbb VPXORD	%XMM26,%XMM26,%XMM26

(103) 0x40fdc1 KMOVQ	%K1,%K2

(103) 0x40fdc6 VGATHERQPD	(%R9,%ZMM24,1),%ZMM26{%K2}

(103) 0x40fdcd VMOVAPD	%ZMM26,%ZMM21{%K1}

(103) 0x40fdd3 VXORPD	%XMM26,%XMM26,%XMM26

(103) 0x40fdd9 KMOVQ	%K1,%K2

(103) 0x40fdde VGATHERQPD	(%R8,%ZMM24,1),%ZMM26{%K2}

(103) 0x40fde5 VMOVAPD	%ZMM26,%ZMM20{%K1}

(103) 0x40fdeb VMOVAPD	%ZMM21,%ZMM26

(103) 0x40fdf1 VFMADD213PD	%ZMM20,%ZMM25,%ZMM26

(103) 0x40fdf7 KMOVQ	%K1,%K2

(103) 0x40fdfc VSCATTERQPD	%ZMM26,(%R8,%ZMM24,1){%K2}

(103) 0x40fe03 VXORPD	%XMM26,%XMM26,%XMM26

(103) 0x40fe09 KMOVQ	%K1,%K2

(103) 0x40fe0e VGATHERQPD	0x8(%R9,%ZMM24,1),%ZMM26{%K2}

(103) 0x40fe16 VMOVAPD	%ZMM26,%ZMM19{%K1}

(103) 0x40fe1c VXORPD	%XMM26,%XMM26,%XMM26

(103) 0x40fe22 KMOVQ	%K1,%K2

(103) 0x40fe27 VGATHERQPD	0x8(%R8,%ZMM24,1),%ZMM26{%K2}

(103) 0x40fe2f VMOVAPD	%ZMM26,%ZMM18{%K1}

(103) 0x40fe35 VMOVAPD	%ZMM19,%ZMM26

(103) 0x40fe3b VFMADD213PD	%ZMM18,%ZMM25,%ZMM26

(103) 0x40fe41 KMOVQ	%K1,%K2

(103) 0x40fe46 VSCATTERQPD	%ZMM26,0x8(%R8,%ZMM24,1){%K2}

(103) 0x40fe4e VXORPD	%XMM26,%XMM26,%XMM26

(103) 0x40fe54 KMOVQ	%K1,%K2

(103) 0x40fe59 VGATHERQPD	0x10(%R9,%ZMM24,1),%ZMM26{%K2}

(103) 0x40fe61 VMOVAPD	%ZMM26,%ZMM17{%K1}

(103) 0x40fe67 VXORPD	%XMM26,%XMM26,%XMM26

(103) 0x40fe6d KMOVQ	%K1,%K2

(103) 0x40fe72 VGATHERQPD	0x10(%R8,%ZMM24,1),%ZMM26{%K2}

(103) 0x40fe7a VMOVAPD	%ZMM26,%ZMM16{%K1}

(103) 0x40fe80 VFMADD213PD	%ZMM16,%ZMM17,%ZMM25

(103) 0x40fe86 VSCATTERQPD	%ZMM25,0x10(%R8,%ZMM24,1){%K1}

(103) 0x40fe8e LEA	0x1(%RDI),%RAX

(103) 0x40fe92 ADD	$0x40,%ESI

(103) 0x40fe95 CMP	0x50(%RSP),%RDI

(103) 0x40fe9a MOV	%RAX,%RDI

(103) 0x40fe9d JE	40fc64

(103) 0x40fea3 LEA	(%RDI,%RDX,1),%RCX

(103) 0x40fea7 MOV	0x58(%RSP),%RAX

(103) 0x40feac MOV	(%RAX,%RCX,4),%R11D

(103) 0x40feb0 TEST	%R11D,%R11D

(103) 0x40feb3 JLE	40fe8e

(103) 0x40feb5 MOV	%ESI,%ECX

(103) 0x40feb7 LEA	(,%RCX,4),%R13

(103) 0x40febf SAL	$0x3,%RCX

(103) 0x40fec3 LEA	(%RDI,%RDX,1),%R15D

(103) 0x40fec7 SAL	$0x6,%R15D

(103) 0x40fecb MOV	0x48(%RSP),%RAX

(103) 0x40fed0 MOV	0x20(%RAX),%RDX

(103) 0x40fed4 MOV	0x28(%RAX),%R12

(103) 0x40fed8 MOV	0x10(%RDX),%R10

(103) 0x40fedc MOV	0x18(%RDX),%R8

(103) 0x40fee0 MOV	0x20(%RDX),%R9

(103) 0x40fee4 LEA	-0x1(%R11),%EDX

(103) 0x40fee8 MOVSXD	%EDX,%RDX

(103) 0x40feeb ADD	%R15,%RDX

(103) 0x40feee SAL	$0x3,%RDX

(103) 0x40fef2 LEA	(%RDX,%RDX,2),%RDX

(103) 0x40fef6 LEA	(%R9,%RDX,1),%R14

(103) 0x40fefa ADD	$0x10,%R14

(103) 0x40fefe LEA	(,%R15,8),%RBX

(103) 0x40ff06 LEA	(%RBX,%RBX,2),%RBX

(103) 0x40ff0a LEA	(%R8,%RBX,1),%RAX

(103) 0x40ff0e CMP	%RAX,%R14

(103) 0x40ff11 JB	40ffb0

(103) 0x40ff17 ADD	%R9,%RBX

(103) 0x40ff1a LEA	(%R8,%RDX,1),%RAX

(103) 0x40ff1e ADD	$0x10,%RAX

(103) 0x40ff22 CMP	%RBX,%RAX

(103) 0x40ff25 JB	40ffb0

(103) 0x40ff2b LEA	(%RCX,%RCX,2),%RCX

(103) 0x40ff2f ADD	$0x10,%RCX

(103) 0x40ff33 ADD	%R13,%R10

(103) 0x40ff36 XOR	%EDX,%EDX

(103) 0x40ff38 NOPL	(%RAX,%RAX,1)

  (105) 0x40ff40 MOVSXD	(%R10,%RDX,4),%RAX

  (105) 0x40ff44 SAL	$0x4,%RAX

  (105) 0x40ff48 VDIVSD	0x8(%R12,%RAX,1),%XMM0,%XMM2

  (105) 0x40ff4f VMOVSD	-0x10(%R9,%RCX,1),%XMM3

  (105) 0x40ff56 VFMADD213SD	-0x10(%R8,%RCX,1),%XMM2,%XMM3

  (105) 0x40ff5d VMOVSD	%XMM3,-0x10(%R8,%RCX,1)

  (105) 0x40ff64 VMOVSD	-0x8(%R9,%RCX,1),%XMM3

  (105) 0x40ff6b VFMADD213SD	-0x8(%R8,%RCX,1),%XMM2,%XMM3

  (105) 0x40ff72 VMOVSD	%XMM3,-0x8(%R8,%RCX,1)

  (105) 0x40ff79 VMOVSD	(%R9,%RCX,1),%XMM3

  (105) 0x40ff7f VFMADD213SD	(%R8,%RCX,1),%XMM2,%XMM3

  (105) 0x40ff85 VMOVSD	%XMM3,(%R8,%RCX,1)

  (105) 0x40ff8b ADD	$0x18,%RCX

  (105) 0x40ff8f INC	%RDX

  (105) 0x40ff92 CMP	%EDX,%R11D

  (105) 0x40ff95 JNE	40ff40

(103) 0x40ff97 MOV	0x30(%RSP),%RDX

(103) 0x40ff9c JMP	40fe8e

0x40ffa1 NOPW	%CS:(%RAX,%RAX,1)

(103) 0x40ffb0 MOV	%R11D,%R14D

(103) 0x40ffb3 VPBROADCASTD	%R11D,%YMM25

(103) 0x40ffb9 VPBROADCASTQ	%R12,%ZMM24

(103) 0x40ffbf AND	$-0x8,%R14D

(103) 0x40ffc3 JE	40fd2e

(103) 0x40ffc9 VMOVUPS	%YMM23,0x60(%RSP)

(103) 0x40ffd1 VMOVUPS	%ZMM21,0x80(%RSP)

(103) 0x40ffd9 VMOVAPD	%ZMM22,%ZMM21

(103) 0x40ffdf VMOVAPD	%ZMM20,%ZMM23

(103) 0x40ffe5 VMOVAPD	%ZMM19,%ZMM22

(103) 0x40ffeb VMOVAPD	%ZMM18,%ZMM19

(103) 0x40fff1 VMOVAPD	%ZMM17,%ZMM20

(103) 0x40fff7 VMOVAPD	%ZMM16,%ZMM18

(103) 0x40fffd LEA	(%RCX,%RCX,2),%RDX

(103) 0x410001 LEA	-0x1(%R14),%ECX

(103) 0x410005 ADD	%R10,%R13

(103) 0x410008 XOR	%EBX,%EBX

(103) 0x41000a NOPW	(%RAX,%RAX,1)

  (104) 0x410010 VPMOVSXDQ	(%R13,%RBX,4),%ZMM26

  (104) 0x410018 VXORPD	%XMM27,%XMM27,%XMM27

  (104) 0x41001e KXNORW	%K0,%K0,%K1

  (104) 0x410022 VPSLLQ	$0x4,%ZMM26,%ZMM26

  (104) 0x410029 VGATHERQPD	0x8(%R12,%ZMM26,1),%ZMM27{%K1}

  (104) 0x410031 VDIVPD	%ZMM27,%ZMM1,%ZMM26

  (104) 0x410037 VMOVUPD	(%R9,%RDX,1),%ZMM27

  (104) 0x41003e VMOVUPD	0x40(%R9,%RDX,1),%ZMM28

  (104) 0x410046 VMOVUPD	0x80(%R9,%RDX,1),%ZMM29

  (104) 0x41004e VMOVAPD	%ZMM27,%ZMM30

  (104) 0x410054 VPERMT2PD	%ZMM28,%ZMM4,%ZMM30

  (104) 0x41005a VMOVAPD	%ZMM27,%ZMM31

  (104) 0x410060 VPERMT2PD	%ZMM28,%ZMM6,%ZMM31

  (104) 0x410066 VPERMT2PD	%ZMM27,%ZMM8,%ZMM28

  (104) 0x41006c VMOVUPD	(%R8,%RDX,1),%ZMM17

  (104) 0x410073 VMOVUPD	0x40(%R8,%RDX,1),%ZMM3

  (104) 0x41007b VPERMT2PD	%ZMM29,%ZMM5,%ZMM30

  (104) 0x410081 VMOVUPD	0x80(%R8,%RDX,1),%ZMM2

  (104) 0x410089 VMOVAPD	%ZMM17,%ZMM27

  (104) 0x41008f VPERMT2PD	%ZMM3,%ZMM4,%ZMM27

  (104) 0x410095 VPERMT2PD	%ZMM29,%ZMM7,%ZMM31

  (104) 0x41009b VPERMT2PD	%ZMM2,%ZMM5,%ZMM27

  (104) 0x4100a1 VMOVAPD	%ZMM17,%ZMM16

  (104) 0x4100a7 VPERMT2PD	%ZMM3,%ZMM6,%ZMM16

  (104) 0x4100ad VPERMT2PD	%ZMM29,%ZMM9,%ZMM28

  (104) 0x4100b3 VPERMT2PD	%ZMM2,%ZMM7,%ZMM16

  (104) 0x4100b9 VPERMT2PD	%ZMM17,%ZMM8,%ZMM3

  (104) 0x4100bf VFMADD231PD	%ZMM30,%ZMM26,%ZMM27

  (104) 0x4100c5 VPERMT2PD	%ZMM2,%ZMM9,%ZMM3

  (104) 0x4100cb VFMADD231PD	%ZMM31,%ZMM26,%ZMM16

  (104) 0x4100d1 VFMADD231PD	%ZMM28,%ZMM26,%ZMM3

  (104) 0x4100d7 VMOVAPD	%ZMM16,%ZMM2

  (104) 0x4100dd VPERMT2PD	%ZMM27,%ZMM10,%ZMM2

  (104) 0x4100e3 VMOVAPD	%ZMM27,%ZMM17

  (104) 0x4100e9 VPERMT2PD	%ZMM16,%ZMM11,%ZMM17

  (104) 0x4100ef VPERMT2PD	%ZMM16,%ZMM12,%ZMM27

  (104) 0x4100f5 VPERMT2PD	%ZMM3,%ZMM13,%ZMM27

  (104) 0x4100fb VPERMT2PD	%ZMM3,%ZMM14,%ZMM17

  (104) 0x410101 VPERMT2PD	%ZMM3,%ZMM15,%ZMM2

  (104) 0x410107 VMOVUPD	%ZMM2,0x80(%R8,%RDX,1)

  (104) 0x41010f VMOVUPD	%ZMM17,0x40(%R8,%RDX,1)

  (104) 0x410117 VMOVUPD	%ZMM27,(%R8,%RDX,1)

  (104) 0x41011e ADD	$0x8,%RBX

  (104) 0x410122 ADD	$0xc0,%RDX

  (104) 0x410129 CMP	%ECX,%EBX

  (104) 0x41012b JLE	410010

(103) 0x410131 CMP	%R14D,%R11D

(103) 0x410134 MOV	0x30(%RSP),%RDX

(103) 0x410139 VMOVAPD	%ZMM18,%ZMM16

(103) 0x41013f VMOVAPD	%ZMM20,%ZMM17

(103) 0x410145 VMOVAPD	%ZMM19,%ZMM18

(103) 0x41014b VMOVAPD	%ZMM22,%ZMM19

(103) 0x410151 VMOVAPD	%ZMM23,%ZMM20

(103) 0x410157 VMOVAPD	%ZMM21,%ZMM22

(103) 0x41015d VMOVUPD	0x80(%RSP),%ZMM21

(103) 0x410165 VMOVDQU64	0x60(%RSP),%YMM23

(103) 0x41016d JNE	40fd36

(103) 0x410173 JMP	40fe8e

0x410178 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►95.63+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.14+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:43	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 3.25 cycles (2.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 45% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.75 to 7.08 cycles (1.24x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Vector unaligned load/store instructions

Detected 12 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 816 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	71
nb uops	70
loop length	357
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	13
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.75 cycles
front end	8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.33	3.33	3.33	3.33	3.33	7.50	7.50	7.50	7.50	0.00	0.50	0.50	0.00	0.00	0.00
cycles	3.33	3.33	3.33	3.33	3.33	3.33	7.50	7.50	7.50	7.50	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.75
Dispatch	7.50
Overall L1	8.75

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	43%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	9%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	45%
load	86%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.75 cycles. At this rate:

36% of peak load performance is reached (93.26 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.75 to 7.50 cycles (1.17x speedup).

ASM code

In the binary file, the address of the function is: 40fbe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x100,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVL $0,0x44(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOVL $0,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0x1,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x48(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x4c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x34(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x30(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV $0x42e950,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0x44(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403230 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x2c(%RSP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x28(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 40fc83 <advancePosition.extracted+0xa3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x42e970,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x3c(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 4030f0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
VMOVQ %R15,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0x48(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x18(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x78(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
SUB %RDX,0x50(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	N/A
VPBROADCASTQ %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVUPD 0x1598a(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x159c0(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x159f6(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15a2c(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15a62(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15a98(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15ace(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b04(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b3a(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b70(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15ba6(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15bdc(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 40fea3 <advancePosition.extracted+0x2c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	timestep.c:85-94
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85-94.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 3.25 cycles (2.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:85

Vector unaligned load/store instructions

Detected 12 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:92
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:93
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:94

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 816 bytes. The binary function is storing 60 bytes.

General properties

nb instructions	71
nb uops	70
loop length	357
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	13
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.75 cycles
front end	8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.33	3.33	3.33	3.33	3.33	7.50	7.50	7.50	7.50	0.00	0.50	0.50	0.00	0.00	0.00
cycles	3.33	3.33	3.33	3.33	3.33	3.33	7.50	7.50	7.50	7.50	0.00	0.50	0.50	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.75
Dispatch	7.50
Overall L1	8.75

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	43%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	9%
load	6%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	45%
load	86%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.75 cycles. At this rate:

36% of peak load performance is reached (93.26 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40fbe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x100,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVL $0,0x44(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOVL $0,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0x1,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x48(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x4c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x34(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x30(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV $0x42e950,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,0x44(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403230 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x2c(%RSP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x28(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
CMP %EAX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 40fc83 <advancePosition.extracted+0xa3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x42e970,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x3c(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 4030f0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
VMOVQ %R15,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV 0x48(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x18(%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x78(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
SUB %RDX,0x50(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	N/A
VPBROADCASTQ %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVUPD 0x1598a(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x159c0(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x159f6(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15a2c(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15a62(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15a98(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15ace(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b04(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b3a(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b70(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15ba6(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15bdc(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 40fea3 <advancePosition.extracted+0x2c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advancePosition.extracted–	1.15	0.31
▼Loop 103 - timestep.c:85-94 - exec–	0.44	0.12
○Loop 104 - timestep.c:88-94 - exec	0.71	0.19
○Loop 105 - timestep.c:88-94 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code