OV - exec - Function advanceVelocity.extracted

	Function: advanceVelocity.extracted	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 2.14% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x40f780 PUSH	%RBP

0x40f781 MOV	%RSP,%RBP

0x40f784 PUSH	%R15

0x40f786 PUSH	%R14

0x40f788 PUSH	%R13

0x40f78a PUSH	%R12

0x40f78c PUSH	%RBX

0x40f78d SUB	$0x28,%RSP

0x40f791 MOV	%RCX,%R15

0x40f794 MOV	%RDX,-0x48(%RBP)

0x40f798 MOVL	$0,-0x3c(%RBP)

0x40f79f MOV	(%RDI),%ESI

0x40f7a1 MOVL	$0,-0x30(%RBP)

0x40f7a8 MOV	%R9D,-0x2c(%RBP)

0x40f7ac MOVL	$0x1,-0x38(%RBP)

0x40f7b3 SUB	$0x8,%RSP

0x40f7b7 LEA	-0x38(%RBP),%RAX

0x40f7bb LEA	-0x3c(%RBP),%RCX

0x40f7bf LEA	-0x30(%RBP),%R8

0x40f7c3 LEA	-0x2c(%RBP),%R9

0x40f7c7 MOV	$0x42e8f0,%EDI

0x40f7cc MOV	%ESI,-0x34(%RBP)

0x40f7cf MOV	$0x22,%EDX

0x40f7d4 PUSH	$0x1

0x40f7d6 PUSH	$0x1

0x40f7d8 PUSH	%RAX

0x40f7d9 CALL	403230 <__kmpc_for_static_init_4@plt>

0x40f7de ADD	$0x20,%RSP

0x40f7e2 MOV	-0x30(%RBP),%EAX

0x40f7e5 MOV	-0x2c(%RBP),%ECX

0x40f7e8 CMP	%ECX,%EAX

0x40f7ea JBE	40f80a

0x40f7ec MOV	$0x42e910,%EDI

0x40f7f1 MOV	-0x34(%RBP),%ESI

0x40f7f4 ADD	$0x28,%RSP

0x40f7f8 POP	%RBX

0x40f7f9 POP	%R12

0x40f7fb POP	%R13

0x40f7fd POP	%R14

0x40f7ff POP	%R15

0x40f801 POP	%RBP

0x40f802 VZEROUPPER

0x40f805 JMP	4030f0

0x40f80a VMOVQ	%R15,%XMM0

0x40f80f MOV	-0x48(%RBP),%RDX

0x40f813 MOV	0x18(%RDX),%RDX

0x40f817 MOV	0x78(%RDX),%RDX

0x40f81b SUB	%RAX,%RCX

0x40f81e VPBROADCASTQ	%XMM0,%ZMM1

0x40f824 MOV	%EAX,%ESI

0x40f826 SAL	$0x6,%ESI

0x40f829 XOR	%EDI,%EDI

0x40f82b VMOVDQU	0x14b6d(%RIP),%YMM2

0x40f833 VPBROADCASTQ	0x13e9b(%RIP),%ZMM3

0x40f83d VMOVUPD	0x15af9(%RIP),%ZMM4

0x40f847 VMOVUPD	0x15b2f(%RIP),%ZMM5

0x40f851 VMOVUPD	0x15b65(%RIP),%ZMM6

0x40f85b VMOVUPD	0x15b9b(%RIP),%ZMM7

0x40f865 VMOVUPD	0x15bd1(%RIP),%ZMM8

0x40f86f VMOVUPD	0x15c07(%RIP),%ZMM9

0x40f879 VMOVUPD	0x15c3d(%RIP),%ZMM10

0x40f883 VMOVUPD	0x15c73(%RIP),%ZMM11

0x40f88d VMOVUPD	0x15ca9(%RIP),%ZMM12

0x40f897 VMOVUPD	0x15cdf(%RIP),%ZMM13

0x40f8a1 VMOVUPD	0x15d15(%RIP),%ZMM14

0x40f8ab VMOVUPD	0x15d4b(%RIP),%ZMM15

0x40f8b5 JMP	40f9da

(100) 0x40f8ba XOR	%R15D,%R15D

(100) 0x40f8bd VPBROADCASTD	%R15D,%YMM23

(100) 0x40f8c3 VPSUBD	%YMM23,%YMM22,%YMM22

(100) 0x40f8c9 VPCMPNLEUD	%YMM2,%YMM22,%K1

(100) 0x40f8d0 VPBROADCASTQ	%R11,%ZMM22

(100) 0x40f8d6 VPADDD	%YMM2,%YMM23,%YMM23

(100) 0x40f8dc VPMOVSXDQ	%YMM23,%ZMM23

(100) 0x40f8e2 VPADDQ	%ZMM23,%ZMM22,%ZMM22

(100) 0x40f8e8 VPMULLQ	%ZMM3,%ZMM22,%ZMM22

(100) 0x40f8ee KMOVQ	%K1,%K2

(100) 0x40f8f3 VPXORD	%XMM23,%XMM23,%XMM23

(100) 0x40f8f9 VGATHERQPD	(%R9,%ZMM22,1),%ZMM23{%K2}

(100) 0x40f900 VMOVAPD	%ZMM23,%ZMM21{%K1}

(100) 0x40f906 KMOVQ	%K1,%K2

(100) 0x40f90b VXORPD	%XMM23,%XMM23,%XMM23

(100) 0x40f911 VGATHERQPD	(%R8,%ZMM22,1),%ZMM23{%K2}

(100) 0x40f918 VMOVAPD	%ZMM23,%ZMM20{%K1}

(100) 0x40f91e VMOVAPD	%ZMM1,%ZMM23

(100) 0x40f924 VFMADD213PD	%ZMM20,%ZMM21,%ZMM23

(100) 0x40f92a KMOVQ	%K1,%K2

(100) 0x40f92f VSCATTERQPD	%ZMM23,(%R8,%ZMM22,1){%K2}

(100) 0x40f936 KMOVQ	%K1,%K2

(100) 0x40f93b VXORPD	%XMM23,%XMM23,%XMM23

(100) 0x40f941 VGATHERQPD	0x8(%R9,%ZMM22,1),%ZMM23{%K2}

(100) 0x40f949 VMOVAPD	%ZMM23,%ZMM19{%K1}

(100) 0x40f94f KMOVQ	%K1,%K2

(100) 0x40f954 VXORPD	%XMM23,%XMM23,%XMM23

(100) 0x40f95a VGATHERQPD	0x8(%R8,%ZMM22,1),%ZMM23{%K2}

(100) 0x40f962 VMOVAPD	%ZMM23,%ZMM18{%K1}

(100) 0x40f968 VMOVAPD	%ZMM1,%ZMM23

(100) 0x40f96e VFMADD213PD	%ZMM18,%ZMM19,%ZMM23

(100) 0x40f974 KMOVQ	%K1,%K2

(100) 0x40f979 VSCATTERQPD	%ZMM23,0x8(%R8,%ZMM22,1){%K2}

(100) 0x40f981 KMOVQ	%K1,%K2

(100) 0x40f986 VXORPD	%XMM23,%XMM23,%XMM23

(100) 0x40f98c VGATHERQPD	0x10(%R9,%ZMM22,1),%ZMM23{%K2}

(100) 0x40f994 VMOVAPD	%ZMM23,%ZMM17{%K1}

(100) 0x40f99a KMOVQ	%K1,%K2

(100) 0x40f99f VXORPD	%XMM23,%XMM23,%XMM23

(100) 0x40f9a5 VGATHERQPD	0x10(%R8,%ZMM22,1),%ZMM23{%K2}

(100) 0x40f9ad VMOVAPD	%ZMM23,%ZMM16{%K1}

(100) 0x40f9b3 VMOVAPD	%ZMM1,%ZMM23

(100) 0x40f9b9 VFMADD213PD	%ZMM16,%ZMM17,%ZMM23

(100) 0x40f9bf VSCATTERQPD	%ZMM23,0x10(%R8,%ZMM22,1){%K1}

(100) 0x40f9c7 LEA	0x1(%RDI),%R8

(100) 0x40f9cb ADD	$0x40,%ESI

(100) 0x40f9ce CMP	%RCX,%RDI

(100) 0x40f9d1 MOV	%R8,%RDI

(100) 0x40f9d4 JE	40f7ec

(100) 0x40f9da LEA	(%RDI,%RAX,1),%R8

(100) 0x40f9de MOV	(%RDX,%R8,4),%R10D

(100) 0x40f9e2 TEST	%R10D,%R10D

(100) 0x40f9e5 JLE	40f9c7

(100) 0x40f9e7 MOV	%ESI,%R14D

(100) 0x40f9ea SAL	$0x3,%R14

(100) 0x40f9ee LEA	(%RDI,%RAX,1),%R11D

(100) 0x40f9f2 SAL	$0x6,%R11D

(100) 0x40f9f6 MOV	-0x48(%RBP),%R8

(100) 0x40f9fa MOV	0x20(%R8),%R9

(100) 0x40f9fe MOV	0x20(%R9),%R8

(100) 0x40fa02 MOV	0x28(%R9),%R9

(100) 0x40fa06 LEA	-0x1(%R10),%R15D

(100) 0x40fa0a MOVSXD	%R15D,%R15

(100) 0x40fa0d ADD	%R11,%R15

(100) 0x40fa10 SAL	$0x3,%R15

(100) 0x40fa14 LEA	(%R15,%R15,2),%R15

(100) 0x40fa18 LEA	(%R9,%R15,1),%R13

(100) 0x40fa1c ADD	$0x10,%R13

(100) 0x40fa20 LEA	(,%R11,8),%R12

(100) 0x40fa28 LEA	(%R12,%R12,2),%R12

(100) 0x40fa2c LEA	(%R8,%R12,1),%RBX

(100) 0x40fa30 CMP	%RBX,%R13

(100) 0x40fa33 JB	40fab0

(100) 0x40fa35 ADD	%R9,%R12

(100) 0x40fa38 LEA	(%R8,%R15,1),%RBX

(100) 0x40fa3c ADD	$0x10,%RBX

(100) 0x40fa40 CMP	%R12,%RBX

(100) 0x40fa43 JB	40fab0

(100) 0x40fa45 LEA	(%R14,%R14,2),%R11

(100) 0x40fa49 ADD	$0x10,%R11

(100) 0x40fa4d NOPL	(%RAX)

  (102) 0x40fa50 VMOVSD	-0x10(%R9,%R11,1),%XMM22

  (102) 0x40fa58 VFMADD213SD	-0x10(%R8,%R11,1),%XMM0,%XMM22

  (102) 0x40fa60 VMOVSD	%XMM22,-0x10(%R8,%R11,1)

  (102) 0x40fa68 VMOVSD	-0x8(%R9,%R11,1),%XMM22

  (102) 0x40fa70 VFMADD213SD	-0x8(%R8,%R11,1),%XMM0,%XMM22

  (102) 0x40fa78 VMOVSD	%XMM22,-0x8(%R8,%R11,1)

  (102) 0x40fa80 VMOVSD	(%R9,%R11,1),%XMM22

  (102) 0x40fa87 VFMADD213SD	(%R8,%R11,1),%XMM0,%XMM22

  (102) 0x40fa8e VMOVSD	%XMM22,(%R8,%R11,1)

  (102) 0x40fa95 ADD	$0x18,%R11

  (102) 0x40fa99 DEC	%R10D

  (102) 0x40fa9c JNE	40fa50

(100) 0x40fa9e JMP	40f9c7

0x40faa3 NOPW	%CS:(%RAX,%RAX,1)

(100) 0x40fab0 MOV	%R10D,%R15D

(100) 0x40fab3 VPBROADCASTD	%R10D,%YMM22

(100) 0x40fab9 AND	$-0x8,%R15D

(100) 0x40fabd JE	40f8ba

(100) 0x40fac3 LEA	(%R14,%R14,2),%R12

(100) 0x40fac7 LEA	-0x1(%R15),%R13D

(100) 0x40facb XOR	%R14D,%R14D

(100) 0x40face XCHG	%AX,%AX

  (101) 0x40fad0 VMOVUPD	(%R9,%R12,1),%ZMM23

  (101) 0x40fad7 VMOVUPD	(%R8,%R12,1),%ZMM24

  (101) 0x40fade VMOVUPD	0x40(%R9,%R12,1),%ZMM25

  (101) 0x40fae6 VMOVUPD	0x40(%R8,%R12,1),%ZMM26

  (101) 0x40faee VMOVUPD	0x80(%R9,%R12,1),%ZMM27

  (101) 0x40faf6 VMOVAPD	%ZMM23,%ZMM28

  (101) 0x40fafc VMOVAPD	%ZMM23,%ZMM29

  (101) 0x40fb02 VMOVAPD	%ZMM24,%ZMM30

  (101) 0x40fb08 VPERMT2PD	%ZMM25,%ZMM4,%ZMM28

  (101) 0x40fb0e VPERMT2PD	%ZMM25,%ZMM6,%ZMM29

  (101) 0x40fb14 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

  (101) 0x40fb1a VMOVAPD	%ZMM24,%ZMM23

  (101) 0x40fb20 VPERMT2PD	%ZMM26,%ZMM4,%ZMM30

  (101) 0x40fb26 VPERMT2PD	%ZMM26,%ZMM6,%ZMM23

  (101) 0x40fb2c VPERMT2PD	%ZMM24,%ZMM8,%ZMM26

  (101) 0x40fb32 VMOVUPD	0x80(%R8,%R12,1),%ZMM24

  (101) 0x40fb3a VPERMT2PD	%ZMM27,%ZMM5,%ZMM28

  (101) 0x40fb40 VPERMT2PD	%ZMM27,%ZMM7,%ZMM29

  (101) 0x40fb46 VPERMT2PD	%ZMM24,%ZMM5,%ZMM30

  (101) 0x40fb4c VPERMT2PD	%ZMM24,%ZMM7,%ZMM23

  (101) 0x40fb52 VFMADD231PD	%ZMM28,%ZMM1,%ZMM30

  (101) 0x40fb58 VFMADD231PD	%ZMM29,%ZMM1,%ZMM23

  (101) 0x40fb5e VPERMT2PD	%ZMM27,%ZMM9,%ZMM25

  (101) 0x40fb64 VPERMT2PD	%ZMM24,%ZMM9,%ZMM26

  (101) 0x40fb6a VFMADD231PD	%ZMM25,%ZMM1,%ZMM26

  (101) 0x40fb70 VMOVAPD	%ZMM23,%ZMM24

  (101) 0x40fb76 VMOVAPD	%ZMM30,%ZMM25

  (101) 0x40fb7c VPERMT2PD	%ZMM30,%ZMM10,%ZMM24

  (101) 0x40fb82 VPERMT2PD	%ZMM23,%ZMM11,%ZMM25

  (101) 0x40fb88 VPERMT2PD	%ZMM23,%ZMM12,%ZMM30

  (101) 0x40fb8e VPERMT2PD	%ZMM26,%ZMM13,%ZMM30

  (101) 0x40fb94 VPERMT2PD	%ZMM26,%ZMM14,%ZMM25

  (101) 0x40fb9a VPERMT2PD	%ZMM26,%ZMM15,%ZMM24

  (101) 0x40fba0 VMOVUPD	%ZMM24,0x80(%R8,%R12,1)

  (101) 0x40fba8 VMOVUPD	%ZMM25,0x40(%R8,%R12,1)

  (101) 0x40fbb0 VMOVUPD	%ZMM30,(%R8,%R12,1)

  (101) 0x40fbb7 ADD	$0x8,%R14D

  (101) 0x40fbbb ADD	$0xc0,%R12

  (101) 0x40fbc2 CMP	%R13D,%R14D

  (101) 0x40fbc5 JLE	40fad0

(100) 0x40fbcb CMP	%R15D,%R10D

(100) 0x40fbce JNE	40f8bd

(100) 0x40fbd4 JMP	40f9c7

0x40fbd9 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►95.95+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.13+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:71	exec
○	main	CoMD.c:125	exec
►1.09+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:39	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 3.50 cycles (2.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 43% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.50 to 6.55 cycles (1.30x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Vector unaligned load/store instructions

Detected 12 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:77
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:77
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 848 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	69
nb uops	68
loop length	334
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	14
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	7.00	7.00	7.00	7.00	0.00	1.00	1.00	0.00	0.00	0.00
cycles	3.17	3.17	3.17	3.17	3.17	3.17	7.00	7.00	7.00	7.00	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	7.00
Overall L1	8.50

Vectorization ratios

INT

all	9%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	42%
load	81%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	11%
load	18%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	43%
load	79%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

38% of peak load performance is reached (99.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 7.00 cycles (1.21x speedup).

ASM code

In the binary file, the address of the function is: 40f780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA -0x3c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV $0x42e8f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403230 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 40f80a <advanceVelocity.extracted+0x8a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x42e910,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 4030f0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
VMOVQ %R15,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDQU 0x14b6d(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VPBROADCASTQ 0x13e9b(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	5	0.50	scal (12.5%)
VMOVUPD 0x15af9(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b2f(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b65(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b9b(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15bd1(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15c07(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15c3d(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15c73(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15ca9(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15cdf(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15d15(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15d4b(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
JMP 40f9da <advanceVelocity.extracted+0x25a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.50 to 3.50 cycles (2.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Vector unaligned load/store instructions

Detected 12 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:76
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:77
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:77
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:78

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 848 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	69
nb uops	68
loop length	334
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	14
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	7.00	7.00	7.00	7.00	0.00	1.00	1.00	0.00	0.00	0.00
cycles	3.17	3.17	3.17	3.17	3.17	3.17	7.00	7.00	7.00	7.00	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	7.00
Overall L1	8.50

Vectorization ratios

INT

all	9%
load	25%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	42%
load	81%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	11%
load	18%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	43%
load	79%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

38% of peak load performance is reached (99.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40f780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x38(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA -0x3c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV $0x42e8f0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403230 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %ECX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 40f80a <advanceVelocity.extracted+0x8a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x42e910,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 4030f0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
VMOVQ %R15,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x78(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %XMM0,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDQU 0x14b6d(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VPBROADCASTQ 0x13e9b(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	5	0.50	scal (12.5%)
VMOVUPD 0x15af9(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b2f(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b65(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15b9b(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15bd1(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15c07(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15c3d(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15c73(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15ca9(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15cdf(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15d15(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15d4b(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
JMP 40f9da <advanceVelocity.extracted+0x25a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity.extracted–	2.14	0.59
▼Loop 100 - timestep.c:71-78 - exec–	0.66	0.18
○Loop 101 - timestep.c:74-78 - exec	1.48	0.40
○Loop 102 - timestep.c:74-78 - exec	0.00	0.00

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Vector unaligned load/store instructions

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Matching between your function (in the source code) and the binary function

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Vectorization ratios

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Cycles and memory resources usage

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ASM code