OV - exec - Function mkSeed

	Function: mkSeed	Module: exec	Source: random.c:46-74 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 46 - 74

--------------------------------------------------------------------------------

46:    *seed %= UINT64_C(2305843009213693951);

[...]

66: {

67:    uint32_t s1 = id * UINT32_C(2654435761);

68:    uint32_t s2 = (id+callSite) * UINT32_C(2654435761);

69:

70:    uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2;

71:    for (unsigned jj=0; jj<10; ++jj)

72:       lcg61(&iSeed);

73:

74:    return iSeed;

0x40f270 PUSH	%RBP

0x40f271 MOV	%RSP,%RBP

0x40f274 IMUL	$-0x61c8864f,%EDI,%ECX

0x40f27a ADD	%EDI,%ESI

0x40f27c IMUL	$-0x61c8864f,%ESI,%EAX

0x40f282 SAL	$0x20,%RCX

0x40f286 OR	%RCX,%RAX

0x40f289 MOV	$0x613606df9756715,%RCX

0x40f293 IMUL	%RCX,%RAX

0x40f297 MOV	$0x9,%ESI

0x40f29c MOV	%RAX,%RDX

0x40f29f MULX	%RSI,%RDI,%RDI

0x40f2a4 SUB	%RDI,%RDX

0x40f2a7 SHR	$0x1,%RDX

0x40f2aa ADD	%RDI,%RDX

0x40f2ad SHR	$0x3c,%RDX

0x40f2b1 MOV	%RDX,%RDI

0x40f2b4 SAL	$0x3d,%RDI

0x40f2b8 SUB	%RDI,%RDX

0x40f2bb ADD	%RAX,%RDX

0x40f2be IMUL	%RCX,%RDX

0x40f2c2 MULX	%RSI,%RDI,%RDI

0x40f2c7 MOV	%RDX,%RAX

0x40f2ca SUB	%RDI,%RAX

0x40f2cd SHR	$0x1,%RAX

0x40f2d0 ADD	%RDI,%RAX

0x40f2d3 SHR	$0x3c,%RAX

0x40f2d7 MOV	%RAX,%RDI

0x40f2da SAL	$0x3d,%RDI

0x40f2de SUB	%RDI,%RAX

0x40f2e1 ADD	%RDX,%RAX

0x40f2e4 IMUL	%RCX,%RAX

0x40f2e8 MOV	%RAX,%RDX

0x40f2eb MULX	%RSI,%RDI,%RDI

0x40f2f0 SUB	%RDI,%RDX

0x40f2f3 SHR	$0x1,%RDX

0x40f2f6 ADD	%RDI,%RDX

0x40f2f9 SHR	$0x3c,%RDX

0x40f2fd MOV	%RDX,%RDI

0x40f300 SAL	$0x3d,%RDI

0x40f304 SUB	%RDI,%RDX

0x40f307 ADD	%RAX,%RDX

0x40f30a IMUL	%RCX,%RDX

0x40f30e MULX	%RSI,%RDI,%RDI

0x40f313 MOV	%RDX,%RAX

0x40f316 SUB	%RDI,%RAX

0x40f319 SHR	$0x1,%RAX

0x40f31c ADD	%RDI,%RAX

0x40f31f SHR	$0x3c,%RAX

0x40f323 MOV	%RAX,%RDI

0x40f326 SAL	$0x3d,%RDI

0x40f32a SUB	%RDI,%RAX

0x40f32d ADD	%RDX,%RAX

0x40f330 IMUL	%RCX,%RAX

0x40f334 MOV	%RAX,%RDX

0x40f337 MULX	%RSI,%RDI,%RDI

0x40f33c SUB	%RDI,%RDX

0x40f33f SHR	$0x1,%RDX

0x40f342 ADD	%RDI,%RDX

0x40f345 SHR	$0x3c,%RDX

0x40f349 MOV	%RDX,%RDI

0x40f34c SAL	$0x3d,%RDI

0x40f350 SUB	%RDI,%RDX

0x40f353 ADD	%RAX,%RDX

0x40f356 IMUL	%RCX,%RDX

0x40f35a MULX	%RSI,%RDI,%RDI

0x40f35f MOV	%RDX,%RAX

0x40f362 SUB	%RDI,%RAX

0x40f365 SHR	$0x1,%RAX

0x40f368 ADD	%RDI,%RAX

0x40f36b SHR	$0x3c,%RAX

0x40f36f MOV	%RAX,%RDI

0x40f372 SAL	$0x3d,%RDI

0x40f376 SUB	%RDI,%RAX

0x40f379 ADD	%RDX,%RAX

0x40f37c IMUL	%RCX,%RAX

0x40f380 MOV	%RAX,%RDX

0x40f383 MULX	%RSI,%RDI,%RDI

0x40f388 SUB	%RDI,%RDX

0x40f38b SHR	$0x1,%RDX

0x40f38e ADD	%RDI,%RDX

0x40f391 SHR	$0x3c,%RDX

0x40f395 MOV	%RDX,%RDI

0x40f398 SAL	$0x3d,%RDI

0x40f39c SUB	%RDI,%RDX

0x40f39f ADD	%RAX,%RDX

0x40f3a2 IMUL	%RCX,%RDX

0x40f3a6 MULX	%RSI,%RDI,%RDI

0x40f3ab MOV	%RDX,%RAX

0x40f3ae SUB	%RDI,%RAX

0x40f3b1 SHR	$0x1,%RAX

0x40f3b4 ADD	%RDI,%RAX

0x40f3b7 SHR	$0x3c,%RAX

0x40f3bb MOV	%RAX,%RDI

0x40f3be SAL	$0x3d,%RDI

0x40f3c2 SUB	%RDI,%RAX

0x40f3c5 ADD	%RDX,%RAX

0x40f3c8 IMUL	%RCX,%RAX

0x40f3cc MOV	%RAX,%RDX

0x40f3cf MULX	%RSI,%RDI,%RDI

0x40f3d4 SUB	%RDI,%RDX

0x40f3d7 SHR	$0x1,%RDX

0x40f3da ADD	%RDI,%RDX

0x40f3dd SHR	$0x3c,%RDX

0x40f3e1 MOV	%RDX,%RDI

0x40f3e4 SAL	$0x3d,%RDI

0x40f3e8 SUB	%RDI,%RDX

0x40f3eb ADD	%RAX,%RDX

0x40f3ee IMUL	%RCX,%RDX

0x40f3f2 MULX	%RSI,%RCX,%RCX

0x40f3f7 MOV	%RDX,%RAX

0x40f3fa SUB	%RCX,%RAX

0x40f3fd SHR	$0x1,%RAX

0x40f400 ADD	%RCX,%RAX

0x40f403 SHR	$0x3c,%RAX

0x40f407 MOV	%RAX,%RCX

0x40f40a SAL	$0x3d,%RCX

0x40f40e SUB	%RCX,%RAX

0x40f411 ADD	%RDX,%RAX

0x40f414 POP	%RBP

0x40f415 RET

0x40f416 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►72.34+	randomDisplacements.extracted	initAtoms.c:199	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►25.18+	setTemperature.extracted.30	initAtoms.c:159	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.06+	randomDisplacements.extracted	initAtoms.c:199	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	randomDisplacements	initAtoms.c:205	exec
○	main	CoMD.c:202	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_0

Source file and lines	random.c:46-74
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46,66-74.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 18.00 to 1.45 cycles (12.43x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MULX: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	121
nb uops	131
loop length	422
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.38
Dispatch	18.00
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40f270

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
IMUL $-0x61c8864f,%EDI,%ECX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
ADD %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
IMUL $-0x61c8864f,%ESI,%EAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
SAL $0x20,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
OR %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
MOV $0x613606df9756715,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV $0x9,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RCX,%RCX	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
POP %RBP	1	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_0

Source file and lines	random.c:46-74
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46,66-74.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MULX: 10 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	121
nb uops	131
loop length	422
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.38 cycles
front end	16.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	18.00	18.00	18.00	18.00	18.00	18.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.38
Dispatch	18.00
Overall L1	18.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	11%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40f270

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
IMUL $-0x61c8864f,%EDI,%ECX	1	0.33	0.33	0.33	0	0	0	3	0.33	scal (6.3%)
ADD %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
IMUL $-0x61c8864f,%ESI,%EAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
SAL $0x20,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
OR %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
MOV $0x613606df9756715,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (12.5%)
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV $0x9,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	scal (6.3%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RAX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0.17	N/A
MULX %RSI,%RDI,%RDI	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RDX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RDI	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
IMUL %RCX,%RDX	1	0.33	0.33	0.33	0	0	0	3	0.33	N/A
MULX %RSI,%RCX,%RCX	2	0.67	0.67	0.67	0	0	0	4	0.67	scal (12.5%)
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x1,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
SHR $0x3c,%RAX	1	0	0	0	0.33	0.33	0.33	1	0.33	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0.17	scal (12.5%)
SAL $0x3d,%RCX	1	0	0	0	0.33	0.33	0.33	1	0.33	scal (12.5%)
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	1	0.17	N/A
POP %RBP	1	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	1	0.50	N/A

Name	Coverage (%)	Time (s)
○mkSeed	0.02	0.01

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Vectorization

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Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

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Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code