OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.41% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

[...]

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40b420 PUSH	%RBP

0x40b421 MOV	%RSP,%RBP

0x40b424 PUSH	%R15

0x40b426 PUSH	%R14

0x40b428 PUSH	%R13

0x40b42a PUSH	%R12

0x40b42c PUSH	%RBX

0x40b42d SUB	$0x28,%RSP

0x40b431 MOV	0xc(%RDI),%EAX

0x40b434 CMP	0x14(%RDI),%EAX

0x40b437 JGE	40b456

0x40b439 CLTQ

0x40b43b MOV	0x78(%RDI),%RCX

0x40b43f NOP

(89) 0x40b440 MOVL	$0,(%RCX,%RAX,4)

(89) 0x40b447 INC	%RAX

(89) 0x40b44a MOVSXD	0x14(%RDI),%RDX

(89) 0x40b44e CMP	%RDX,%RAX

(89) 0x40b451 JL	40b440

0x40b453 MOV	0xc(%RDI),%EAX

0x40b456 MOV	%RAX,-0x30(%RBP)

0x40b45a TEST	%EAX,%EAX

0x40b45c JLE	40b840

0x40b462 MOV	0x78(%RDI),%R10

0x40b466 XOR	%EAX,%EAX

0x40b468 JMP	40b480

0x40b46a NOPW	(%RAX,%RAX,1)

(87) 0x40b470 INC	%RAX

(87) 0x40b473 MOVSXD	-0x30(%RBP),%RCX

(87) 0x40b477 CMP	%RCX,%RAX

(87) 0x40b47a JGE	40b840

(87) 0x40b480 CMPL	$0,(%R10,%RAX,4)

(87) 0x40b485 JLE	40b470

(87) 0x40b487 MOVSXD	%EAX,%RCX

(87) 0x40b48a SAL	$0x6,%RCX

(87) 0x40b48e MOV	%RCX,-0x40(%RBP)

(87) 0x40b492 XOR	%EDX,%EDX

(87) 0x40b494 MOV	-0x30(%RBP),%RCX

(87) 0x40b498 MOV	%ECX,%R14D

(87) 0x40b49b MOV	%RAX,-0x48(%RBP)

(87) 0x40b49f JMP	40b4c0

0x40b4a1 NOPW	%CS:(%RAX,%RAX,1)

  (88) 0x40b4b0 MOV	-0x38(%RBP),%RDX

  (88) 0x40b4b4 INC	%EDX

  (88) 0x40b4b6 MOV	0x78(%RDI),%R10

  (88) 0x40b4ba CMP	(%R10,%RAX,4),%EDX

  (88) 0x40b4be JGE	40b470

  (88) 0x40b4c0 MOV	0x18(%RSI),%R11

  (88) 0x40b4c4 MOV	-0x40(%RBP),%RCX

  (88) 0x40b4c8 ADD	%EDX,%ECX

  (88) 0x40b4ca MOVSXD	%ECX,%R9

  (88) 0x40b4cd LEA	(%R9,%R9,2),%RBX

  (88) 0x40b4d1 VMOVSD	(%R11,%RBX,8),%XMM0

  (88) 0x40b4d7 VUCOMISD	0x30(%RDI),%XMM0

  (88) 0x40b4dc MOV	(%RDI),%R13D

  (88) 0x40b4df MOV	%R13D,%R12D

  (88) 0x40b4e2 JAE	40b501

  (88) 0x40b4e4 VSUBSD	0x18(%RDI),%XMM0,%XMM0

  (88) 0x40b4e9 VMULSD	0x60(%RDI),%XMM0,%XMM0

  (88) 0x40b4ee VROUNDSD	$0x9,%XMM0,%XMM0,%XMM0

  (88) 0x40b4f4 VCVTTSD2SI	%XMM0,%R12D

  (88) 0x40b4f8 CMP	%R12D,%R13D

  (88) 0x40b4fb JNE	40b501

  (88) 0x40b4fd LEA	-0x1(%R13),%R12D

  (88) 0x40b501 VMOVSD	0x8(%R11,%RBX,8),%XMM0

  (88) 0x40b508 VSUBSD	0x20(%RDI),%XMM0,%XMM1

  (88) 0x40b50d VMULSD	0x68(%RDI),%XMM1,%XMM1

  (88) 0x40b512 VROUNDSD	$0x9,%XMM1,%XMM1,%XMM1

  (88) 0x40b518 VCVTTSD2SI	%XMM1,%R15D

  (88) 0x40b51c MOV	0x4(%RDI),%ECX

  (88) 0x40b51f MOV	%R14D,%EAX

  (88) 0x40b522 CMP	%R15D,%ECX

  (88) 0x40b525 JNE	40b52b

  (88) 0x40b527 LEA	-0x1(%RCX),%R15D

  (88) 0x40b52b MOV	%RDX,-0x38(%RBP)

  (88) 0x40b52f VMOVSD	0x10(%R11,%RBX,8),%XMM2

  (88) 0x40b536 VMOVSD	0x38(%RDI),%XMM1

  (88) 0x40b53b MOV	0x8(%RDI),%R14D

  (88) 0x40b53f VUCOMISD	%XMM1,%XMM0

  (88) 0x40b543 MOV	%R15D,%EDX

  (88) 0x40b546 CMOVAE	%ECX,%EDX

  (88) 0x40b549 VUCOMISD	0x40(%RDI),%XMM2

  (88) 0x40b54e JAE	40b5a0

  (88) 0x40b550 VSUBSD	0x28(%RDI),%XMM2,%XMM2

  (88) 0x40b555 VMULSD	0x70(%RDI),%XMM2,%XMM2

  (88) 0x40b55a VROUNDSD	$0x9,%XMM2,%XMM2,%XMM2

  (88) 0x40b560 VCVTTSD2SI	%XMM2,%R8D

  (88) 0x40b564 CMP	%R8D,%R14D

  (88) 0x40b567 JNE	40b56d

  (88) 0x40b569 LEA	-0x1(%R14),%R8D

  (88) 0x40b56d CMP	$-0x1,%R8D

  (88) 0x40b571 JE	40b5db

  (88) 0x40b573 VUCOMISD	%XMM1,%XMM0

  (88) 0x40b577 JB	40b613

  (88) 0x40b57d IMUL	%R14D,%ECX

  (88) 0x40b581 ADD	$0x2,%R13D

  (88) 0x40b585 ADD	%R14D,%R8D

  (88) 0x40b588 IMUL	%R13D,%R8D

  (88) 0x40b58c LEA	(%R12,%RCX,2),%ECX

  (88) 0x40b590 ADD	%R8D,%ECX

  (88) 0x40b593 JMP	40b657

0x40b598 NOPL	(%RAX,%RAX,1)

  (88) 0x40b5a0 LEA	(%R14,%R14,1),%R8D

  (88) 0x40b5a4 IMUL	%ECX,%R8D

  (88) 0x40b5a8 ADD	$0x2,%R13D

  (88) 0x40b5ac LEA	(%RDX,%R14,2),%EDX

  (88) 0x40b5b0 ADD	%EDX,%ECX

  (88) 0x40b5b2 ADD	$0x3,%ECX

  (88) 0x40b5b5 IMUL	%R13D,%ECX

  (88) 0x40b5b9 MOV	%EAX,%R14D

  (88) 0x40b5bc ADD	%EAX,%R12D

  (88) 0x40b5bf ADD	%R8D,%R12D

  (88) 0x40b5c2 LEA	(%RCX,%R12,1),%R15D

  (88) 0x40b5c6 INC	%R15D

  (88) 0x40b5c9 TEST	%R15D,%R15D

  (88) 0x40b5cc MOV	-0x48(%RBP),%RAX

  (88) 0x40b5d0 JNS	40b672

0x40b5d6 JMP	40b827

  (88) 0x40b5db LEA	(%R14,%R14,1),%R8D

  (88) 0x40b5df IMUL	%R8D,%ECX

  (88) 0x40b5e3 ADD	$0x2,%R13D

  (88) 0x40b5e7 LEA	(%RDX,%R14,2),%EDX

  (88) 0x40b5eb INC	%EDX

  (88) 0x40b5ed IMUL	%R13D,%EDX

  (88) 0x40b5f1 ADD	%ECX,%R12D

  (88) 0x40b5f4 ADD	%EDX,%R12D

  (88) 0x40b5f7 MOV	-0x30(%RBP),%RCX

  (88) 0x40b5fb LEA	(%RCX,%R12,1),%R15D

  (88) 0x40b5ff INC	%R15D

  (88) 0x40b602 MOV	%ECX,%R14D

  (88) 0x40b605 TEST	%R15D,%R15D

  (88) 0x40b608 MOV	-0x48(%RBP),%RAX

  (88) 0x40b60c JNS	40b672

0x40b60e JMP	40b827

  (88) 0x40b613 CMP	$-0x1,%R15D

  (88) 0x40b617 JE	40b644

  (88) 0x40b619 CMP	%R12D,%R13D

  (88) 0x40b61c JNE	40b7f3

  (88) 0x40b622 ADD	%R14D,%R8D

  (88) 0x40b625 IMUL	%R8D,%ECX

  (88) 0x40b629 MOV	-0x30(%RBP),%RDX

  (88) 0x40b62d ADD	%EDX,%R15D

  (88) 0x40b630 ADD	%ECX,%R15D

  (88) 0x40b633 MOV	%EDX,%R14D

  (88) 0x40b636 TEST	%R15D,%R15D

  (88) 0x40b639 MOV	-0x48(%RBP),%RAX

  (88) 0x40b63d JNS	40b672

0x40b63f JMP	40b827

  (88) 0x40b644 IMUL	%ECX,%R14D

  (88) 0x40b648 ADD	$0x2,%R13D

  (88) 0x40b64c IMUL	%R8D,%R13D

  (88) 0x40b650 LEA	(%R12,%R14,2),%ECX

  (88) 0x40b654 ADD	%R13D,%ECX

  (88) 0x40b657 MOV	-0x30(%RBP),%RDX

  (88) 0x40b65b LEA	(%RDX,%RCX,1),%R15D

  (88) 0x40b65f INC	%R15D

  (88) 0x40b662 MOV	%EDX,%R14D

  (88) 0x40b665 TEST	%R15D,%R15D

  (88) 0x40b668 MOV	-0x48(%RBP),%RAX

  (88) 0x40b66c JS	40b827

  (88) 0x40b672 CMP	0x14(%RDI),%R15D

  (88) 0x40b676 JGE	40b84f

  (88) 0x40b67c MOV	%R15D,%R8D

  (88) 0x40b67f CMP	%R8,%RAX

  (88) 0x40b682 JE	40b4b0

  (88) 0x40b688 LEA	(%R11,%RBX,8),%RCX

  (88) 0x40b68c MOVSXD	(%R10,%R8,4),%R10

  (88) 0x40b690 MOVSXD	%R15D,%RDX

  (88) 0x40b693 SAL	$0x6,%RDX

  (88) 0x40b697 ADD	%R10,%RDX

  (88) 0x40b69a MOV	0x8(%RSI),%R10

  (88) 0x40b69e MOV	(%R10,%R9,4),%EBX

  (88) 0x40b6a2 MOV	%EBX,(%R10,%RDX,4)

  (88) 0x40b6a6 MOV	0x10(%RSI),%R10

  (88) 0x40b6aa MOV	(%R10,%R9,4),%EBX

  (88) 0x40b6ae MOV	%EBX,(%R10,%RDX,4)

  (88) 0x40b6b2 LEA	(,%RDX,8),%R10

  (88) 0x40b6ba LEA	(%R10,%R10,2),%R10

  (88) 0x40b6be MOV	0x10(%RCX),%RBX

  (88) 0x40b6c2 MOV	%RBX,0x10(%R11,%R10,1)

  (88) 0x40b6c7 VMOVUPS	(%RCX),%XMM0

  (88) 0x40b6cb VMOVUPS	%XMM0,(%R11,%R10,1)

  (88) 0x40b6d1 MOV	0x20(%RSI),%R11

  (88) 0x40b6d5 LEA	(,%R9,8),%RCX

  (88) 0x40b6dd LEA	(%RCX,%RCX,2),%RCX

  (88) 0x40b6e1 MOV	0x10(%R11,%RCX,1),%RBX

  (88) 0x40b6e6 MOV	%RBX,0x10(%R11,%R10,1)

  (88) 0x40b6eb VMOVUPS	(%R11,%RCX,1),%XMM0

  (88) 0x40b6f1 VMOVUPS	%XMM0,(%R11,%R10,1)

  (88) 0x40b6f7 MOV	0x28(%RSI),%R11

  (88) 0x40b6fb MOV	0x10(%R11,%RCX,1),%RBX

  (88) 0x40b700 MOV	%RBX,0x10(%R11,%R10,1)

  (88) 0x40b705 VMOVUPD	(%R11,%RCX,1),%XMM0

  (88) 0x40b70b VMOVUPD	%XMM0,(%R11,%R10,1)

  (88) 0x40b711 MOV	0x30(%RSI),%R10

  (88) 0x40b715 MOV	(%R10,%R9,8),%R11

  (88) 0x40b719 MOV	%R11,(%R10,%RDX,8)

  (88) 0x40b71d MOV	0x78(%RDI),%R10

  (88) 0x40b721 MOV	(%R10,%R8,4),%EDX

  (88) 0x40b725 LEA	0x1(%RDX),%R11D

  (88) 0x40b729 MOV	%R11D,(%R10,%R8,4)

  (88) 0x40b72d CMP	$0x3f,%EDX

  (88) 0x40b730 JGE	40b868

  (88) 0x40b736 MOVSXD	(%R10,%RAX,4),%RDX

  (88) 0x40b73a DEC	%RDX

  (88) 0x40b73d MOV	%EDX,(%R10,%RAX,4)

  (88) 0x40b741 TEST	%EDX,%EDX

  (88) 0x40b743 JE	40b7cb

  (88) 0x40b749 ADD	-0x40(%RBP),%RDX

  (88) 0x40b74d MOV	0x8(%RSI),%R8

  (88) 0x40b751 MOV	(%R8,%RDX,4),%R10D

  (88) 0x40b755 MOV	%R10D,(%R8,%R9,4)

  (88) 0x40b759 MOV	0x10(%RSI),%R8

  (88) 0x40b75d MOV	(%R8,%RDX,4),%R10D

  (88) 0x40b761 MOV	%R10D,(%R8,%R9,4)

  (88) 0x40b765 MOV	0x18(%RSI),%R8

  (88) 0x40b769 LEA	(,%RDX,8),%R10

  (88) 0x40b771 LEA	(%R10,%R10,2),%R10

  (88) 0x40b775 MOV	0x10(%R8,%R10,1),%R11

  (88) 0x40b77a MOV	%R11,0x10(%R8,%RCX,1)

  (88) 0x40b77f VMOVUPS	(%R8,%R10,1),%XMM0

  (88) 0x40b785 VMOVUPS	%XMM0,(%R8,%RCX,1)

  (88) 0x40b78b MOV	0x20(%RSI),%R8

  (88) 0x40b78f MOV	0x10(%R8,%R10,1),%R11

  (88) 0x40b794 MOV	%R11,0x10(%R8,%RCX,1)

  (88) 0x40b799 VMOVUPS	(%R8,%R10,1),%XMM0

  (88) 0x40b79f VMOVUPS	%XMM0,(%R8,%RCX,1)

  (88) 0x40b7a5 MOV	0x28(%RSI),%R8

  (88) 0x40b7a9 MOV	0x10(%R8,%R10,1),%R11

  (88) 0x40b7ae MOV	%R11,0x10(%R8,%RCX,1)

  (88) 0x40b7b3 VMOVUPD	(%R8,%R10,1),%XMM0

  (88) 0x40b7b9 VMOVUPD	%XMM0,(%R8,%RCX,1)

  (88) 0x40b7bf MOV	0x30(%RSI),%RCX

  (88) 0x40b7c3 MOV	(%RCX,%RDX,8),%RDX

  (88) 0x40b7c7 MOV	%RDX,(%RCX,%R9,8)

  (88) 0x40b7cb MOV	0xc(%RDI),%ECX

  (88) 0x40b7ce CMP	%R15D,%ECX

  (88) 0x40b7d1 MOV	%RCX,-0x30(%RBP)

  (88) 0x40b7d5 JGE	40b7d9

  (88) 0x40b7d7 DECL	(%RSI)

  (88) 0x40b7d9 MOV	%ECX,%R14D

  (88) 0x40b7dc MOV	-0x38(%RBP),%RDX

  (88) 0x40b7e0 MOV	0x78(%RDI),%R10

  (88) 0x40b7e4 CMP	(%R10,%RAX,4),%EDX

  (88) 0x40b7e8 JL	40b4c0

(87) 0x40b7ee JMP	40b470

  (88) 0x40b7f3 IMUL	%R8D,%ECX

  (88) 0x40b7f7 ADD	%R15D,%ECX

  (88) 0x40b7fa MOV	-0x30(%RBP),%R8

  (88) 0x40b7fe LEA	(%RCX,%R8,1),%EDX

  (88) 0x40b802 IMUL	%R13D,%ECX

  (88) 0x40b806 ADD	%R12D,%ECX

  (88) 0x40b809 CMP	$-0x1,%R12D

  (88) 0x40b80d MOV	%EAX,%R14D

  (88) 0x40b810 CMOVE	%R8D,%R14D

  (88) 0x40b814 CMOVE	%EDX,%ECX

  (88) 0x40b817 MOV	%ECX,%R15D

  (88) 0x40b81a TEST	%R15D,%R15D

  (88) 0x40b81d MOV	-0x48(%RBP),%RAX

  (88) 0x40b821 JNS	40b672

0x40b827 MOV	$0x4245de,%EDI

0x40b82c MOV	$0x424507,%ESI

0x40b831 MOV	$0x4245e8,%ECX

0x40b836 MOV	$0xf6,%EDX

0x40b83b CALL	4030b0 <__assert_fail@plt>

0x40b840 ADD	$0x28,%RSP

0x40b844 POP	%RBX

0x40b845 POP	%R12

0x40b847 POP	%R13

0x40b849 POP	%R14

0x40b84b POP	%R15

0x40b84d POP	%RBP

0x40b84e RET

0x40b84f MOV	$0x424617,%EDI

0x40b854 MOV	$0x424507,%ESI

0x40b859 MOV	$0x4245e8,%ECX

0x40b85e MOV	$0xf7,%EDX

0x40b863 CALL	4030b0 <__assert_fail@plt>

0x40b868 MOV	$0x424631,%EDI

0x40b86d MOV	$0x424507,%ESI

0x40b872 MOV	$0x424650,%ECX

0x40b877 MOV	$0x106,%EDX

0x40b87c CALL	4030b0 <__assert_fail@plt>

0x40b881 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►74.28+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
►24.93+	timestep	timestep.c:148	exec
○	main	CoMD.c:125	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-237,246-247,258-269,288-304,327-334,352-365,371-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.00 to 0.40 cycles (14.84x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:384

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	51
nb uops	48
loop length	204
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	4.33
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 4.33 cycles (1.38x speedup).

ASM code

In the binary file, the address of the function is: 40b420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JGE 40b456 <updateLinkCells+0x36>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CLTQ																				scal (12.5%)
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40b840 <updateLinkCells+0x420>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40b480 <updateLinkCells+0x60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 40b827 <updateLinkCells+0x407>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JMP 40b827 <updateLinkCells+0x407>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JMP 40b827 <updateLinkCells+0x407>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV $0x4245de,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x424507,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x4245e8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x424617,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x424507,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x4245e8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV $0x424631,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x424507,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x424650,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	linkCells.c:211-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:384

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	51
nb uops	48
loop length	204
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	4.33
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	10%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40b420

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP 0x14(%RDI),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (6.3%)
JGE 40b456 <updateLinkCells+0x36>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CLTQ																				scal (12.5%)
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %EAX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 40b840 <updateLinkCells+0x420>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 40b480 <updateLinkCells+0x60>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 40b827 <updateLinkCells+0x407>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JMP 40b827 <updateLinkCells+0x407>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
JMP 40b827 <updateLinkCells+0x407>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV $0x4245de,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x424507,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x4245e8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV $0x424617,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x424507,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x4245e8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV $0x424631,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x424507,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x424650,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4030b0 <__assert_fail@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.41	0.11
▼Loop 87 - linkCells.c:211-373 - exec–	0.01	0.05
○Loop 88 - linkCells.c:211-373 - exec	0.40	3.52
○Loop 89 - linkCells.c:384-385 - exec	0.00	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code