OV - exec - Function kineticEnergy.extracted

	Function: kineticEnergy.extracted	Module: exec	Source: timestep.c:107-116	Coverage (incl. loops): 0.07% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 107 - 116

--------------------------------------------------------------------------------

107:    #pragma omp parallel for reduction(+:kenergy)

108:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++)

109:    {

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

0x410320 PUSH	%RBP

0x410321 MOV	%RSP,%RBP

0x410324 PUSH	%R15

0x410326 PUSH	%R14

0x410328 PUSH	%R13

0x41032a PUSH	%R12

0x41032c PUSH	%RBX

0x41032d SUB	$0x38,%RSP

0x410331 MOV	%R9,-0x50(%RBP)

0x410335 MOV	%RDX,-0x58(%RBP)

0x410339 MOVL	$0,-0x44(%RBP)

0x410340 MOV	%RDI,-0x60(%RBP)

0x410344 MOV	(%RDI),%ESI

0x410346 MOVL	$0,-0x30(%RBP)

0x41034d MOV	%R8D,-0x2c(%RBP)

0x410351 MOVL	$0x1,-0x40(%RBP)

0x410358 SUB	$0x8,%RSP

0x41035c LEA	-0x40(%RBP),%RAX

0x410360 LEA	-0x44(%RBP),%RCX

0x410364 LEA	-0x30(%RBP),%R8

0x410368 LEA	-0x2c(%RBP),%R9

0x41036c MOV	$0x42ea10,%EDI

0x410371 MOV	%ESI,-0x3c(%RBP)

0x410374 MOV	$0x22,%EDX

0x410379 PUSH	$0x1

0x41037b PUSH	$0x1

0x41037d PUSH	%RAX

0x41037e CALL	403230 <__kmpc_for_static_init_4@plt>

0x410383 ADD	$0x20,%RSP

0x410387 MOV	-0x30(%RBP),%EAX

0x41038a MOV	-0x2c(%RBP),%R12D

0x41038e VXORPD	%XMM0,%XMM0,%XMM0

0x410392 CMP	%R12D,%EAX

0x410395 JBE	410416

0x410397 VMOVSD	%XMM0,-0x38(%RBP)

0x41039c MOV	$0x42ea30,%EDI

0x4103a1 MOV	-0x3c(%RBP),%ESI

0x4103a4 VZEROUPPER

0x4103a7 CALL	4030f0 <__kmpc_for_static_fini@plt>

0x4103ac MOV	-0x60(%RBP),%RBX

0x4103b0 MOV	(%RBX),%ESI

0x4103b2 SUB	$0x8,%RSP

0x4103b6 MOV	$0x42fac0,%RAX

0x4103bd LEA	-0x38(%RBP),%R8

0x4103c1 MOV	$0x42ea70,%EDI

0x4103c6 MOV	$0x410310,%R9D

0x4103cc MOV	$0x1,%EDX

0x4103d1 MOV	$0x8,%ECX

0x4103d6 PUSH	%RAX

0x4103d7 CALL	403330 <__kmpc_reduce@plt>

0x4103dc ADD	$0x10,%RSP

0x4103e0 CMP	$0x2,%EAX

0x4103e3 JE	41070f

0x4103e9 CMP	$0x1,%EAX

0x4103ec JNE	410737

0x4103f2 VMOVSD	-0x38(%RBP),%XMM0

0x4103f7 MOV	-0x50(%RBP),%RAX

0x4103fb VADDSD	(%RAX),%XMM0,%XMM0

0x4103ff VMOVSD	%XMM0,(%RAX)

0x410403 MOV	(%RBX),%ESI

0x410405 MOV	$0x42fac0,%RDX

0x41040c MOV	$0x42ea90,%EDI

0x410411 JMP	410732

0x410416 MOV	-0x58(%RBP),%RDX

0x41041a MOV	0x18(%RDX),%RDX

0x41041e MOV	0x78(%RDX),%RBX

0x410422 SUB	%RAX,%R12

0x410425 MOV	%EAX,%ESI

0x410427 SAL	$0x6,%ESI

0x41042a XOR	%EDI,%EDI

0x41042c VMOVDQU	0x13f6c(%RIP),%YMM1

0x410434 VPBROADCASTQ	0x1329a(%RIP),%ZMM2

0x41043e VBROADCASTSD	0x124f0(%RIP),%ZMM3

0x410448 VMOVUPD	0x154ee(%RIP),%ZMM4

0x410452 VMOVUPD	0x15524(%RIP),%ZMM5

0x41045c VMOVUPD	0x1555a(%RIP),%ZMM6

0x410466 VMOVUPD	0x15590(%RIP),%ZMM7

0x410470 VMOVUPD	0x155c6(%RIP),%ZMM8

0x41047a VMOVUPD	0x155fc(%RIP),%ZMM9

0x410484 JMP	4105be

0x410489 NOPL	(%RAX)

(108) 0x410490 VPBROADCASTD	%R11D,%YMM16

(108) 0x410496 VPBROADCASTQ	%R13,%ZMM15

(108) 0x41049c XOR	%R10D,%R10D

(108) 0x41049f LEA	(%RDI,%RAX,1),%EDX

(108) 0x4104a2 SAL	$0x6,%EDX

(108) 0x4104a5 VPBROADCASTD	%R10D,%YMM17

(108) 0x4104ab VPSUBD	%YMM17,%YMM16,%YMM16

(108) 0x4104b1 VPCMPNLEUD	%YMM1,%YMM16,%K1

(108) 0x4104b8 VPBROADCASTQ	%RDX,%ZMM16

(108) 0x4104be VPADDD	%YMM1,%YMM17,%YMM17

(108) 0x4104c4 VPMOVSXDQ	%YMM17,%ZMM17

(108) 0x4104ca VPADDQ	%ZMM17,%ZMM16,%ZMM16

(108) 0x4104d0 VPMULLQ	%ZMM2,%ZMM16,%ZMM16

(108) 0x4104d6 MOVSXD	%R10D,%R10

(108) 0x4104d9 ADD	%RDX,%R10

(108) 0x4104dc VMOVDQU32	(%R9,%R10,4),%YMM17{%K1}{z}

(108) 0x4104e3 VMOVDQA32	%YMM17,%YMM14{%K1}

(108) 0x4104e9 KMOVQ	%K1,%K2

(108) 0x4104ee VPXORD	%XMM17,%XMM17,%XMM17

(108) 0x4104f4 VGATHERQPD	(%R8,%ZMM16,1),%ZMM17{%K2}

(108) 0x4104fb VMOVAPD	%ZMM17,%ZMM13{%K1}

(108) 0x410501 VMULPD	%ZMM13,%ZMM13,%ZMM17

(108) 0x410507 KMOVQ	%K1,%K2

(108) 0x41050c VXORPD	%XMM18,%XMM18,%XMM18

(108) 0x410512 VGATHERQPD	0x8(%R8,%ZMM16,1),%ZMM18{%K2}

(108) 0x41051a VMOVAPD	%ZMM18,%ZMM12{%K1}

(108) 0x410520 VFMADD231PD	%ZMM12,%ZMM12,%ZMM17

(108) 0x410526 KMOVQ	%K1,%K2

(108) 0x41052b VXORPD	%XMM18,%XMM18,%XMM18

(108) 0x410531 VGATHERQPD	0x10(%R8,%ZMM16,1),%ZMM18{%K2}

(108) 0x410539 VMOVAPD	%ZMM18,%ZMM11{%K1}

(108) 0x41053f VFMADD231PD	%ZMM11,%ZMM11,%ZMM17

(108) 0x410545 VMULPD	%ZMM3,%ZMM17,%ZMM16

(108) 0x41054b VPMOVSXDQ	%YMM14,%ZMM17

(108) 0x410551 VPSLLQ	$0x4,%ZMM17,%ZMM17

(108) 0x410558 VPADDQ	%ZMM17,%ZMM15,%ZMM15

(108) 0x41055e KMOVQ	%K1,%K2

(108) 0x410563 VPXORD	%XMM17,%XMM17,%XMM17

(108) 0x410569 VGATHERQPD	0x8(,%ZMM15,1),%ZMM17{%K2}

(108) 0x410574 VDIVPD	%ZMM17,%ZMM16,%ZMM15{%K1}{z}

(108) 0x41057a VMOVAPD	%ZMM17,%ZMM10{%K1}

(108) 0x410580 VEXTRACTF64X4	$0x1,%ZMM15,%YMM16

(108) 0x410587 VADDPD	%ZMM16,%ZMM15,%ZMM15

(108) 0x41058d VEXTRACTF32X4	$0x1,%YMM15,%XMM16

(108) 0x410594 VADDPD	%XMM16,%XMM15,%XMM15

(108) 0x41059a VSHUFPD	$0x1,%XMM15,%XMM15,%XMM16

(108) 0x4105a1 VADDSD	%XMM16,%XMM15,%XMM15

(108) 0x4105a7 VADDSD	%XMM0,%XMM15,%XMM0

(108) 0x4105ab LEA	0x1(%RDI),%RDX

(108) 0x4105af ADD	$0x40,%ESI

(108) 0x4105b2 CMP	%R12,%RDI

(108) 0x4105b5 MOV	%RDX,%RDI

(108) 0x4105b8 JE	410397

(108) 0x4105be LEA	(%RDI,%RAX,1),%RDX

(108) 0x4105c2 MOV	(%RBX,%RDX,4),%R11D

(108) 0x4105c6 TEST	%R11D,%R11D

(108) 0x4105c9 JLE	4105ab

(108) 0x4105cb MOV	-0x58(%RBP),%R8

(108) 0x4105cf MOV	0x20(%R8),%RDX

(108) 0x4105d3 MOV	0x28(%R8),%R13

(108) 0x4105d7 MOV	0x10(%RDX),%R9

(108) 0x4105db MOV	0x20(%RDX),%R8

(108) 0x4105df MOV	%R11D,%R10D

(108) 0x4105e2 AND	$-0x8,%R10D

(108) 0x4105e6 JE	410490

(108) 0x4105ec MOV	%RBX,%RCX

(108) 0x4105ef MOV	%ESI,%R14D

(108) 0x4105f2 LEA	(,%R14,8),%RDX

(108) 0x4105fa LEA	(%RDX,%RDX,2),%R15

(108) 0x4105fe SAL	$0x2,%R14

(108) 0x410602 LEA	-0x1(%R10),%EBX

(108) 0x410606 VPBROADCASTQ	%R13,%ZMM15

(108) 0x41060c ADD	%R8,%R15

(108) 0x41060f ADD	%R9,%R14

(108) 0x410612 VXORPD	%XMM16,%XMM16,%XMM16

(108) 0x410618 XOR	%EDX,%EDX

(108) 0x41061a NOPW	(%RAX,%RAX,1)

  (109) 0x410620 VPMOVSXDQ	(%R14,%RDX,4),%ZMM17

  (109) 0x410627 VMOVUPD	(%R15),%ZMM18

  (109) 0x41062d VMOVUPD	0x40(%R15),%ZMM19

  (109) 0x410634 VMOVUPD	0x80(%R15),%ZMM20

  (109) 0x41063b VMULPD	%ZMM20,%ZMM20,%ZMM20

  (109) 0x410641 VMULPD	%ZMM19,%ZMM19,%ZMM19

  (109) 0x410647 VMULPD	%ZMM18,%ZMM18,%ZMM18

  (109) 0x41064d VMOVAPD	%ZMM18,%ZMM21

  (109) 0x410653 VPERMT2PD	%ZMM19,%ZMM4,%ZMM21

  (109) 0x410659 VPERMT2PD	%ZMM20,%ZMM5,%ZMM21

  (109) 0x41065f VMOVAPD	%ZMM18,%ZMM22

  (109) 0x410665 VPERMT2PD	%ZMM19,%ZMM6,%ZMM22

  (109) 0x41066b VPERMT2PD	%ZMM20,%ZMM7,%ZMM22

  (109) 0x410671 VADDPD	%ZMM21,%ZMM22,%ZMM21

  (109) 0x410677 VPERMT2PD	%ZMM18,%ZMM8,%ZMM19

  (109) 0x41067d VPERMT2PD	%ZMM20,%ZMM9,%ZMM19

  (109) 0x410683 VADDPD	%ZMM19,%ZMM21,%ZMM18

  (109) 0x410689 VPSLLQ	$0x4,%ZMM17,%ZMM17

  (109) 0x410690 VXORPD	%XMM19,%XMM19,%XMM19

  (109) 0x410696 KXNORW	%K0,%K0,%K1

  (109) 0x41069a VMULPD	%ZMM3,%ZMM18,%ZMM18

  (109) 0x4106a0 VGATHERQPD	0x8(%R13,%ZMM17,1),%ZMM19{%K1}

  (109) 0x4106a8 VDIVPD	%ZMM19,%ZMM18,%ZMM17

  (109) 0x4106ae VADDPD	%ZMM16,%ZMM17,%ZMM16

  (109) 0x4106b4 ADD	$0xc0,%R15

  (109) 0x4106bb ADD	$0x8,%RDX

  (109) 0x4106bf CMP	%EBX,%EDX

  (109) 0x4106c1 JLE	410620

(108) 0x4106c7 VEXTRACTF64X4	$0x1,%ZMM16,%YMM17

(108) 0x4106ce VADDPD	%ZMM17,%ZMM16,%ZMM16

(108) 0x4106d4 VEXTRACTF32X4	$0x1,%YMM16,%XMM17

(108) 0x4106db VADDPD	%XMM17,%XMM16,%XMM16

(108) 0x4106e1 VSHUFPD	$0x1,%XMM16,%XMM16,%XMM17

(108) 0x4106e8 VADDSD	%XMM17,%XMM16,%XMM16

(108) 0x4106ee VADDSD	%XMM16,%XMM0,%XMM0

(108) 0x4106f4 CMP	%R10D,%R11D

(108) 0x4106f7 JNE	410701

(108) 0x4106f9 MOV	%RCX,%RBX

(108) 0x4106fc JMP	4105ab

(108) 0x410701 VPBROADCASTD	%R11D,%YMM16

(108) 0x410707 MOV	%RCX,%RBX

(108) 0x41070a JMP	41049f

0x41070f VMOVSD	-0x38(%RBP),%XMM0

0x410714 MOV	(%RBX),%ESI

0x410716 MOV	$0x42ea50,%EDI

0x41071b MOV	-0x50(%RBP),%RDX

0x41071f CALL	403150 <__kmpc_atomic_float8_add@plt>

0x410724 MOV	(%RBX),%ESI

0x410726 MOV	$0x42fac0,%RDX

0x41072d MOV	$0x42eab0,%EDI

0x410732 CALL	403380 <__kmpc_end_reduce@plt>

0x410737 ADD	$0x38,%RSP

0x41073b POP	%RBX

0x41073c POP	%R12

0x41073e POP	%R13

0x410740 POP	%R14

0x410742 POP	%R15

0x410744 POP	%RBP

0x410745 RET

0x410746 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.32+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.52+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	timestep	timestep.c:120	exec
○	main	CoMD.c:125	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 3.50 cycles (3.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.75 to 9.42 cycles (1.35x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_atomic_float8_add@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107

Vector unaligned load/store instructions

Detected 6 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:115
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:115
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:116
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:116

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 536 bytes (67 double precision FP elements). The binary function is storing 60 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	102
loop length	433
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	8
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.75 cycles
front end	12.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	10.25	10.25	10.25	10.25	0.00	1.00	0.50	0.50	1.00	1.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	10.25	10.25	10.25	10.25	0.00	1.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.75
Dispatch	10.25
Overall L1	12.75

Vectorization ratios

INT

all	7%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	53%
load	60%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	23%
load	36%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	9%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	53%
load	65%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	24%
load	39%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.75 cycles. At this rate:

16% of peak load performance is reached (42.04 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.75 to 10.25 cycles (1.24x speedup).

ASM code

In the binary file, the address of the function is: 410320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RDI,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R8D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x44(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x42ea10,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403230 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 410416 <kineticEnergy.extracted+0xf6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD %XMM0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV $0x42ea30,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4030f0 <__kmpc_for_static_fini@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42fac0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x42ea70,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x410310,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403330 <__kmpc_reduce@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 41070f <kineticEnergy.extracted+0x3ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JNE 410737 <kineticEnergy.extracted+0x417>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
VADDSD (%RAX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOV $0x42fac0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42ea90,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 410732 <kineticEnergy.extracted+0x412>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
SUB %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDQU 0x13f6c(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VPBROADCASTQ 0x1329a(%RIP),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VBROADCASTSD 0x124f0(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVUPD 0x154ee(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15524(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x1555a(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15590(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x155c6(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x155fc(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
JMP 4105be <kineticEnergy.extracted+0x29e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOV $0x42ea50,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
CALL 403150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOV $0x42fac0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42eab0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403380 <__kmpc_end_reduce@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_0

Source file and lines	timestep.c:107-116
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107-116.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.75 to 3.50 cycles (3.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_atomic_float8_add@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
__kmpc_end_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
__kmpc_for_static_fini@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
__kmpc_for_static_init_4@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107
__kmpc_reduce@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:107

Vector unaligned load/store instructions

Detected 6 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:114
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:115
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:115
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:116
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:116

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 536 bytes (67 double precision FP elements). The binary function is storing 60 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	99
nb uops	102
loop length	433
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	1
used zmm registers	8
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.75 cycles
front end	12.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	10.25	10.25	10.25	10.25	0.00	1.00	0.50	0.50	1.00	1.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	10.25	10.25	10.25	10.25	0.00	1.00	0.50	0.50	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.75
Dispatch	10.25
Overall L1	12.75

Vectorization ratios

INT

all	7%
load	11%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	53%
load	60%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	23%
load	36%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Vector efficiency ratios

INT

all	9%
load	11%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	53%
load	65%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	24%
load	39%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.75 cycles. At this rate:

16% of peak load performance is reached (42.04 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.71 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 410320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOVL $0,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RDI,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R8D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x44(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x42ea10,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403230 <__kmpc_for_static_init_4@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV -0x2c(%RBP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JBE 410416 <kineticEnergy.extracted+0xf6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD %XMM0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV $0x42ea30,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4030f0 <__kmpc_for_static_fini@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42fac0,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x42ea70,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x410310,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x1,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 403330 <__kmpc_reduce@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
ADD $0x10,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 41070f <kineticEnergy.extracted+0x3ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JNE 410737 <kineticEnergy.extracted+0x417>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
VADDSD (%RAX),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RAX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOV $0x42fac0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42ea90,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 410732 <kineticEnergy.extracted+0x412>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x58(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
SUB %RAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.33	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVDQU 0x13f6c(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (50.0%)
VPBROADCASTQ 0x1329a(%RIP),%ZMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	5	0.50	scal (12.5%)
VBROADCASTSD 0x124f0(%RIP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVUPD 0x154ee(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15524(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x1555a(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x15590(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x155c6(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVUPD 0x155fc(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.50	vect (100.0%)
JMP 4105be <kineticEnergy.extracted+0x29e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD -0x38(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOV $0x42ea50,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
CALL 403150 <__kmpc_atomic_float8_add@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
MOV (%RBX),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOV $0x42fac0,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x42eab0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 403380 <__kmpc_end_reduce@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼kineticEnergy.extracted–	0.07	0.02
▼Loop 108 - timestep.c:107-116 - exec–	0.03	0.01
○Loop 109 - timestep.c:110-116 - exec	0.04	0.01

Report Configuration

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code