OV - exec - Loop 106

	Loop Id: 106	Module: exec	Source: timestep.c:72-78	Coverage: 0.03%

0x2118d0 ADD	$0x40,%ESI

0x2118d3 LEA	0x1(%RAX),%RCX

0x2118d7 CMP	-0x60(%RBP),%RAX

0x2118db MOV	%RCX,%RAX

0x2118de JGE	2117d5

0x2118e4 MOV	(%RDI,%RAX,4),%R9D

0x2118e8 TEST	%R9D,%R9D

0x2118eb JLE	2118d0

0x2118ed MOV	0x20(%RDX),%RCX

0x2118f1 MOVSXD	%ESI,%R15

0x2118f4 XOR	%R12D,%R12D

0x2118f7 MOV	0x20(%RCX),%R10

0x2118fb MOV	0x28(%RCX),%R11

0x2118ff CMP	$0x4,%R9D

0x211903 JB	211ba0

0x211909 LEA	(,%R15,8),%RCX

0x211911 LEA	(%RCX,%RCX,2),%R13

0x211915 LEA	-0x1(%R9),%ECX

0x211919 ADD	%R15,%RCX

0x21191c SAL	$0x3,%RCX

0x211920 LEA	(%R10,%R13,1),%R14

0x211924 ADD	%R11,%R13

0x211927 CMP	-0x58(%RBP),%R14

0x21192b LEA	(%RCX,%RCX,2),%RCX

0x21192f LEA	0x18(%R10,%RCX,1),%R8

0x211934 LEA	0x18(%R11,%RCX,1),%RCX

0x211939 SETB	%DL

0x21193c CMP	%RBX,%R8

0x21193f SETA	%DIL

0x211943 CMP	%RCX,%R14

0x211946 SETB	%CL

0x211949 CMP	%R8,%R13

0x21194c SETB	%R8B

0x211950 TEST	%DIL,%DL

0x211953 JNE	211974

0x211955 MOV	-0x50(%RBP),%RDX

0x211959 MOV	-0x48(%RBP),%RDI

0x21195d AND	%R8B,%CL

0x211960 JNE	211ba0

0x211966 CMP	$0x8,%R9D

0x21196a JAE	211981

0x21196c XOR	%R8D,%R8D

0x21196f JMP	211ab8

0x211974 MOV	-0x50(%RBP),%RDX

0x211978 MOV	-0x48(%RBP),%RDI

0x21197c JMP	211ba0

0x211981 MOV	%R9D,%ECX

0x211984 SHR	$0x3,%ECX

0x211987 MOV	%R9D,%R8D

0x21198a AND	$-0x8,%R8D

0x21198e SAL	$0x6,%RCX

0x211992 LEA	(%RCX,%RCX,2),%R12

0x211996 XOR	%ECX,%ECX

0x211998 NOPL	(%RAX,%RAX,1)

  (108) 0x2119a0 VMOVUPD	(%R13,%RCX,1),%ZMM18

  (108) 0x2119a8 VMOVUPD	0x40(%R13,%RCX,1),%ZMM19

  (108) 0x2119b0 VMOVUPD	0x40(%R14,%RCX,1),%ZMM26

  (108) 0x2119b8 VMOVUPD	0x80(%R13,%RCX,1),%ZMM20

  (108) 0x2119c0 VMOVUPD	0x80(%R14,%RCX,1),%ZMM23

  (108) 0x2119c8 VBROADCASTSD	(%RBX),%ZMM17

  (108) 0x2119ce VMOVAPD	%ZMM18,%ZMM21

  (108) 0x2119d4 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

  (108) 0x2119da VMOVAPD	%ZMM18,%ZMM22

  (108) 0x2119e0 VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

  (108) 0x2119e6 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

  (108) 0x2119ec VMOVUPD	(%R14,%RCX,1),%ZMM18

  (108) 0x2119f3 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

  (108) 0x2119f9 VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

  (108) 0x2119ff VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

  (108) 0x211a05 VMOVAPD	%ZMM18,%ZMM24

  (108) 0x211a0b VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

  (108) 0x211a11 VMOVAPD	%ZMM18,%ZMM25

  (108) 0x211a17 VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

  (108) 0x211a1d VPERMT2PD	%ZMM18,%ZMM9,%ZMM26

  (108) 0x211a23 VPERMT2PD	%ZMM23,%ZMM6,%ZMM24

  (108) 0x211a29 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

  (108) 0x211a2f VPERMT2PD	%ZMM23,%ZMM10,%ZMM26

  (108) 0x211a35 VFMADD231PD	%ZMM21,%ZMM17,%ZMM24

  (108) 0x211a3b VFMADD231PD	%ZMM22,%ZMM17,%ZMM25

  (108) 0x211a41 VFMADD231PD	%ZMM19,%ZMM17,%ZMM26

  (108) 0x211a47 VMOVAPD	%ZMM25,%ZMM17

  (108) 0x211a4d VPERMT2PD	%ZMM24,%ZMM11,%ZMM17

  (108) 0x211a53 VMOVAPD	%ZMM24,%ZMM18

  (108) 0x211a59 VPERMT2PD	%ZMM25,%ZMM13,%ZMM18

  (108) 0x211a5f VPERMT2PD	%ZMM25,%ZMM15,%ZMM24

  (108) 0x211a65 VPERMT2PD	%ZMM26,%ZMM12,%ZMM17

  (108) 0x211a6b VPERMT2PD	%ZMM26,%ZMM14,%ZMM18

  (108) 0x211a71 VPERMT2PD	%ZMM26,%ZMM16,%ZMM24

  (108) 0x211a77 VMOVUPD	%ZMM24,(%R14,%RCX,1)

  (108) 0x211a7e VMOVUPD	%ZMM18,0x40(%R14,%RCX,1)

  (108) 0x211a86 VMOVUPD	%ZMM17,0x80(%R14,%RCX,1)

  (108) 0x211a8e ADD	$0xc0,%RCX

  (108) 0x211a95 CMP	%RCX,%R12

  (108) 0x211a98 JNE	2119a0

0x211a9e CMP	%R9,%R8

0x211aa1 JE	2118d0

0x211aa7 TEST	$0x4,%R9B

0x211aab JNE	211ab8

0x211aad ADD	%R8,%R15

0x211ab0 MOV	%R8D,%R12D

0x211ab3 JMP	211ba0

0x211ab8 MOV	%R9D,%R12D

0x211abb AND	$-0x4,%R12D

0x211abf MOV	%R8,%RCX

0x211ac2 LEA	(%R12,%R15,1),%R14

0x211ac6 ADD	%R8,%R15

0x211ac9 SUB	%R12,%RCX

0x211acc SAL	$0x3,%R15

0x211ad0 LEA	(%R15,%R15,2),%R8

0x211ad4 NOPW	%CS:(%RAX,%RAX,1)

  (109) 0x211ae0 VMOVUPD	(%R11,%R8,1),%ZMM18

  (109) 0x211ae7 VMOVUPD	0x40(%R11,%R8,1),%YMM19

  (109) 0x211aef VMOVUPD	0x40(%R10,%R8,1),%YMM22

  (109) 0x211af7 VBROADCASTSD	(%RBX),%YMM17

  (109) 0x211afd VMOVAPD	%ZMM18,%ZMM20

  (109) 0x211b03 VMOVAPD	%ZMM18,%ZMM21

  (109) 0x211b09 VPERMT2PD	%ZMM19,%ZMM0,%ZMM20

  (109) 0x211b0f VPERMT2PD	%ZMM19,%ZMM1,%ZMM21

  (109) 0x211b15 VPERMT2PD	%ZMM19,%ZMM2,%ZMM18

  (109) 0x211b1b VMOVUPD	(%R10,%R8,1),%ZMM19

  (109) 0x211b22 VMOVAPD	%ZMM19,%ZMM23

  (109) 0x211b28 VPERMT2PD	%ZMM22,%ZMM0,%ZMM23

  (109) 0x211b2e VMOVAPD	%ZMM19,%ZMM24

  (109) 0x211b34 VPERMT2PD	%ZMM22,%ZMM1,%ZMM24

  (109) 0x211b3a VPERMT2PD	%ZMM22,%ZMM2,%ZMM19

  (109) 0x211b40 VFMADD231PD	%YMM20,%YMM17,%YMM23

  (109) 0x211b46 VFMADD231PD	%YMM21,%YMM17,%YMM24

  (109) 0x211b4c VFMADD231PD	%YMM18,%YMM17,%YMM19

  (109) 0x211b52 VINSERTF64X4	$0x1,%YMM24,%ZMM23,%ZMM17

  (109) 0x211b59 VMOVAPD	%ZMM17,%ZMM18

  (109) 0x211b5f VPERMT2PD	%ZMM19,%ZMM3,%ZMM18

  (109) 0x211b65 VPERMT2PD	%ZMM19,%ZMM4,%ZMM17

  (109) 0x211b6b VMOVUPD	%ZMM17,(%R10,%R8,1)

  (109) 0x211b72 VMOVUPD	%YMM18,0x40(%R10,%R8,1)

  (109) 0x211b7a ADD	$0x60,%R8

  (109) 0x211b7e ADD	$0x4,%RCX

  (109) 0x211b82 JNE	211ae0

0x211b88 MOV	%R14,%R15

0x211b8b CMP	%R9,%R12

0x211b8e JE	2118d0

0x211b94 NOPW	%CS:(%RAX,%RAX,1)

0x211ba0 LEA	(%R15,%R15,2),%RCX

0x211ba4 SUB	%R12D,%R9D

0x211ba7 LEA	0x10(,%RCX,8),%RCX

0x211baf NOP

  (107) 0x211bb0 VMOVSD	(%RBX),%XMM17

  (107) 0x211bb6 VMOVSD	-0x10(%R11,%RCX,1),%XMM18

  (107) 0x211bbe VFMADD213SD	-0x10(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x211bc6 VMOVSD	%XMM18,-0x10(%R10,%RCX,1)

  (107) 0x211bce VMOVSD	(%RBX),%XMM17

  (107) 0x211bd4 VMOVSD	-0x8(%R11,%RCX,1),%XMM18

  (107) 0x211bdc VFMADD213SD	-0x8(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x211be4 VMOVSD	%XMM18,-0x8(%R10,%RCX,1)

  (107) 0x211bec VMOVSD	(%RBX),%XMM17

  (107) 0x211bf2 VMOVSD	(%R11,%RCX,1),%XMM18

  (107) 0x211bf9 VFMADD213SD	(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x211c00 VMOVSD	%XMM18,(%R10,%RCX,1)

  (107) 0x211c07 ADD	$0x18,%RCX

  (107) 0x211c0b DEC	%R9D

  (107) 0x211c0e JNE	211bb0

0x211c10 JMP	2118d0

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 72 - 78

--------------------------------------------------------------------------------

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.44
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	micro-operation queue,
Function	advanceVelocity.omp_outlined
Source	timestep.c:72-74,timestep.c:78-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.63
CQA cycles if no scalar integer	9.63
CQA cycles if FP arith vectorized	9.63
CQA cycles if fully vectorized	0.67
Front-end cycles	9.63
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	77.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.90
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.62

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	14.44
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	micro-operation queue,
Function	advanceVelocity.omp_outlined
Source	timestep.c:72-74,timestep.c:78-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.63
CQA cycles if no scalar integer	9.63
CQA cycles if FP arith vectorized	9.63
CQA cycles if fully vectorized	0.67
Front-end cycles	9.63
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	77.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.90
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.62

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advanceVelocity.omp_outlined
Source file and lines	timestep.c:72-78
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72-78.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72-74,78.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.63 to 0.67 cycles (14.44x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 76 bytes.

General properties

nb instructions	79
nb uops	77
loop length	319
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.50	9.50	9.50	9.50	9.50	9.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	9.50	9.50	9.50	9.50	9.50	9.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.63
Dispatch	9.50
Overall L1	9.63

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.63 cycles. At this rate:

3% of peak load performance is reached (7.90 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 2118e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
ADD $0x40,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP -0x60(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JGE 2117d5 <advanceVelocity.omp_outlined+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI,%RAX,4),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2118d0 <advanceVelocity.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %ESI,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RCX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RCX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x4,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 211ba0 <advanceVelocity.omp_outlined+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA (,%R15,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RCX,2),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%R9),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%R10,%R13,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R11,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP -0x58(%RBP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
LEA (%RCX,%RCX,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x18(%R10,%RCX,1),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
LEA 0x18(%R11,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
SETB %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
SETA %DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RCX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
SETB %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
TEST %DIL,%DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 211974 <advanceVelocity.omp_outlined+0x224>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
AND %R8B,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 211ba0 <advanceVelocity.omp_outlined+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 211981 <advanceVelocity.omp_outlined+0x231>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 211ab8 <advanceVelocity.omp_outlined+0x368>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 211ba0 <advanceVelocity.omp_outlined+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %R9D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%ECX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %R9D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x8,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RCX,%RCX,2),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JE 2118d0 <advanceVelocity.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
TEST $0x4,%R9B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 211ab8 <advanceVelocity.omp_outlined+0x368>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
ADD %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 211ba0 <advanceVelocity.omp_outlined+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %R9D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%R15,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x3,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%R15,%R15,2),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R9,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JE 2118d0 <advanceVelocity.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA (%R15,%R15,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R12D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x10(,%RCX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 2118d0 <advanceVelocity.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	advanceVelocity.omp_outlined
Source file and lines	timestep.c:72-78
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=10
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:74

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 76 bytes.

General properties

nb instructions	79
nb uops	77
loop length	319
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.50	9.50	9.50	9.50	9.50	9.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	9.50	9.50	9.50	9.50	9.50	9.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.63
Dispatch	9.50
Overall L1	9.63

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.63 cycles. At this rate:

3% of peak load performance is reached (7.90 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 2118e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
ADD $0x40,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP -0x60(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JGE 2117d5 <advanceVelocity.omp_outlined+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI,%RAX,4),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %R9D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2118d0 <advanceVelocity.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x20(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %ESI,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RCX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RCX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x4,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 211ba0 <advanceVelocity.omp_outlined+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA (,%R15,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RCX,2),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%R9),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%R10,%R13,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R11,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP -0x58(%RBP),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
LEA (%RCX,%RCX,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x18(%R10,%RCX,1),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
LEA 0x18(%R11,%RCX,1),%RCX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
SETB %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
SETA %DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RCX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
SETB %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
SETB %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
TEST %DIL,%DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 211974 <advanceVelocity.omp_outlined+0x224>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
AND %R8B,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 211ba0 <advanceVelocity.omp_outlined+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 211981 <advanceVelocity.omp_outlined+0x231>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 211ab8 <advanceVelocity.omp_outlined+0x368>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 211ba0 <advanceVelocity.omp_outlined+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %R9D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%ECX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV %R9D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
AND $-0x8,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SAL $0x6,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%RCX,%RCX,2),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JE 2118d0 <advanceVelocity.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
TEST $0x4,%R9B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 211ab8 <advanceVelocity.omp_outlined+0x368>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
ADD %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 211ba0 <advanceVelocity.omp_outlined+0x450>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %R9D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R12,%R15,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R12,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SAL $0x3,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%R15,%R15,2),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R9,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JE 2118d0 <advanceVelocity.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
LEA (%R15,%R15,2),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R12D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x10(,%RCX,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 2118d0 <advanceVelocity.omp_outlined+0x180>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code