OV - exec - Function advanceVelocity.omp

	Function: advanceVelocity.omp_outlined	Module: exec	Source: timestep.c:71-78	Coverage (incl. loops): 1.90% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 71 - 78

--------------------------------------------------------------------------------

71:    #pragma omp parallel for

72:    for (int iBox=0; iBox<nBoxes; iBox++)

73:    {

74:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

75:       {

76:          s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0];

77:          s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1];

78:          s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2];

0x211750 PUSH	%RBP

0x211751 MOV	%RSP,%RBP

0x211754 PUSH	%R15

0x211756 PUSH	%R14

0x211758 PUSH	%R13

0x21175a PUSH	%R12

0x21175c PUSH	%RBX

0x21175d SUB	$0x38,%RSP

0x211761 MOV	(%RDX),%R14D

0x211764 TEST	%R14D,%R14D

0x211767 JLE	2117e7

0x211769 MOV	(%RDI),%ESI

0x21176b DEC	%R14D

0x21176e MOV	%R8,%RBX

0x211771 MOV	%RCX,%R15

0x211774 MOVL	$0,-0x30(%RBP)

0x21177b MOVL	$0x1,-0x3c(%RBP)

0x211782 MOVL	$0,-0x38(%RBP)

0x211789 MOV	%R14D,-0x2c(%RBP)

0x21178d SUB	$0x8,%RSP

0x211791 LEA	-0x3c(%RBP),%RAX

0x211795 LEA	0x22dc(%RIP),%RDI

0x21179c LEA	-0x38(%RBP),%RCX

0x2117a0 LEA	-0x30(%RBP),%R8

0x2117a4 LEA	-0x2c(%RBP),%R9

0x2117a8 MOV	%ESI,-0x34(%RBP)

0x2117ab MOV	$0x22,%EDX

0x2117b0 PUSH	$0x1

0x2117b2 PUSH	$0x1

0x2117b4 PUSH	%RAX

0x2117b5 CALL	212580 <@plt_start@+0x180>

0x2117ba ADD	$0x20,%RSP

0x2117be MOV	-0x2c(%RBP),%EAX

0x2117c1 CMP	%R14D,%EAX

0x2117c4 CMOVL	%EAX,%R14D

0x2117c8 MOVSXD	-0x30(%RBP),%RAX

0x2117cc MOV	%R14D,-0x2c(%RBP)

0x2117d0 CMP	%R14D,%EAX

0x2117d3 JLE	2117f6

0x2117d5 MOV	-0x34(%RBP),%ESI

0x2117d8 LEA	0x22b1(%RIP),%RDI

0x2117df VZEROUPPER

0x2117e2 CALL	212590 <@plt_start@+0x190>

0x2117e7 ADD	$0x38,%RSP

0x2117eb POP	%RBX

0x2117ec POP	%R12

0x2117ee POP	%R13

0x2117f0 POP	%R14

0x2117f2 POP	%R15

0x2117f4 POP	%RBP

0x2117f5 RET

0x2117f6 MOV	(%R15),%RDX

0x2117f9 VMOVAPD	-0xcee1(%RIP),%YMM0

0x211801 VMOVAPD	-0xcea9(%RIP),%YMM1

0x211809 VMOVAPD	-0xcf11(%RIP),%YMM2

0x211811 VMOVAPD	-0xcf39(%RIP),%YMM3

0x211819 VMOVAPD	-0xc4e3(%RIP),%ZMM4

0x211823 VMOVAPD	-0xc7ed(%RIP),%ZMM5

0x21182d VMOVAPD	-0xc7b7(%RIP),%ZMM6

0x211837 VMOVAPD	-0xc781(%RIP),%ZMM7

0x211841 VMOVAPD	-0xc74b(%RIP),%ZMM8

0x21184b VMOVAPD	-0xc715(%RIP),%ZMM9

0x211855 VMOVAPD	-0xc6df(%RIP),%ZMM10

0x21185f VMOVAPD	-0xc6a9(%RIP),%ZMM11

0x211869 VMOVAPD	-0xc673(%RIP),%ZMM12

0x211873 VMOVAPD	-0xc63d(%RIP),%ZMM13

0x21187d VMOVAPD	-0xc607(%RIP),%ZMM14

0x211887 VMOVAPD	-0xc5d1(%RIP),%ZMM15

0x211891 VMOVAPD	-0xc59b(%RIP),%ZMM16

0x21189b MOV	%EAX,%ESI

0x21189d SAL	$0x6,%ESI

0x2118a0 MOV	0x18(%RDX),%RCX

0x2118a4 MOV	%RDX,-0x50(%RBP)

0x2118a8 MOV	0x78(%RCX),%RDI

0x2118ac MOVSXD	%R14D,%RCX

0x2118af MOV	%RCX,-0x60(%RBP)

0x2118b3 LEA	0x8(%RBX),%RCX

0x2118b7 MOV	%RCX,-0x58(%RBP)

0x2118bb MOV	%RDI,-0x48(%RBP)

0x2118bf JMP	2118e4

0x2118c1 NOPW	%CS:(%RAX,%RAX,1)

(106) 0x2118d0 ADD	$0x40,%ESI

(106) 0x2118d3 LEA	0x1(%RAX),%RCX

(106) 0x2118d7 CMP	-0x60(%RBP),%RAX

(106) 0x2118db MOV	%RCX,%RAX

(106) 0x2118de JGE	2117d5

(106) 0x2118e4 MOV	(%RDI,%RAX,4),%R9D

(106) 0x2118e8 TEST	%R9D,%R9D

(106) 0x2118eb JLE	2118d0

(106) 0x2118ed MOV	0x20(%RDX),%RCX

(106) 0x2118f1 MOVSXD	%ESI,%R15

(106) 0x2118f4 XOR	%R12D,%R12D

(106) 0x2118f7 MOV	0x20(%RCX),%R10

(106) 0x2118fb MOV	0x28(%RCX),%R11

(106) 0x2118ff CMP	$0x4,%R9D

(106) 0x211903 JB	211ba0

(106) 0x211909 LEA	(,%R15,8),%RCX

(106) 0x211911 LEA	(%RCX,%RCX,2),%R13

(106) 0x211915 LEA	-0x1(%R9),%ECX

(106) 0x211919 ADD	%R15,%RCX

(106) 0x21191c SAL	$0x3,%RCX

(106) 0x211920 LEA	(%R10,%R13,1),%R14

(106) 0x211924 ADD	%R11,%R13

(106) 0x211927 CMP	-0x58(%RBP),%R14

(106) 0x21192b LEA	(%RCX,%RCX,2),%RCX

(106) 0x21192f LEA	0x18(%R10,%RCX,1),%R8

(106) 0x211934 LEA	0x18(%R11,%RCX,1),%RCX

(106) 0x211939 SETB	%DL

(106) 0x21193c CMP	%RBX,%R8

(106) 0x21193f SETA	%DIL

(106) 0x211943 CMP	%RCX,%R14

(106) 0x211946 SETB	%CL

(106) 0x211949 CMP	%R8,%R13

(106) 0x21194c SETB	%R8B

(106) 0x211950 TEST	%DIL,%DL

(106) 0x211953 JNE	211974

(106) 0x211955 MOV	-0x50(%RBP),%RDX

(106) 0x211959 MOV	-0x48(%RBP),%RDI

(106) 0x21195d AND	%R8B,%CL

(106) 0x211960 JNE	211ba0

(106) 0x211966 CMP	$0x8,%R9D

(106) 0x21196a JAE	211981

(106) 0x21196c XOR	%R8D,%R8D

(106) 0x21196f JMP	211ab8

(106) 0x211974 MOV	-0x50(%RBP),%RDX

(106) 0x211978 MOV	-0x48(%RBP),%RDI

(106) 0x21197c JMP	211ba0

(106) 0x211981 MOV	%R9D,%ECX

(106) 0x211984 SHR	$0x3,%ECX

(106) 0x211987 MOV	%R9D,%R8D

(106) 0x21198a AND	$-0x8,%R8D

(106) 0x21198e SAL	$0x6,%RCX

(106) 0x211992 LEA	(%RCX,%RCX,2),%R12

(106) 0x211996 XOR	%ECX,%ECX

(106) 0x211998 NOPL	(%RAX,%RAX,1)

  (108) 0x2119a0 VMOVUPD	(%R13,%RCX,1),%ZMM18

  (108) 0x2119a8 VMOVUPD	0x40(%R13,%RCX,1),%ZMM19

  (108) 0x2119b0 VMOVUPD	0x40(%R14,%RCX,1),%ZMM26

  (108) 0x2119b8 VMOVUPD	0x80(%R13,%RCX,1),%ZMM20

  (108) 0x2119c0 VMOVUPD	0x80(%R14,%RCX,1),%ZMM23

  (108) 0x2119c8 VBROADCASTSD	(%RBX),%ZMM17

  (108) 0x2119ce VMOVAPD	%ZMM18,%ZMM21

  (108) 0x2119d4 VPERMT2PD	%ZMM19,%ZMM5,%ZMM21

  (108) 0x2119da VMOVAPD	%ZMM18,%ZMM22

  (108) 0x2119e0 VPERMT2PD	%ZMM19,%ZMM7,%ZMM22

  (108) 0x2119e6 VPERMT2PD	%ZMM18,%ZMM9,%ZMM19

  (108) 0x2119ec VMOVUPD	(%R14,%RCX,1),%ZMM18

  (108) 0x2119f3 VPERMT2PD	%ZMM20,%ZMM6,%ZMM21

  (108) 0x2119f9 VPERMT2PD	%ZMM20,%ZMM8,%ZMM22

  (108) 0x2119ff VPERMT2PD	%ZMM20,%ZMM10,%ZMM19

  (108) 0x211a05 VMOVAPD	%ZMM18,%ZMM24

  (108) 0x211a0b VPERMT2PD	%ZMM26,%ZMM5,%ZMM24

  (108) 0x211a11 VMOVAPD	%ZMM18,%ZMM25

  (108) 0x211a17 VPERMT2PD	%ZMM26,%ZMM7,%ZMM25

  (108) 0x211a1d VPERMT2PD	%ZMM18,%ZMM9,%ZMM26

  (108) 0x211a23 VPERMT2PD	%ZMM23,%ZMM6,%ZMM24

  (108) 0x211a29 VPERMT2PD	%ZMM23,%ZMM8,%ZMM25

  (108) 0x211a2f VPERMT2PD	%ZMM23,%ZMM10,%ZMM26

  (108) 0x211a35 VFMADD231PD	%ZMM21,%ZMM17,%ZMM24

  (108) 0x211a3b VFMADD231PD	%ZMM22,%ZMM17,%ZMM25

  (108) 0x211a41 VFMADD231PD	%ZMM19,%ZMM17,%ZMM26

  (108) 0x211a47 VMOVAPD	%ZMM25,%ZMM17

  (108) 0x211a4d VPERMT2PD	%ZMM24,%ZMM11,%ZMM17

  (108) 0x211a53 VMOVAPD	%ZMM24,%ZMM18

  (108) 0x211a59 VPERMT2PD	%ZMM25,%ZMM13,%ZMM18

  (108) 0x211a5f VPERMT2PD	%ZMM25,%ZMM15,%ZMM24

  (108) 0x211a65 VPERMT2PD	%ZMM26,%ZMM12,%ZMM17

  (108) 0x211a6b VPERMT2PD	%ZMM26,%ZMM14,%ZMM18

  (108) 0x211a71 VPERMT2PD	%ZMM26,%ZMM16,%ZMM24

  (108) 0x211a77 VMOVUPD	%ZMM24,(%R14,%RCX,1)

  (108) 0x211a7e VMOVUPD	%ZMM18,0x40(%R14,%RCX,1)

  (108) 0x211a86 VMOVUPD	%ZMM17,0x80(%R14,%RCX,1)

  (108) 0x211a8e ADD	$0xc0,%RCX

  (108) 0x211a95 CMP	%RCX,%R12

  (108) 0x211a98 JNE	2119a0

(106) 0x211a9e CMP	%R9,%R8

(106) 0x211aa1 JE	2118d0

(106) 0x211aa7 TEST	$0x4,%R9B

(106) 0x211aab JNE	211ab8

(106) 0x211aad ADD	%R8,%R15

(106) 0x211ab0 MOV	%R8D,%R12D

(106) 0x211ab3 JMP	211ba0

(106) 0x211ab8 MOV	%R9D,%R12D

(106) 0x211abb AND	$-0x4,%R12D

(106) 0x211abf MOV	%R8,%RCX

(106) 0x211ac2 LEA	(%R12,%R15,1),%R14

(106) 0x211ac6 ADD	%R8,%R15

(106) 0x211ac9 SUB	%R12,%RCX

(106) 0x211acc SAL	$0x3,%R15

(106) 0x211ad0 LEA	(%R15,%R15,2),%R8

(106) 0x211ad4 NOPW	%CS:(%RAX,%RAX,1)

  (109) 0x211ae0 VMOVUPD	(%R11,%R8,1),%ZMM18

  (109) 0x211ae7 VMOVUPD	0x40(%R11,%R8,1),%YMM19

  (109) 0x211aef VMOVUPD	0x40(%R10,%R8,1),%YMM22

  (109) 0x211af7 VBROADCASTSD	(%RBX),%YMM17

  (109) 0x211afd VMOVAPD	%ZMM18,%ZMM20

  (109) 0x211b03 VMOVAPD	%ZMM18,%ZMM21

  (109) 0x211b09 VPERMT2PD	%ZMM19,%ZMM0,%ZMM20

  (109) 0x211b0f VPERMT2PD	%ZMM19,%ZMM1,%ZMM21

  (109) 0x211b15 VPERMT2PD	%ZMM19,%ZMM2,%ZMM18

  (109) 0x211b1b VMOVUPD	(%R10,%R8,1),%ZMM19

  (109) 0x211b22 VMOVAPD	%ZMM19,%ZMM23

  (109) 0x211b28 VPERMT2PD	%ZMM22,%ZMM0,%ZMM23

  (109) 0x211b2e VMOVAPD	%ZMM19,%ZMM24

  (109) 0x211b34 VPERMT2PD	%ZMM22,%ZMM1,%ZMM24

  (109) 0x211b3a VPERMT2PD	%ZMM22,%ZMM2,%ZMM19

  (109) 0x211b40 VFMADD231PD	%YMM20,%YMM17,%YMM23

  (109) 0x211b46 VFMADD231PD	%YMM21,%YMM17,%YMM24

  (109) 0x211b4c VFMADD231PD	%YMM18,%YMM17,%YMM19

  (109) 0x211b52 VINSERTF64X4	$0x1,%YMM24,%ZMM23,%ZMM17

  (109) 0x211b59 VMOVAPD	%ZMM17,%ZMM18

  (109) 0x211b5f VPERMT2PD	%ZMM19,%ZMM3,%ZMM18

  (109) 0x211b65 VPERMT2PD	%ZMM19,%ZMM4,%ZMM17

  (109) 0x211b6b VMOVUPD	%ZMM17,(%R10,%R8,1)

  (109) 0x211b72 VMOVUPD	%YMM18,0x40(%R10,%R8,1)

  (109) 0x211b7a ADD	$0x60,%R8

  (109) 0x211b7e ADD	$0x4,%RCX

  (109) 0x211b82 JNE	211ae0

(106) 0x211b88 MOV	%R14,%R15

(106) 0x211b8b CMP	%R9,%R12

(106) 0x211b8e JE	2118d0

(106) 0x211b94 NOPW	%CS:(%RAX,%RAX,1)

(106) 0x211ba0 LEA	(%R15,%R15,2),%RCX

(106) 0x211ba4 SUB	%R12D,%R9D

(106) 0x211ba7 LEA	0x10(,%RCX,8),%RCX

(106) 0x211baf NOP

  (107) 0x211bb0 VMOVSD	(%RBX),%XMM17

  (107) 0x211bb6 VMOVSD	-0x10(%R11,%RCX,1),%XMM18

  (107) 0x211bbe VFMADD213SD	-0x10(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x211bc6 VMOVSD	%XMM18,-0x10(%R10,%RCX,1)

  (107) 0x211bce VMOVSD	(%RBX),%XMM17

  (107) 0x211bd4 VMOVSD	-0x8(%R11,%RCX,1),%XMM18

  (107) 0x211bdc VFMADD213SD	-0x8(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x211be4 VMOVSD	%XMM18,-0x8(%R10,%RCX,1)

  (107) 0x211bec VMOVSD	(%RBX),%XMM17

  (107) 0x211bf2 VMOVSD	(%R11,%RCX,1),%XMM18

  (107) 0x211bf9 VFMADD213SD	(%R10,%RCX,1),%XMM17,%XMM18

  (107) 0x211c00 VMOVSD	%XMM18,(%R10,%RCX,1)

  (107) 0x211c07 ADD	$0x18,%RCX

  (107) 0x211c0b DEC	%R9D

  (107) 0x211c0e JNE	211bb0

(106) 0x211c10 JMP	2118d0

0x211c15 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.38 to 4.50 cycles (2.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 44% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.38 to 7.92 cycles (1.31x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1004 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	82
nb uops	83
loop length	395
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Dispatch	9.25
Overall L1	10.38

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	8%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	75%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.38 cycles. At this rate:

37% of peak load performance is reached (96.77 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.38 to 9.25 cycles (1.12x speedup).

ASM code

In the binary file, the address of the function is: 211750

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2117e7 <advanceVelocity.omp_outlined+0x97>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x3c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x22dc(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212580 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2117f6 <advanceVelocity.omp_outlined+0xa6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x22b1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 212590 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0xcee1(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcea9(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcf11(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcf39(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xc4e3(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc7ed(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc7b7(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc781(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc74b(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc715(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc6df(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc6a9(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc673(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc63d(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc607(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc5d1(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc59b(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV 0x18(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x78(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %R14D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x8(%RBX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2118e4 <advanceVelocity.omp_outlined+0x194>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	timestep.c:71-78
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71-78.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.38 to 4.50 cycles (2.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:72

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1004 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	82
nb uops	83
loop length	395
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	4
used zmm registers	13
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.38 cycles
front end	10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.50	4.50	4.50	4.50	4.50	4.50	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.38
Dispatch	9.25
Overall L1	10.38

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	47%
load	85%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	8%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	88%
load	88%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	75%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.38 cycles. At this rate:

37% of peak load performance is reached (96.77 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 211750

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R14D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2117e7 <advanceVelocity.omp_outlined+0x97>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0x1,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x3c(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x22dc(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 212580 <@plt_start@+0x180>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMOVL %EAX,%R14D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOVSXD -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %R14D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 2117f6 <advanceVelocity.omp_outlined+0xa6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x22b1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 212590 <@plt_start@+0x190>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVAPD -0xcee1(%RIP),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcea9(%RIP),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcf11(%RIP),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xcf39(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (50.0%)
VMOVAPD -0xc4e3(%RIP),%ZMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc7ed(%RIP),%ZMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc7b7(%RIP),%ZMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc781(%RIP),%ZMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc74b(%RIP),%ZMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc715(%RIP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc6df(%RIP),%ZMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc6a9(%RIP),%ZMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc673(%RIP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc63d(%RIP),%ZMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc607(%RIP),%ZMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc5d1(%RIP),%ZMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
VMOVAPD -0xc59b(%RIP),%ZMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (100.0%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SAL $0x6,%ESI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (6.3%)
MOV 0x18(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x78(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOVSXD %R14D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0x8(%RBX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2118e4 <advanceVelocity.omp_outlined+0x194>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advanceVelocity.omp_outlined–	1.90	0.54
▼Loop 106 - timestep.c:72-78 - exec–	0.03	0.01
○Loop 108 - timestep.c:74-78 - exec	1.54	0.43
○Loop 109 - timestep.c:74-78 - exec	0.21	0.06
○Loop 107 - timestep.c:74-78 - exec	0.13	0.04

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