OV - exec - Function updateLinkCells

	Function: updateLinkCells	Module: exec	Source: linkCells.c:211-385 [...]	Coverage (incl. loops): 0.36% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 211 - 385

--------------------------------------------------------------------------------

211:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

212:          (gridSize[0]+2)*(gridSize[1]+2) + (gridSize[0]+2)*(iy+1) + (ix+1);

213:    }

214:    // Halo in Z-

215:    else if (iz == -1)

216:    {

217:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + 2*gridSize[2]*(gridSize[0]+2) +

218:          (gridSize[0]+2)*(iy+1) + (ix+1);

219:    }

220:    // Halo in Y+

221:    else if (iy == gridSize[1])

222:    {

223:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + gridSize[2]*(gridSize[0]+2) +

224:          (gridSize[0]+2)*iz + (ix+1);

225:    }

226:    // Halo in Y-

227:    else if (iy == -1)

228:    {

229:       iBox = boxes->nLocalBoxes + 2*gridSize[2]*gridSize[1] + iz*(gridSize[0]+2) + (ix+1);

230:    }

231:    // Halo in X+

232:    else if (ix == gridSize[0])

233:    {

234:       iBox = boxes->nLocalBoxes + gridSize[1]*gridSize[2] + iz*gridSize[1] + iy;

235:    }

236:    // Halo in X-

237:    else if (ix == -1)

238:    {

239:       iBox = boxes->nLocalBoxes + iz*gridSize[1] + iy;

240:    }

241:    // local link celll.

242:    else

243:    {

244:       iBox = ix + gridSize[0]*iy + gridSize[0]*gridSize[1]*iz;

245:    }

246:    assert(iBox >= 0);

247:    assert(iBox < boxes->nTotalBoxes);

[...]

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

[...]

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

[...]

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

372:    {

373:       if (iz == gridSize[2]) iz = gridSize[2] - 1;

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x20e300 PUSH	%RBP

0x20e301 MOV	%RSP,%RBP

0x20e304 PUSH	%R15

0x20e306 PUSH	%R14

0x20e308 PUSH	%R13

0x20e30a PUSH	%R12

0x20e30c PUSH	%RBX

0x20e30d SUB	$0x18,%RSP

0x20e311 MOV	0xc(%RDI),%R8D

0x20e315 CMP	%R8D,0x14(%RDI)

0x20e319 JLE	20e347

0x20e31b MOV	0x78(%RDI),%RCX

0x20e31f MOVSXD	%R8D,%RAX

0x20e322 NOPW	%CS:(%RAX,%RAX,1)

(91) 0x20e330 MOVL	$0,(%RCX,%RAX,4)

(91) 0x20e337 INC	%RAX

(91) 0x20e33a MOVSXD	0x14(%RDI),%RDX

(91) 0x20e33e CMP	%RDX,%RAX

(91) 0x20e341 JL	20e330

0x20e343 MOV	0xc(%RDI),%R8D

0x20e347 TEST	%R8D,%R8D

0x20e34a JLE	20e6ec

0x20e350 MOV	0x78(%RDI),%R10

0x20e354 XOR	%EAX,%EAX

0x20e356 JMP	20e36f

0x20e358 NOPL	(%RAX,%RAX,1)

(89) 0x20e360 INC	%RAX

(89) 0x20e363 MOVSXD	%R8D,%RCX

(89) 0x20e366 CMP	%RCX,%RAX

(89) 0x20e369 JGE	20e6ec

(89) 0x20e36f CMPL	$0,(%R10,%RAX,4)

(89) 0x20e374 JLE	20e360

(89) 0x20e376 MOVSXD	%EAX,%RCX

(89) 0x20e379 XOR	%EDX,%EDX

(89) 0x20e37b SAL	$0x6,%RCX

(89) 0x20e37f MOV	%RCX,-0x38(%RBP)

(89) 0x20e383 JMP	20e3a0

0x20e385 NOPW	%CS:(%RAX,%RAX,1)

  (90) 0x20e390 MOV	-0x30(%RBP),%RDX

  (90) 0x20e394 INC	%EDX

  (90) 0x20e396 MOV	0x78(%RDI),%R10

  (90) 0x20e39a CMP	%EDX,(%R10,%RAX,4)

  (90) 0x20e39e JLE	20e360

  (90) 0x20e3a0 MOV	-0x38(%RBP),%RCX

  (90) 0x20e3a4 MOV	0x18(%RSI),%R11

  (90) 0x20e3a8 VMOVSD	0x30(%RDI),%XMM1

  (90) 0x20e3ad ADD	%EDX,%ECX

  (90) 0x20e3af MOVSXD	%ECX,%R9

  (90) 0x20e3b2 LEA	(%R9,%R9,2),%RBX

  (90) 0x20e3b6 VMOVSD	(%R11,%RBX,8),%XMM0

  (90) 0x20e3bc VUCOMISD	%XMM0,%XMM1

  (90) 0x20e3c0 JBE	20e3f0

  (90) 0x20e3c2 VSUBSD	0x18(%RDI),%XMM0,%XMM0

  (90) 0x20e3c7 MOV	(%RDI),%R12D

  (90) 0x20e3ca VMULSD	0x60(%RDI),%XMM0,%XMM0

  (90) 0x20e3cf VROUNDSD	$0x9,%XMM0,%XMM0,%XMM0

  (90) 0x20e3d5 VCVTTSD2SI	%XMM0,%R15D

  (90) 0x20e3d9 CMP	%R15D,%R12D

  (90) 0x20e3dc JNE	20e3f6

  (90) 0x20e3de LEA	-0x1(%R12),%R15D

  (90) 0x20e3e3 JMP	20e3f6

0x20e3e5 NOPW	%CS:(%RAX,%RAX,1)

  (90) 0x20e3f0 MOV	(%RDI),%R12D

  (90) 0x20e3f3 MOV	%R12D,%R15D

  (90) 0x20e3f6 VMOVSD	0x8(%R11,%RBX,8),%XMM0

  (90) 0x20e3fd MOV	0x4(%RDI),%R13D

  (90) 0x20e401 VSUBSD	0x20(%RDI),%XMM0,%XMM1

  (90) 0x20e406 VMULSD	0x68(%RDI),%XMM1,%XMM1

  (90) 0x20e40b VROUNDSD	$0x9,%XMM1,%XMM1,%XMM1

  (90) 0x20e411 VCVTTSD2SI	%XMM1,%R14D

  (90) 0x20e415 CMP	%R14D,%R13D

  (90) 0x20e418 JNE	20e41e

  (90) 0x20e41a LEA	-0x1(%R13),%R14D

  (90) 0x20e41e VMOVSD	0x38(%RDI),%XMM1

  (90) 0x20e423 VMOVSD	0x10(%R11,%RBX,8),%XMM2

  (90) 0x20e42a VMOVSD	0x40(%RDI),%XMM3

  (90) 0x20e42f MOV	0x8(%RDI),%ECX

  (90) 0x20e432 MOV	%RDX,-0x30(%RBP)

  (90) 0x20e436 VUCOMISD	%XMM0,%XMM1

  (90) 0x20e43a CMOVBE	%R13D,%R14D

  (90) 0x20e43e VUCOMISD	%XMM2,%XMM3

  (90) 0x20e442 JBE	20e4a0

  (90) 0x20e444 VSUBSD	0x28(%RDI),%XMM2,%XMM2

  (90) 0x20e449 VMULSD	0x70(%RDI),%XMM2,%XMM2

  (90) 0x20e44e VROUNDSD	$0x9,%XMM2,%XMM2,%XMM2

  (90) 0x20e454 VCVTTSD2SI	%XMM2,%EDX

  (90) 0x20e458 CMP	%EDX,%ECX

  (90) 0x20e45a JNE	20e45f

  (90) 0x20e45c LEA	-0x1(%RCX),%EDX

  (90) 0x20e45f CMP	$-0x1,%EDX

  (90) 0x20e462 JE	20e4d1

  (90) 0x20e464 VUCOMISD	%XMM0,%XMM1

  (90) 0x20e468 JA	20e4fa

  (90) 0x20e46e IMUL	%ECX,%R13D

  (90) 0x20e472 ADD	%ECX,%EDX

  (90) 0x20e474 ADD	$0x2,%R12D

  (90) 0x20e478 IMUL	%R12D,%EDX

  (90) 0x20e47c LEA	(%R15,%R13,2),%ECX

  (90) 0x20e480 ADD	%R8D,%ECX

  (90) 0x20e483 LEA	0x1(%RDX,%RCX,1),%R14D

  (90) 0x20e488 TEST	%R14D,%R14D

  (90) 0x20e48b JNS	20e570

0x20e491 JMP	20e6fb

0x20e496 NOPW	%CS:(%RAX,%RAX,1)

  (90) 0x20e4a0 LEA	(%RCX,%RCX,1),%EDX

  (90) 0x20e4a3 LEA	(%R14,%RCX,2),%ECX

  (90) 0x20e4a7 ADD	$0x2,%R12D

  (90) 0x20e4ab ADD	%R8D,%R15D

  (90) 0x20e4ae IMUL	%R13D,%EDX

  (90) 0x20e4b2 LEA	0x3(%R13,%RCX,1),%ECX

  (90) 0x20e4b7 IMUL	%R12D,%ECX

  (90) 0x20e4bb ADD	%EDX,%R15D

  (90) 0x20e4be LEA	0x1(%RCX,%R15,1),%R14D

  (90) 0x20e4c3 TEST	%R14D,%R14D

  (90) 0x20e4c6 JNS	20e570

0x20e4cc JMP	20e6fb

  (90) 0x20e4d1 LEA	(%RCX,%RCX,1),%EDX

  (90) 0x20e4d4 LEA	0x1(%R14,%RCX,2),%ECX

  (90) 0x20e4d9 ADD	$0x2,%R12D

  (90) 0x20e4dd ADD	%R8D,%R15D

  (90) 0x20e4e0 IMUL	%EDX,%R13D

  (90) 0x20e4e4 IMUL	%R12D,%ECX

  (90) 0x20e4e8 ADD	%R13D,%R15D

  (90) 0x20e4eb LEA	0x1(%RCX,%R15,1),%R14D

  (90) 0x20e4f0 TEST	%R14D,%R14D

  (90) 0x20e4f3 JNS	20e570

0x20e4f5 JMP	20e6fb

  (90) 0x20e4fa CMP	$-0x1,%R14D

  (90) 0x20e4fe JE	20e51b

  (90) 0x20e500 CMP	%R15D,%R12D

  (90) 0x20e503 JNE	20e53d

  (90) 0x20e505 ADD	%EDX,%ECX

  (90) 0x20e507 ADD	%R8D,%R14D

  (90) 0x20e50a IMUL	%ECX,%R13D

  (90) 0x20e50e ADD	%R13D,%R14D

  (90) 0x20e511 TEST	%R14D,%R14D

  (90) 0x20e514 JNS	20e570

0x20e516 JMP	20e6fb

  (90) 0x20e51b IMUL	%R13D,%ECX

  (90) 0x20e51f ADD	$0x2,%R12D

  (90) 0x20e523 IMUL	%EDX,%R12D

  (90) 0x20e527 LEA	(%R15,%RCX,2),%ECX

  (90) 0x20e52b ADD	%R8D,%ECX

  (90) 0x20e52e LEA	0x1(%R12,%RCX,1),%R14D

  (90) 0x20e533 TEST	%R14D,%R14D

  (90) 0x20e536 JNS	20e570

0x20e538 JMP	20e6fb

  (90) 0x20e53d IMUL	%EDX,%R13D

  (90) 0x20e541 ADD	%R14D,%R13D

  (90) 0x20e544 CMP	$-0x1,%R15D

  (90) 0x20e548 JE	20e55e

  (90) 0x20e54a IMUL	%R13D,%R12D

  (90) 0x20e54e ADD	%R15D,%R12D

  (90) 0x20e551 MOV	%R12D,%R14D

  (90) 0x20e554 TEST	%R14D,%R14D

  (90) 0x20e557 JNS	20e570

0x20e559 JMP	20e6fb

  (90) 0x20e55e ADD	%R8D,%R13D

  (90) 0x20e561 MOV	%R13D,%R14D

  (90) 0x20e564 TEST	%R14D,%R14D

  (90) 0x20e567 JS	20e6fb

  (90) 0x20e56d NOPL	(%RAX)

  (90) 0x20e570 CMP	%R14D,0x14(%RDI)

  (90) 0x20e574 JLE	20e71a

  (90) 0x20e57a MOV	%R14D,%EDX

  (90) 0x20e57d CMP	%RDX,%RAX

  (90) 0x20e580 JE	20e390

  (90) 0x20e586 MOV	0x8(%RSI),%R15

  (90) 0x20e58a MOVSXD	(%R10,%RDX,4),%R10

  (90) 0x20e58e LEA	(%R11,%RBX,8),%RCX

  (90) 0x20e592 MOVSXD	%R14D,%R8

  (90) 0x20e595 SAL	$0x6,%R8

  (90) 0x20e599 MOV	(%R15,%R9,4),%EBX

  (90) 0x20e59d ADD	%R10,%R8

  (90) 0x20e5a0 MOV	%EBX,(%R15,%R8,4)

  (90) 0x20e5a4 MOV	0x10(%RSI),%R10

  (90) 0x20e5a8 MOV	(%R10,%R9,4),%EBX

  (90) 0x20e5ac MOV	%EBX,(%R10,%R8,4)

  (90) 0x20e5b0 LEA	(,%R8,8),%R10

  (90) 0x20e5b8 MOV	0x10(%RCX),%RBX

  (90) 0x20e5bc LEA	(%R10,%R10,2),%R10

  (90) 0x20e5c0 MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x20e5c5 VMOVUPS	(%RCX),%XMM0

  (90) 0x20e5c9 LEA	(,%R9,8),%RCX

  (90) 0x20e5d1 LEA	(%RCX,%RCX,2),%RCX

  (90) 0x20e5d5 VMOVUPS	%XMM0,(%R11,%R10,1)

  (90) 0x20e5db MOV	0x20(%RSI),%R11

  (90) 0x20e5df MOV	0x10(%R11,%RCX,1),%RBX

  (90) 0x20e5e4 MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x20e5e9 VMOVUPS	(%R11,%RCX,1),%XMM0

  (90) 0x20e5ef VMOVUPS	%XMM0,(%R11,%R10,1)

  (90) 0x20e5f5 MOV	0x28(%RSI),%R11

  (90) 0x20e5f9 MOV	0x10(%R11,%RCX,1),%RBX

  (90) 0x20e5fe MOV	%RBX,0x10(%R11,%R10,1)

  (90) 0x20e603 VMOVUPD	(%R11,%RCX,1),%XMM0

  (90) 0x20e609 VMOVUPD	%XMM0,(%R11,%R10,1)

  (90) 0x20e60f MOV	0x30(%RSI),%R10

  (90) 0x20e613 MOV	(%R10,%R9,8),%R11

  (90) 0x20e617 MOV	%R11,(%R10,%R8,8)

  (90) 0x20e61b MOV	0x78(%RDI),%R8

  (90) 0x20e61f MOV	(%R8,%RDX,4),%R10D

  (90) 0x20e623 LEA	0x1(%R10),%R11D

  (90) 0x20e627 MOV	%R11D,(%R8,%RDX,4)

  (90) 0x20e62b CMP	$0x3f,%R10D

  (90) 0x20e62f JGE	20e739

  (90) 0x20e635 MOVSXD	(%R8,%RAX,4),%RDX

  (90) 0x20e639 DEC	%RDX

  (90) 0x20e63c MOV	%EDX,(%R8,%RAX,4)

  (90) 0x20e640 TEST	%EDX,%EDX

  (90) 0x20e642 JE	20e6ca

  (90) 0x20e648 ADD	-0x38(%RBP),%RDX

  (90) 0x20e64c MOV	0x8(%RSI),%R8

  (90) 0x20e650 MOV	(%R8,%RDX,4),%R10D

  (90) 0x20e654 MOV	%R10D,(%R8,%R9,4)

  (90) 0x20e658 MOV	0x10(%RSI),%R8

  (90) 0x20e65c MOV	(%R8,%RDX,4),%R10D

  (90) 0x20e660 MOV	%R10D,(%R8,%R9,4)

  (90) 0x20e664 LEA	(,%RDX,8),%R8

  (90) 0x20e66c MOV	0x18(%RSI),%R10

  (90) 0x20e670 LEA	(%R8,%R8,2),%R8

  (90) 0x20e674 MOV	0x10(%R10,%R8,1),%R11

  (90) 0x20e679 MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x20e67e VMOVUPS	(%R10,%R8,1),%XMM0

  (90) 0x20e684 VMOVUPS	%XMM0,(%R10,%RCX,1)

  (90) 0x20e68a MOV	0x20(%RSI),%R10

  (90) 0x20e68e MOV	0x10(%R10,%R8,1),%R11

  (90) 0x20e693 MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x20e698 VMOVUPS	(%R10,%R8,1),%XMM0

  (90) 0x20e69e VMOVUPS	%XMM0,(%R10,%RCX,1)

  (90) 0x20e6a4 MOV	0x28(%RSI),%R10

  (90) 0x20e6a8 MOV	0x10(%R10,%R8,1),%R11

  (90) 0x20e6ad MOV	%R11,0x10(%R10,%RCX,1)

  (90) 0x20e6b2 VMOVUPD	(%R10,%R8,1),%XMM0

  (90) 0x20e6b8 VMOVUPD	%XMM0,(%R10,%RCX,1)

  (90) 0x20e6be MOV	0x30(%RSI),%RCX

  (90) 0x20e6c2 MOV	(%RCX,%RDX,8),%RDX

  (90) 0x20e6c6 MOV	%RDX,(%RCX,%R9,8)

  (90) 0x20e6ca MOV	0xc(%RDI),%R8D

  (90) 0x20e6ce CMP	%R14D,%R8D

  (90) 0x20e6d1 JGE	20e6d5

  (90) 0x20e6d3 DECL	(%RSI)

  (90) 0x20e6d5 MOV	-0x30(%RBP),%RDX

  (90) 0x20e6d9 MOV	0x78(%RDI),%R10

  (90) 0x20e6dd CMP	(%R10,%RAX,4),%EDX

  (90) 0x20e6e1 JL	20e3a0

(89) 0x20e6e7 JMP	20e360

0x20e6ec ADD	$0x18,%RSP

0x20e6f0 POP	%RBX

0x20e6f1 POP	%R12

0x20e6f3 POP	%R13

0x20e6f5 POP	%R14

0x20e6f7 POP	%R15

0x20e6f9 POP	%RBP

0x20e6fa RET

0x20e6fb LEA	-0xa26f(%RIP),%RDI

0x20e702 LEA	-0xbec1(%RIP),%RSI

0x20e709 LEA	-0xa51e(%RIP),%RCX

0x20e710 MOV	$0xf6,%EDX

0x20e715 CALL	2124e0 <@plt_start@+0xe0>

0x20e71a LEA	-0xb9bc(%RIP),%RDI

0x20e721 LEA	-0xbee0(%RIP),%RSI

0x20e728 LEA	-0xa53d(%RIP),%RCX

0x20e72f MOV	$0xf7,%EDX

0x20e734 CALL	2124e0 <@plt_start@+0xe0>

0x20e739 LEA	-0xbe9c(%RIP),%RDI

0x20e740 LEA	-0xbeff(%RIP),%RSI

0x20e747 LEA	-0xc763(%RIP),%RCX

0x20e74e MOV	$0x106,%EDX

0x20e753 CALL	2124e0 <@plt_start@+0xe0>

0x20e758 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:211-385
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:211-247,258-269,288-304,327-334,352,359-365,371-373,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 6.38 to 0.41 cycles (15.43x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	54
nb uops	51
loop length	255
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	5.00
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.38 cycles. At this rate:

1% of peak load performance is reached (4.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.38 to 5.00 cycles (1.27x speedup).

ASM code

In the binary file, the address of the function is: 20e300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP %R8D,0x14(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JLE 20e347 <updateLinkCells+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20e6ec <updateLinkCells+0x3ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 20e36f <updateLinkCells+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
LEA -0xa26f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xbec1(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa51e(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 2124e0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xb9bc(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xbee0(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa53d(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 2124e0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xbe9c(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xbeff(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc763(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 2124e0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	linkCells.c:211-385
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:246
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:247
- /home/eoseret/qaas_runs_ZEN5/174-043-3878/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:262

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	54
nb uops	51
loop length	255
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.38 cycles
front end	6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Dispatch	5.00
Overall L1	6.38

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.38 cycles. At this rate:

1% of peak load performance is reached (4.39 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 20e300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
CMP %R8D,0x14(%RDI)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
JLE 20e347 <updateLinkCells+0x47>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOVSXD %R8D,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xc(%RDI),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
TEST %R8D,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 20e6ec <updateLinkCells+0x3ec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 20e36f <updateLinkCells+0x6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 20e6fb <updateLinkCells+0x3fb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
LEA -0xa26f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xbec1(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa51e(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0xf6,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 2124e0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xb9bc(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xbee0(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xa53d(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0xf7,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 2124e0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
LEA -0xbe9c(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xbeff(%RIP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xc763(%RIP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x106,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CALL 2124e0 <@plt_start@+0xe0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼updateLinkCells–	0.36	0.10
▼Loop 89 - linkCells.c:211-373 - exec–	0.00	0.04
○Loop 90 - linkCells.c:211-373 - exec	0.35	3.19
○Loop 91 - linkCells.c:384-385 - exec	0.00	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code