Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 60.87% |
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Function: ljForce._omp_fn.1 | Module: exec | Source: ljForce.c:172-216 [...] | Coverage: 60.87% |
---|
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 172 - 216 |
-------------------------------------------------------------------------------- |
172: #pragma omp parallel for reduction(+:ePot) |
173: for (int iBox=0; iBox<s->boxes->nLocalBoxes; iBox++) |
174: { |
175: int nIBox = s->boxes->nAtoms[iBox]; |
176: |
177: // loop over neighbors of iBox |
178: for (int jTmp=0; jTmp<nNbrBoxes; jTmp++) |
179: { |
180: int jBox = s->boxes->nbrBoxes[iBox][jTmp]; |
181: |
182: assert(jBox>=0); |
183: |
184: int nJBox = s->boxes->nAtoms[jBox]; |
185: |
186: // loop over atoms in iBox |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
0x40bab0 PUSH %RBP |
0x40bab1 MOV %RSP,%RBP |
0x40bab4 PUSH %R15 |
0x40bab6 PUSH %R14 |
0x40bab8 PUSH %R13 |
0x40baba PUSH %R12 |
0x40babc MOV %RDI,%R12 |
0x40babf PUSH %RBX |
0x40bac0 SUB $0x68,%RSP |
0x40bac4 VMOVSD 0x18(%RDI),%XMM10 |
0x40bac9 VMOVSD 0x10(%RDI),%XMM9 |
0x40bace MOV 0x30(%RDI),%EAX |
0x40bad1 VMOVSD 0x20(%RDI),%XMM5 |
0x40bad6 VMOVSD 0x8(%RDI),%XMM8 |
0x40badb MOV (%RDI),%R15 |
0x40bade VMOVSD %XMM10,-0x50(%RBP) |
0x40bae3 VMOVSD %XMM9,-0x48(%RBP) |
0x40bae8 VMOVSD %XMM5,-0x38(%RBP) |
0x40baed MOV 0x18(%R15),%R13 |
0x40baf1 VMOVSD %XMM8,-0x40(%RBP) |
0x40baf6 MOV %EAX,-0x64(%RBP) |
0x40baf9 CALL 403060 <omp_get_num_threads@plt> |
0x40bafe MOV %EAX,%EBX |
0x40bb00 CALL 403160 <omp_get_thread_num@plt> |
0x40bb05 VMOVSD -0x40(%RBP),%XMM0 |
0x40bb0a VMOVSD -0x48(%RBP),%XMM9 |
0x40bb0f MOV %EAX,%ECX |
0x40bb11 MOV 0xc(%R13),%EAX |
0x40bb15 VMOVSD -0x50(%RBP),%XMM10 |
0x40bb1a CLTD |
0x40bb1b IDIV %EBX |
0x40bb1d CMP %EDX,%ECX |
0x40bb1f JL 40bf04 |
0x40bb25 IMUL %EAX,%ECX |
0x40bb28 ADD %ECX,%EDX |
0x40bb2a ADD %EDX,%EAX |
0x40bb2c MOV %EAX,-0x68(%RBP) |
0x40bb2f CMP %EAX,%EDX |
0x40bb31 JGE 40bf1a |
0x40bb37 MOVSXD -0x64(%RBP),%RSI |
0x40bb3b MOVSXD %EDX,%RAX |
0x40bb3e MOV 0x78(%R13),%R14 |
0x40bb42 SAL $0x6,%EDX |
0x40bb45 VMULSD 0x6583(%RIP),%XMM0,%XMM8 |
0x40bb4d MOV %EDX,%ECX |
0x40bb4f VXORPD %XMM5,%XMM5,%XMM5 |
0x40bb53 VMOVSD 0x5bdd(%RIP),%XMM7 |
0x40bb5b LEA (,%RSI,4),%RDI |
0x40bb63 VMOVSD 0x5f8d(%RIP),%XMM6 |
0x40bb6b VMOVSD 0x6565(%RIP),%XMM11 |
0x40bb73 MOV %RDI,-0x70(%RBP) |
(83) 0x40bb77 MOV -0x64(%RBP),%R9D |
(83) 0x40bb7b MOV (%R14,%RAX,4),%R8D |
(83) 0x40bb7f TEST %R9D,%R9D |
(83) 0x40bb82 JLE 40beba |
(83) 0x40bb88 MOV 0x80(%R13),%R11 |
(83) 0x40bb8f MOV %EAX,%ESI |
(83) 0x40bb91 LEA (%R8,%RCX,1),%R10D |
(83) 0x40bb95 MOV %ECX,-0x7c(%RBP) |
(83) 0x40bb98 SAL $0x6,%ESI |
(83) 0x40bb9b MOV -0x70(%RBP),%RBX |
(83) 0x40bb9f LEA -0x1(%R10),%R9D |
(83) 0x40bba3 MOV %R13,-0x78(%RBP) |
(83) 0x40bba7 MOVSXD %ESI,%R8 |
(83) 0x40bbaa MOV (%R11,%RAX,8),%RDX |
(83) 0x40bbae SUB %ESI,%R9D |
(83) 0x40bbb1 MOV %R14,-0x48(%RBP) |
(83) 0x40bbb5 LEA (,%R8,8),%RDI |
(83) 0x40bbbd MOV %R10D,-0x5c(%RBP) |
(83) 0x40bbc1 VMOVSD 0x6517(%RIP),%XMM12 |
(83) 0x40bbc9 ADD %RDX,%RBX |
(83) 0x40bbcc MOV %RDI,-0x58(%RBP) |
(83) 0x40bbd0 MOV %ESI,-0x60(%RBP) |
(83) 0x40bbd3 MOV %RAX,-0x88(%RBP) |
(83) 0x40bbda MOV %RBX,-0x50(%RBP) |
(83) 0x40bbde LEA 0x1(%R8,%R9,1),%RBX |
(83) 0x40bbe3 MOV %R12,%R9 |
(83) 0x40bbe6 SAL $0x3,%RBX |
(85) 0x40bbea MOV (%RDX),%R11D |
(85) 0x40bbed TEST %R11D,%R11D |
(85) 0x40bbf0 JS 40bf20 |
(85) 0x40bbf6 MOV -0x48(%RBP),%R13 |
(85) 0x40bbfa MOVSXD %R11D,%R12 |
(85) 0x40bbfd MOV -0x60(%RBP),%EAX |
(85) 0x40bc00 MOV (%R13,%R12,4),%R14D |
(85) 0x40bc05 CMP %EAX,-0x5c(%RBP) |
(85) 0x40bc08 JLE 40be97 |
(85) 0x40bc0e LEA (%R12,%R12,2),%R12 |
(85) 0x40bc12 MOV %RDX,-0x40(%RBP) |
(85) 0x40bc16 SAL $0x6,%R11D |
(85) 0x40bc1a LEA (%R14,%R14,2),%RCX |
(85) 0x40bc1e SAL $0x9,%R12 |
(85) 0x40bc22 MOV -0x58(%RBP),%R8 |
(85) 0x40bc26 LEA (%R14,%R11,1),%R13D |
(85) 0x40bc2a VXORPD %XMM4,%XMM4,%XMM4 |
(85) 0x40bc2e LEA (%R12,%RCX,8),%R14 |
(85) 0x40bc32 NOPW (%RAX,%RAX,1) |
(86) 0x40bc38 CMP %R13D,%R11D |
(86) 0x40bc3b JGE 40be86 |
(86) 0x40bc41 MOV 0x20(%R15),%RDI |
(86) 0x40bc45 LEA (%R8,%R8,2),%R10 |
(86) 0x40bc49 MOV 0x18(%RDI),%RCX |
(86) 0x40bc4d LEA (%RCX,%R12,1),%RAX |
(86) 0x40bc51 LEA (%RCX,%R10,1),%RDX |
(86) 0x40bc55 ADD %R14,%RCX |
(86) 0x40bc58 MOV %RCX,%RSI |
(86) 0x40bc5b SUB %RAX,%RSI |
(86) 0x40bc5e AND $0x8,%ESI |
(86) 0x40bc61 JE 40bd20 |
(86) 0x40bc67 VMOVSD 0x8(%RDX),%XMM2 |
(86) 0x40bc6c VSUBSD 0x8(%RAX),%XMM2,%XMM0 |
(86) 0x40bc71 VMOVSD (%RDX),%XMM1 |
(86) 0x40bc75 VSUBSD (%RAX),%XMM1,%XMM1 |
(86) 0x40bc79 VMOVSD 0x10(%RDX),%XMM13 |
(86) 0x40bc7e VSUBSD 0x10(%RAX),%XMM13,%XMM2 |
(86) 0x40bc83 VMULSD %XMM0,%XMM0,%XMM3 |
(86) 0x40bc87 VFMADD231SD %XMM1,%XMM1,%XMM3 |
(86) 0x40bc8c VFMADD231SD %XMM2,%XMM2,%XMM3 |
(86) 0x40bc91 VCOMISD %XMM3,%XMM9 |
(86) 0x40bc95 JB 40bd11 |
(86) 0x40bc97 VCOMISD %XMM4,%XMM3 |
(86) 0x40bc9b JBE 40bd11 |
(86) 0x40bc9d VDIVSD %XMM3,%XMM7,%XMM15 |
(86) 0x40bca1 MOV 0x30(%RDI),%RSI |
(86) 0x40bca5 ADD %R8,%RSI |
(86) 0x40bca8 VMULSD %XMM15,%XMM15,%XMM13 |
(86) 0x40bcad VMULSD %XMM15,%XMM10,%XMM3 |
(86) 0x40bcb2 VMULSD %XMM15,%XMM8,%XMM14 |
(86) 0x40bcb7 VMULSD %XMM3,%XMM13,%XMM3 |
(86) 0x40bcbb VSUBSD %XMM7,%XMM3,%XMM13 |
(86) 0x40bcbf VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(86) 0x40bcc5 VMOVSD %XMM13,%XMM13,%XMM15 |
(86) 0x40bcca VFMADD231SD %XMM6,%XMM13,%XMM5 |
(86) 0x40bccf VMOVSD %XMM3,%XMM3,%XMM13 |
(86) 0x40bcd3 VFMADD132SD %XMM11,%XMM12,%XMM13 |
(86) 0x40bcd8 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(86) 0x40bcdd VMULSD %XMM13,%XMM3,%XMM3 |
(86) 0x40bce2 VMOVSD %XMM15,(%RSI) |
(86) 0x40bce6 MOV 0x28(%RDI),%RSI |
(86) 0x40bcea ADD %R10,%RSI |
(86) 0x40bced VMULSD %XMM14,%XMM3,%XMM14 |
(86) 0x40bcf2 VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(86) 0x40bcf7 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(86) 0x40bcfd VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(86) 0x40bd03 VMOVSD %XMM1,(%RSI) |
(86) 0x40bd07 VMOVSD %XMM0,0x8(%RSI) |
(86) 0x40bd0c VMOVSD %XMM14,0x10(%RSI) |
(86) 0x40bd11 ADD $0x18,%RAX |
(86) 0x40bd15 CMP %RAX,%RCX |
(86) 0x40bd18 JE 40be86 |
(86) 0x40bd1e XCHG %AX,%AX |
(87) 0x40bd20 VMOVSD 0x8(%RDX),%XMM0 |
(87) 0x40bd25 VSUBSD 0x8(%RAX),%XMM0,%XMM0 |
(87) 0x40bd2a VMOVSD (%RDX),%XMM1 |
(87) 0x40bd2e VSUBSD (%RAX),%XMM1,%XMM1 |
(87) 0x40bd32 VMOVSD 0x10(%RDX),%XMM2 |
(87) 0x40bd37 VSUBSD 0x10(%RAX),%XMM2,%XMM2 |
(87) 0x40bd3c VMULSD %XMM0,%XMM0,%XMM15 |
(87) 0x40bd40 VFMADD231SD %XMM1,%XMM1,%XMM15 |
(87) 0x40bd45 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(87) 0x40bd4a VCOMISD %XMM15,%XMM9 |
(87) 0x40bd4f JB 40bdca |
(87) 0x40bd51 VCOMISD %XMM4,%XMM15 |
(87) 0x40bd55 JBE 40bdca |
(87) 0x40bd57 VDIVSD %XMM15,%XMM7,%XMM3 |
(87) 0x40bd5c MOV 0x30(%RDI),%RSI |
(87) 0x40bd60 ADD %R8,%RSI |
(87) 0x40bd63 VMULSD %XMM3,%XMM3,%XMM13 |
(87) 0x40bd67 VMULSD %XMM3,%XMM10,%XMM15 |
(87) 0x40bd6b VMULSD %XMM3,%XMM8,%XMM14 |
(87) 0x40bd6f VMULSD %XMM15,%XMM13,%XMM3 |
(87) 0x40bd74 VSUBSD %XMM7,%XMM3,%XMM13 |
(87) 0x40bd78 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(87) 0x40bd7e VMOVSD %XMM13,%XMM13,%XMM15 |
(87) 0x40bd83 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(87) 0x40bd88 VMOVSD %XMM3,%XMM3,%XMM13 |
(87) 0x40bd8c VFMADD132SD %XMM11,%XMM12,%XMM13 |
(87) 0x40bd91 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(87) 0x40bd96 VMULSD %XMM13,%XMM3,%XMM3 |
(87) 0x40bd9b VMOVSD %XMM15,(%RSI) |
(87) 0x40bd9f MOV 0x28(%RDI),%RSI |
(87) 0x40bda3 ADD %R10,%RSI |
(87) 0x40bda6 VMULSD %XMM14,%XMM3,%XMM14 |
(87) 0x40bdab VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(87) 0x40bdb0 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(87) 0x40bdb6 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(87) 0x40bdbc VMOVSD %XMM1,(%RSI) |
(87) 0x40bdc0 VMOVSD %XMM0,0x8(%RSI) |
(87) 0x40bdc5 VMOVSD %XMM14,0x10(%RSI) |
(87) 0x40bdca VMOVSD 0x8(%RDX),%XMM0 |
(87) 0x40bdcf VSUBSD 0x20(%RAX),%XMM0,%XMM0 |
(87) 0x40bdd4 LEA 0x18(%RAX),%RSI |
(87) 0x40bdd8 VMOVSD (%RDX),%XMM1 |
(87) 0x40bddc VSUBSD 0x18(%RAX),%XMM1,%XMM1 |
(87) 0x40bde1 VMOVSD 0x10(%RDX),%XMM2 |
(87) 0x40bde6 VSUBSD 0x28(%RAX),%XMM2,%XMM2 |
(87) 0x40bdeb VMULSD %XMM0,%XMM0,%XMM15 |
(87) 0x40bdef VFMADD231SD %XMM1,%XMM1,%XMM15 |
(87) 0x40bdf4 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(87) 0x40bdf9 VCOMISD %XMM15,%XMM9 |
(87) 0x40bdfe JB 40be79 |
(87) 0x40be00 VCOMISD %XMM4,%XMM15 |
(87) 0x40be04 JBE 40be79 |
(87) 0x40be06 VDIVSD %XMM15,%XMM7,%XMM3 |
(87) 0x40be0b MOV 0x30(%RDI),%RAX |
(87) 0x40be0f ADD %R8,%RAX |
(87) 0x40be12 VMULSD %XMM3,%XMM3,%XMM13 |
(87) 0x40be16 VMULSD %XMM3,%XMM10,%XMM15 |
(87) 0x40be1a VMULSD %XMM3,%XMM8,%XMM14 |
(87) 0x40be1e VMULSD %XMM15,%XMM13,%XMM3 |
(87) 0x40be23 VSUBSD %XMM7,%XMM3,%XMM13 |
(87) 0x40be27 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(87) 0x40be2d VMOVSD %XMM13,%XMM13,%XMM15 |
(87) 0x40be32 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(87) 0x40be37 VMOVSD %XMM3,%XMM3,%XMM13 |
(87) 0x40be3b VFMADD132SD %XMM11,%XMM12,%XMM13 |
(87) 0x40be40 VFMADD213SD (%RAX),%XMM6,%XMM15 |
(87) 0x40be45 VMULSD %XMM13,%XMM3,%XMM3 |
(87) 0x40be4a VMOVSD %XMM15,(%RAX) |
(87) 0x40be4e MOV 0x28(%RDI),%RAX |
(87) 0x40be52 ADD %R10,%RAX |
(87) 0x40be55 VMULSD %XMM14,%XMM3,%XMM14 |
(87) 0x40be5a VFNMADD213SD (%RAX),%XMM14,%XMM1 |
(87) 0x40be5f VFNMADD213SD 0x8(%RAX),%XMM14,%XMM0 |
(87) 0x40be65 VFNMADD213SD 0x10(%RAX),%XMM2,%XMM14 |
(87) 0x40be6b VMOVSD %XMM1,(%RAX) |
(87) 0x40be6f VMOVSD %XMM0,0x8(%RAX) |
(87) 0x40be74 VMOVSD %XMM14,0x10(%RAX) |
(87) 0x40be79 LEA 0x18(%RSI),%RAX |
(87) 0x40be7d CMP %RAX,%RCX |
(87) 0x40be80 JNE 40bd20 |
(86) 0x40be86 ADD $0x8,%R8 |
(86) 0x40be8a CMP %R8,%RBX |
(86) 0x40be8d JNE 40bc38 |
(85) 0x40be93 MOV -0x40(%RBP),%RDX |
(85) 0x40be97 ADD $0x4,%RDX |
(85) 0x40be9b CMP %RDX,-0x50(%RBP) |
(85) 0x40be9f JNE 40bbea |
(83) 0x40bea5 MOV -0x78(%RBP),%R13 |
(83) 0x40bea9 MOV -0x48(%RBP),%R14 |
(83) 0x40bead MOV %R9,%R12 |
(83) 0x40beb0 MOV -0x7c(%RBP),%ECX |
(83) 0x40beb3 MOV -0x88(%RBP),%RAX |
(83) 0x40beba INC %RAX |
(83) 0x40bebd ADD $0x40,%ECX |
(83) 0x40bec0 CMP %EAX,-0x68(%RBP) |
(83) 0x40bec3 JG 40bb77 |
0x40bec9 MOV 0x28(%R12),%R11 |
0x40bece LEA 0x28(%R12),%R15 |
(84) 0x40bed3 VMOVQ %R11,%XMM9 |
(84) 0x40bed8 MOV %R11,%RAX |
(84) 0x40bedb VADDSD %XMM9,%XMM5,%XMM10 |
(84) 0x40bee0 VMOVQ %XMM10,%RBX |
(84) 0x40bee5 LOCK CMPXCHG %RBX,(%R15) |
(84) 0x40beea MOV %R11,%R9 |
(84) 0x40beed MOV %RAX,%R11 |
(84) 0x40bef0 CMP %RAX,%R9 |
(84) 0x40bef3 JNE 40bed3 |
0x40bef5 ADD $0x68,%RSP |
0x40bef9 POP %RBX |
0x40befa POP %R12 |
0x40befc POP %R13 |
0x40befe POP %R14 |
0x40bf00 POP %R15 |
0x40bf02 POP %RBP |
0x40bf03 RET |
0x40bf04 INC %EAX |
0x40bf06 XOR %EDX,%EDX |
0x40bf08 IMUL %EAX,%ECX |
0x40bf0b ADD %ECX,%EDX |
0x40bf0d ADD %EDX,%EAX |
0x40bf0f MOV %EAX,-0x68(%RBP) |
0x40bf12 CMP %EAX,%EDX |
0x40bf14 JL 40bb37 |
0x40bf1a VXORPD %XMM5,%XMM5,%XMM5 |
0x40bf1e JMP 40bec9 |
0x40bf20 MOV $0x4120c8,%ECX |
0x40bf25 MOV $0xb6,%EDX |
0x40bf2a MOV $0x411fd0,%ESI |
0x40bf2f MOV $0x4120bd,%EDI |
0x40bf34 CALL 4030c0 <__assert_fail@plt> |
0x40bf39 NOPL (%RAX) |
Path / |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 77 |
nb uops | 79 |
loop length | 284 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 8 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 13.17 cycles |
front end | 13.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.50 | 6.50 | 6.50 | 6.50 | 5.00 | 9.67 | 9.67 | 9.67 | 0.50 | 0.50 | 0.00 | 0.00 | 2.00 | 2.00 |
cycles | 6.50 | 6.50 | 6.50 | 6.50 | 5.00 | 9.67 | 9.67 | 9.67 | 0.50 | 0.50 | 0.00 | 0.00 | 2.00 | 2.00 |
Cycles executing div or sqrt instructions | 6.00 |
Front-end | 13.17 |
Dispatch | 9.67 |
DIV/SQRT | 6.00 |
Overall L1 | 13.17 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 7% |
load | 12% |
store | 7% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 10% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB $0x68,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD 0x18(%RDI),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x10(%RDI),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD 0x20(%RDI),%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x8(%RDI),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD %XMM9,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD %XMM5,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD %XMM8,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x48(%RBP),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CLTD | |||||||||||||||||
IDIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-14 | 6 |
CMP %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JL 40bf04 <ljForce._omp_fn.1+0x454> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %EDX,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EAX,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 40bf1a <ljForce._omp_fn.1+0x46a> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOVSXD -0x64(%RBP),%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOVSXD %EDX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SAL $0x6,%EDX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD 0x6583(%RIP),%XMM0,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x5bdd(%RIP),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%RSI,4),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD 0x5f8d(%RIP),%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x6565(%RIP),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x28(%R12),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD $0x68,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %EDX,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EAX,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JL 40bb37 <ljForce._omp_fn.1+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40bec9 <ljForce._omp_fn.1+0x419> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV $0x4120c8,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV $0xb6,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV $0x411fd0,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV $0x4120bd,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CALL 4030c0 <__assert_fail@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Source file and lines | ljForce.c:172-216 |
Module | exec |
nb instructions | 77 |
nb uops | 79 |
loop length | 284 |
used x86 registers | 13 |
used mmx registers | 0 |
used xmm registers | 8 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 13.17 cycles |
front end | 13.17 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.50 | 6.50 | 6.50 | 6.50 | 5.00 | 9.67 | 9.67 | 9.67 | 0.50 | 0.50 | 0.00 | 0.00 | 2.00 | 2.00 |
cycles | 6.50 | 6.50 | 6.50 | 6.50 | 5.00 | 9.67 | 9.67 | 9.67 | 0.50 | 0.50 | 0.00 | 0.00 | 2.00 | 2.00 |
Cycles executing div or sqrt instructions | 6.00 |
Front-end | 13.17 |
Dispatch | 9.67 |
DIV/SQRT | 6.00 |
Overall L1 | 13.17 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 5% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 22% |
all | 7% |
load | 12% |
store | 7% |
mul | 6% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 13% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 10% |
load | 12% |
store | 10% |
mul | 8% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 6% |
other | 10% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
SUB $0x68,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD 0x18(%RDI),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x10(%RDI),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x30(%RDI),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD 0x20(%RDI),%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x8(%RDI),%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV (%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD %XMM10,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD %XMM9,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD %XMM5,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV 0x18(%R15),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD %XMM8,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV %EAX,-0x64(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CALL 403060 <omp_get_num_threads@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %EAX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CALL 403160 <omp_get_thread_num@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD -0x40(%RBP),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD -0x48(%RBP),%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xc(%R13),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD -0x50(%RBP),%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CLTD | |||||||||||||||||
IDIV %EBX | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 9-14 | 6 |
CMP %EDX,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JL 40bf04 <ljForce._omp_fn.1+0x454> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %EDX,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EAX,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JGE 40bf1a <ljForce._omp_fn.1+0x46a> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOVSXD -0x64(%RBP),%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOVSXD %EDX,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV 0x78(%R13),%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SAL $0x6,%EDX | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD 0x6583(%RIP),%XMM0,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x5bdd(%RIP),%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%RSI,4),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD 0x5f8d(%RIP),%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVSD 0x6565(%RIP),%XMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV 0x28(%R12),%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x28(%R12),%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD $0x68,%RSP | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
POP %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
RET | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
IMUL %EAX,%ECX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %ECX,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD %EDX,%EAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,-0x68(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
CMP %EAX,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JL 40bb37 <ljForce._omp_fn.1+0x87> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
VXORPD %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 40bec9 <ljForce._omp_fn.1+0x419> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV $0x4120c8,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV $0xb6,%EDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV $0x411fd0,%ESI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV $0x4120bd,%EDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CALL 4030c0 <__assert_fail@plt> | 2 | 0.50 | 0 | 0 | 0 | 0.50 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼ljForce._omp_fn.1– | 60.87 | 6.17 |
▼Loop 83 - ljForce.c:175-216 - exec– | 0.02 | 0 |
▼Loop 85 - ljForce.c:178-216 - exec– | 0.16 | 0.01 |
▼Loop 86 - ljForce.c:187-216 - exec– | 4.17 | 0.21 |
○Loop 87 - ljForce.c:191-216 - exec | 56.52 | 2.87 |
○Loop 84 - ljForce.c:172-172 - exec | 0 | 0 |