Loop Id: 112 | Module: exec | Source: timestep.c:88-94 | Coverage: 0.68% |
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Loop Id: 112 | Module: exec | Source: timestep.c:88-94 | Coverage: 0.68% |
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0x211f80 MOVSXD (%R9,%R13,4),%R14 [4] |
0x211f84 VMOVSD (%RBX),%XMM2 [1] |
0x211f88 INC %R13 |
0x211f8b VMULSD -0x10(%R12,%R10,1),%XMM2,%XMM2 [2] |
0x211f92 SAL $0x4,%R14 |
0x211f96 VDIVSD 0x8(%R11,%R14,1),%XMM0,%XMM1 [5] |
0x211f9d VFMADD213SD -0x10(%R15,%R10,1),%XMM1,%XMM2 [3] |
0x211fa4 VMOVSD %XMM2,-0x10(%R15,%R10,1) [3] |
0x211fab VMOVSD (%RBX),%XMM2 [1] |
0x211faf VMULSD -0x8(%R12,%R10,1),%XMM2,%XMM2 [2] |
0x211fb6 VFMADD213SD -0x8(%R15,%R10,1),%XMM1,%XMM2 [3] |
0x211fbd VMOVSD %XMM2,-0x8(%R15,%R10,1) [3] |
0x211fc4 VMOVSD (%RBX),%XMM2 [1] |
0x211fc8 VMULSD (%R12,%R10,1),%XMM2,%XMM2 [2] |
0x211fce VFMADD213SD (%R15,%R10,1),%XMM1,%XMM2 [3] |
0x211fd4 VMOVSD %XMM2,(%R15,%R10,1) [3] |
0x211fda ADD $0x18,%R10 |
0x211fde CMP %R13D,%R8D |
0x211fe1 JNE 211f80 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 88 - 94 |
-------------------------------------------------------------------------------- |
88: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
89: { |
90: int iSpecies = s->atoms->iSpecies[iOff]; |
91: real_t invMass = 1.0/s->species[iSpecies].mass; |
92: s->atoms->r[iOff][0] += dt*s->atoms->p[iOff][0]*invMass; |
93: s->atoms->r[iOff][1] += dt*s->atoms->p[iOff][1]*invMass; |
94: s->atoms->r[iOff][2] += dt*s->atoms->p[iOff][2]*invMass; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.13 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | P8, P9, |
Function | .omp_outlined..2 |
Source | timestep.c:88-94 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 4.42 |
CQA cycles if fully vectorized | 1.25 |
Front-end cycles | 3.00 |
DIV/SQRT cycles | 1.25 |
P0 cycles | 1.25 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 0.50 |
P4 cycles | 4.67 |
P5 cycles | 4.67 |
P6 cycles | 4.67 |
P7 cycles | 3.50 |
P8 cycles | 3.50 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 1.50 |
P12 cycles | 1.50 |
P13 cycles | 5.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 19.00 |
Nb uops | 18.00 |
Nb loads | 11.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 3.00 |
Nb FLOP fma | 3.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.60 |
Bytes prefetched | 0.00 |
Bytes loaded | 84.00 |
Bytes stored | 24.00 |
Stride 0 | 1.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.13 |
CQA speedup if fully vectorized | 4.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.07 |
Bottlenecks | P8, P9, |
Function | .omp_outlined..2 |
Source | timestep.c:88-94 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 4.42 |
CQA cycles if fully vectorized | 1.25 |
Front-end cycles | 3.00 |
DIV/SQRT cycles | 1.25 |
P0 cycles | 1.25 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 0.50 |
P4 cycles | 4.67 |
P5 cycles | 4.67 |
P6 cycles | 4.67 |
P7 cycles | 3.50 |
P8 cycles | 3.50 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 1.50 |
P12 cycles | 1.50 |
P13 cycles | 5.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 19.00 |
Nb uops | 18.00 |
Nb loads | 11.00 |
Nb stores | 3.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 3.00 |
Nb FLOP fma | 3.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 21.60 |
Bytes prefetched | 0.00 |
Bytes loaded | 84.00 |
Bytes stored | 24.00 |
Stride 0 | 1.00 |
Stride 1 | 3.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 1.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 0.00 |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 12.50 |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | NA |
Path / |
Function | .omp_outlined..2 |
Source file and lines | timestep.c:88-94 |
Module | exec |
nb instructions | 19 |
nb uops | 18 |
loop length | 99 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 3.00 cycles |
front end | 3.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.25 | 1.25 | 1.00 | 1.00 | 0.50 | 4.67 | 4.67 | 4.67 | 3.50 | 3.50 | 0.00 | 0.00 | 1.50 | 1.50 |
cycles | 1.25 | 1.25 | 1.00 | 1.00 | 0.50 | 4.67 | 4.67 | 4.67 | 3.50 | 3.50 | 0.00 | 0.00 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | 5.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 3.00 |
Dispatch | 4.67 |
DIV/SQRT | 5.00 |
Data deps. | 1.00 |
Overall L1 | 5.00 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVSXD (%R9,%R13,4),%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD (%RBX),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %R13 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMULSD -0x10(%R12,%R10,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
SAL $0x4,%R14 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VDIVSD 0x8(%R11,%R14,1),%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VFMADD213SD -0x10(%R15,%R10,1),%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM2,-0x10(%R15,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%RBX),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD -0x8(%R12,%R10,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD -0x8(%R15,%R10,1),%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM2,-0x8(%R15,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%RBX),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD (%R12,%R10,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD (%R15,%R10,1),%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM2,(%R15,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD $0x18,%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R13D,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 211f80 <.omp_outlined..2+0x110> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | .omp_outlined..2 |
Source file and lines | timestep.c:88-94 |
Module | exec |
nb instructions | 19 |
nb uops | 18 |
loop length | 99 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 3.00 cycles |
front end | 3.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.25 | 1.25 | 1.00 | 1.00 | 0.50 | 4.67 | 4.67 | 4.67 | 3.50 | 3.50 | 0.00 | 0.00 | 1.50 | 1.50 |
cycles | 1.25 | 1.25 | 1.00 | 1.00 | 0.50 | 4.67 | 4.67 | 4.67 | 3.50 | 3.50 | 0.00 | 0.00 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | 5.00 |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 3.00 |
Dispatch | 4.67 |
DIV/SQRT | 5.00 |
Data deps. | 1.00 |
Overall L1 | 5.00 |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 0% |
div/sqrt | 0% |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 12% |
div/sqrt | 12% |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVSXD (%R9,%R13,4),%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMOVSD (%RBX),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
INC %R13 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMULSD -0x10(%R12,%R10,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
SAL $0x4,%R14 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VDIVSD 0x8(%R11,%R14,1),%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
VFMADD213SD -0x10(%R15,%R10,1),%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM2,-0x10(%R15,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%RBX),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD -0x8(%R12,%R10,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD -0x8(%R15,%R10,1),%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM2,-0x8(%R15,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
VMOVSD (%RBX),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMULSD (%R12,%R10,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VFMADD213SD (%R15,%R10,1),%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVSD %XMM2,(%R15,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
ADD $0x18,%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R13D,%R8D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 211f80 <.omp_outlined..2+0x110> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |