Loop Id: 85 | Module: exec | Source: ljForce.c:178-216 [...] | Coverage: 0.16% |
---|
Loop Id: 85 | Module: exec | Source: ljForce.c:178-216 [...] | Coverage: 0.16% |
---|
0x40bbea MOV (%RDX),%R11D |
0x40bbed TEST %R11D,%R11D |
0x40bbf0 JS 40bf20 |
0x40bbf6 MOV -0x48(%RBP),%R13 |
0x40bbfa MOVSXD %R11D,%R12 |
0x40bbfd MOV -0x60(%RBP),%EAX |
0x40bc00 MOV (%R13,%R12,4),%R14D |
0x40bc05 CMP %EAX,-0x5c(%RBP) |
0x40bc08 JLE 40be97 |
0x40bc0e LEA (%R12,%R12,2),%R12 |
0x40bc12 MOV %RDX,-0x40(%RBP) |
0x40bc16 SAL $0x6,%R11D |
0x40bc1a LEA (%R14,%R14,2),%RCX |
0x40bc1e SAL $0x9,%R12 |
0x40bc22 MOV -0x58(%RBP),%R8 |
0x40bc26 LEA (%R14,%R11,1),%R13D |
0x40bc2a VXORPD %XMM4,%XMM4,%XMM4 |
0x40bc2e LEA (%R12,%RCX,8),%R14 |
0x40bc32 NOPW (%RAX,%RAX,1) |
(86) 0x40bc38 CMP %R13D,%R11D |
(86) 0x40bc3b JGE 40be86 |
(86) 0x40bc41 MOV 0x20(%R15),%RDI |
(86) 0x40bc45 LEA (%R8,%R8,2),%R10 |
(86) 0x40bc49 MOV 0x18(%RDI),%RCX |
(86) 0x40bc4d LEA (%RCX,%R12,1),%RAX |
(86) 0x40bc51 LEA (%RCX,%R10,1),%RDX |
(86) 0x40bc55 ADD %R14,%RCX |
(86) 0x40bc58 MOV %RCX,%RSI |
(86) 0x40bc5b SUB %RAX,%RSI |
(86) 0x40bc5e AND $0x8,%ESI |
(86) 0x40bc61 JE 40bd20 |
(86) 0x40bc67 VMOVSD 0x8(%RDX),%XMM2 |
(86) 0x40bc6c VSUBSD 0x8(%RAX),%XMM2,%XMM0 |
(86) 0x40bc71 VMOVSD (%RDX),%XMM1 |
(86) 0x40bc75 VSUBSD (%RAX),%XMM1,%XMM1 |
(86) 0x40bc79 VMOVSD 0x10(%RDX),%XMM13 |
(86) 0x40bc7e VSUBSD 0x10(%RAX),%XMM13,%XMM2 |
(86) 0x40bc83 VMULSD %XMM0,%XMM0,%XMM3 |
(86) 0x40bc87 VFMADD231SD %XMM1,%XMM1,%XMM3 |
(86) 0x40bc8c VFMADD231SD %XMM2,%XMM2,%XMM3 |
(86) 0x40bc91 VCOMISD %XMM3,%XMM9 |
(86) 0x40bc95 JB 40bd11 |
(86) 0x40bc97 VCOMISD %XMM4,%XMM3 |
(86) 0x40bc9b JBE 40bd11 |
(86) 0x40bc9d VDIVSD %XMM3,%XMM7,%XMM15 |
(86) 0x40bca1 MOV 0x30(%RDI),%RSI |
(86) 0x40bca5 ADD %R8,%RSI |
(86) 0x40bca8 VMULSD %XMM15,%XMM15,%XMM13 |
(86) 0x40bcad VMULSD %XMM15,%XMM10,%XMM3 |
(86) 0x40bcb2 VMULSD %XMM15,%XMM8,%XMM14 |
(86) 0x40bcb7 VMULSD %XMM3,%XMM13,%XMM3 |
(86) 0x40bcbb VSUBSD %XMM7,%XMM3,%XMM13 |
(86) 0x40bcbf VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(86) 0x40bcc5 VMOVSD %XMM13,%XMM13,%XMM15 |
(86) 0x40bcca VFMADD231SD %XMM6,%XMM13,%XMM5 |
(86) 0x40bccf VMOVSD %XMM3,%XMM3,%XMM13 |
(86) 0x40bcd3 VFMADD132SD %XMM11,%XMM12,%XMM13 |
(86) 0x40bcd8 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(86) 0x40bcdd VMULSD %XMM13,%XMM3,%XMM3 |
(86) 0x40bce2 VMOVSD %XMM15,(%RSI) |
(86) 0x40bce6 MOV 0x28(%RDI),%RSI |
(86) 0x40bcea ADD %R10,%RSI |
(86) 0x40bced VMULSD %XMM14,%XMM3,%XMM14 |
(86) 0x40bcf2 VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(86) 0x40bcf7 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(86) 0x40bcfd VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(86) 0x40bd03 VMOVSD %XMM1,(%RSI) |
(86) 0x40bd07 VMOVSD %XMM0,0x8(%RSI) |
(86) 0x40bd0c VMOVSD %XMM14,0x10(%RSI) |
(86) 0x40bd11 ADD $0x18,%RAX |
(86) 0x40bd15 CMP %RAX,%RCX |
(86) 0x40bd18 JE 40be86 |
(86) 0x40bd1e XCHG %AX,%AX |
(87) 0x40bd20 VMOVSD 0x8(%RDX),%XMM0 |
(87) 0x40bd25 VSUBSD 0x8(%RAX),%XMM0,%XMM0 |
(87) 0x40bd2a VMOVSD (%RDX),%XMM1 |
(87) 0x40bd2e VSUBSD (%RAX),%XMM1,%XMM1 |
(87) 0x40bd32 VMOVSD 0x10(%RDX),%XMM2 |
(87) 0x40bd37 VSUBSD 0x10(%RAX),%XMM2,%XMM2 |
(87) 0x40bd3c VMULSD %XMM0,%XMM0,%XMM15 |
(87) 0x40bd40 VFMADD231SD %XMM1,%XMM1,%XMM15 |
(87) 0x40bd45 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(87) 0x40bd4a VCOMISD %XMM15,%XMM9 |
(87) 0x40bd4f JB 40bdca |
(87) 0x40bd51 VCOMISD %XMM4,%XMM15 |
(87) 0x40bd55 JBE 40bdca |
(87) 0x40bd57 VDIVSD %XMM15,%XMM7,%XMM3 |
(87) 0x40bd5c MOV 0x30(%RDI),%RSI |
(87) 0x40bd60 ADD %R8,%RSI |
(87) 0x40bd63 VMULSD %XMM3,%XMM3,%XMM13 |
(87) 0x40bd67 VMULSD %XMM3,%XMM10,%XMM15 |
(87) 0x40bd6b VMULSD %XMM3,%XMM8,%XMM14 |
(87) 0x40bd6f VMULSD %XMM15,%XMM13,%XMM3 |
(87) 0x40bd74 VSUBSD %XMM7,%XMM3,%XMM13 |
(87) 0x40bd78 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(87) 0x40bd7e VMOVSD %XMM13,%XMM13,%XMM15 |
(87) 0x40bd83 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(87) 0x40bd88 VMOVSD %XMM3,%XMM3,%XMM13 |
(87) 0x40bd8c VFMADD132SD %XMM11,%XMM12,%XMM13 |
(87) 0x40bd91 VFMADD213SD (%RSI),%XMM6,%XMM15 |
(87) 0x40bd96 VMULSD %XMM13,%XMM3,%XMM3 |
(87) 0x40bd9b VMOVSD %XMM15,(%RSI) |
(87) 0x40bd9f MOV 0x28(%RDI),%RSI |
(87) 0x40bda3 ADD %R10,%RSI |
(87) 0x40bda6 VMULSD %XMM14,%XMM3,%XMM14 |
(87) 0x40bdab VFNMADD213SD (%RSI),%XMM14,%XMM1 |
(87) 0x40bdb0 VFNMADD213SD 0x8(%RSI),%XMM14,%XMM0 |
(87) 0x40bdb6 VFNMADD213SD 0x10(%RSI),%XMM2,%XMM14 |
(87) 0x40bdbc VMOVSD %XMM1,(%RSI) |
(87) 0x40bdc0 VMOVSD %XMM0,0x8(%RSI) |
(87) 0x40bdc5 VMOVSD %XMM14,0x10(%RSI) |
(87) 0x40bdca VMOVSD 0x8(%RDX),%XMM0 |
(87) 0x40bdcf VSUBSD 0x20(%RAX),%XMM0,%XMM0 |
(87) 0x40bdd4 LEA 0x18(%RAX),%RSI |
(87) 0x40bdd8 VMOVSD (%RDX),%XMM1 |
(87) 0x40bddc VSUBSD 0x18(%RAX),%XMM1,%XMM1 |
(87) 0x40bde1 VMOVSD 0x10(%RDX),%XMM2 |
(87) 0x40bde6 VSUBSD 0x28(%RAX),%XMM2,%XMM2 |
(87) 0x40bdeb VMULSD %XMM0,%XMM0,%XMM15 |
(87) 0x40bdef VFMADD231SD %XMM1,%XMM1,%XMM15 |
(87) 0x40bdf4 VFMADD231SD %XMM2,%XMM2,%XMM15 |
(87) 0x40bdf9 VCOMISD %XMM15,%XMM9 |
(87) 0x40bdfe JB 40be79 |
(87) 0x40be00 VCOMISD %XMM4,%XMM15 |
(87) 0x40be04 JBE 40be79 |
(87) 0x40be06 VDIVSD %XMM15,%XMM7,%XMM3 |
(87) 0x40be0b MOV 0x30(%RDI),%RAX |
(87) 0x40be0f ADD %R8,%RAX |
(87) 0x40be12 VMULSD %XMM3,%XMM3,%XMM13 |
(87) 0x40be16 VMULSD %XMM3,%XMM10,%XMM15 |
(87) 0x40be1a VMULSD %XMM3,%XMM8,%XMM14 |
(87) 0x40be1e VMULSD %XMM15,%XMM13,%XMM3 |
(87) 0x40be23 VSUBSD %XMM7,%XMM3,%XMM13 |
(87) 0x40be27 VFMSUB213SD -0x38(%RBP),%XMM3,%XMM13 |
(87) 0x40be2d VMOVSD %XMM13,%XMM13,%XMM15 |
(87) 0x40be32 VFMADD231SD %XMM6,%XMM13,%XMM5 |
(87) 0x40be37 VMOVSD %XMM3,%XMM3,%XMM13 |
(87) 0x40be3b VFMADD132SD %XMM11,%XMM12,%XMM13 |
(87) 0x40be40 VFMADD213SD (%RAX),%XMM6,%XMM15 |
(87) 0x40be45 VMULSD %XMM13,%XMM3,%XMM3 |
(87) 0x40be4a VMOVSD %XMM15,(%RAX) |
(87) 0x40be4e MOV 0x28(%RDI),%RAX |
(87) 0x40be52 ADD %R10,%RAX |
(87) 0x40be55 VMULSD %XMM14,%XMM3,%XMM14 |
(87) 0x40be5a VFNMADD213SD (%RAX),%XMM14,%XMM1 |
(87) 0x40be5f VFNMADD213SD 0x8(%RAX),%XMM14,%XMM0 |
(87) 0x40be65 VFNMADD213SD 0x10(%RAX),%XMM2,%XMM14 |
(87) 0x40be6b VMOVSD %XMM1,(%RAX) |
(87) 0x40be6f VMOVSD %XMM0,0x8(%RAX) |
(87) 0x40be74 VMOVSD %XMM14,0x10(%RAX) |
(87) 0x40be79 LEA 0x18(%RSI),%RAX |
(87) 0x40be7d CMP %RAX,%RCX |
(87) 0x40be80 JNE 40bd20 |
(86) 0x40be86 ADD $0x8,%R8 |
(86) 0x40be8a CMP %R8,%RBX |
(86) 0x40be8d JNE 40bc38 |
0x40be93 MOV -0x40(%RBP),%RDX |
0x40be97 ADD $0x4,%RDX |
0x40be9b CMP %RDX,-0x50(%RBP) |
0x40be9f JNE 40bbea |
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 178 - 216 |
-------------------------------------------------------------------------------- |
178: for (int jTmp=0; jTmp<nNbrBoxes; jTmp++) |
179: { |
180: int jBox = s->boxes->nbrBoxes[iBox][jTmp]; |
181: |
182: assert(jBox>=0); |
183: |
184: int nJBox = s->boxes->nAtoms[jBox]; |
185: |
186: // loop over atoms in iBox |
187: for (int iOff=MAXATOMS*iBox; iOff<(iBox*MAXATOMS+nIBox); iOff++) |
188: { |
189: |
190: // loop over atoms in jBox |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.33 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.46 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.17 |
Bottlenecks | micro-operation queue, |
Function | ljForce._omp_fn.1 |
Source | ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:201-201 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 1.50 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 0.54 |
Front-end cycles | 3.50 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 3.00 |
P1 cycles | 2.75 |
P2 cycles | 2.75 |
P3 cycles | 1.50 |
P4 cycles | 3.00 |
P5 cycles | 3.00 |
P6 cycles | 3.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 23.00 |
Nb uops | 21.00 |
Nb loads | 8.00 |
Nb stores | 1.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 48.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 20.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 33.33 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 9.38 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.33 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 6.46 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.17 |
Bottlenecks | micro-operation queue, |
Function | ljForce._omp_fn.1 |
Source | ljForce.c:178-184,ljForce.c:187-187,ljForce.c:191-191,ljForce.c:201-201 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 1.50 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 0.54 |
Front-end cycles | 3.50 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 3.00 |
P1 cycles | 2.75 |
P2 cycles | 2.75 |
P3 cycles | 1.50 |
P4 cycles | 3.00 |
P5 cycles | 3.00 |
P6 cycles | 3.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 23.00 |
Nb uops | 21.00 |
Nb loads | 8.00 |
Nb stores | 1.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 48.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 20.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 33.33 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 9.38 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | ljForce._omp_fn.1 |
Source file and lines | ljForce.c:178-216 |
Module | exec |
nb instructions | 23 |
nb uops | 21 |
loop length | 96 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 3.50 cycles |
front end | 3.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 3.00 | 2.75 | 2.75 | 1.50 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 3.00 | 3.00 | 2.75 | 2.75 | 1.50 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.50 |
Dispatch | 3.00 |
Overall L1 | 3.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 20% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 33% |
all | 9% |
load | 9% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 9% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%RDX),%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
TEST %R11D,%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JS 40bf20 <ljForce._omp_fn.1+0x470> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x48(%RBP),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOVSXD %R11D,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x60(%RBP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%R13,%R12,4),%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %EAX,-0x5c(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 40be97 <ljForce._omp_fn.1+0x3e7> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA (%R12,%R12,2),%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
SAL $0x6,%R11D | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%R14,2),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SAL $0x9,%R12 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%R14,%R11,1),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R12,%RCX,8),%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV -0x40(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x4,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RDX,-0x50(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JNE 40bbea <ljForce._omp_fn.1+0x13a> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | ljForce._omp_fn.1 |
Source file and lines | ljForce.c:178-216 |
Module | exec |
nb instructions | 23 |
nb uops | 21 |
loop length | 96 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 3.50 cycles |
front end | 3.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 3.00 | 2.75 | 2.75 | 1.50 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 3.00 | 3.00 | 2.75 | 2.75 | 1.50 | 3.00 | 3.00 | 3.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.50 |
Dispatch | 3.00 |
Overall L1 | 3.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 100% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 20% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 33% |
all | 9% |
load | 9% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 25% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 9% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%RDX),%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
TEST %R11D,%R11D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JS 40bf20 <ljForce._omp_fn.1+0x470> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x48(%RBP),%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOVSXD %R11D,%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x60(%RBP),%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%R13,%R12,4),%R14D | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %EAX,-0x5c(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 40be97 <ljForce._omp_fn.1+0x3e7> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA (%R12,%R12,2),%R12 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RDX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
SAL $0x6,%R11D | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (%R14,%R14,2),%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
SAL $0x9,%R12 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA (%R14,%R11,1),%R13D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R12,%RCX,8),%R14 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV -0x40(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADD $0x4,%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %RDX,-0x50(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JNE 40bbea <ljForce._omp_fn.1+0x13a> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |