Loop Id: 123 | Module: exec | Source: timestep.c:74-78 | Coverage: 0.02% |
---|
Loop Id: 123 | Module: exec | Source: timestep.c:74-78 | Coverage: 0.02% |
---|
0x212ac0 VMOVUPD (%R12,%RCX,1),%ZMM18 [3] |
0x212ac7 VMOVUPD 0x40(%R12,%RCX,1),%YMM19 [3] |
0x212acf VMOVUPD 0x40(%R15,%RCX,1),%YMM22 [2] |
0x212ad7 VBROADCASTSD (%RBX),%YMM17 [1] |
0x212add VMOVAPD %ZMM18,%ZMM20 |
0x212ae3 VMOVAPD %ZMM18,%ZMM21 |
0x212ae9 VPERMT2PD %ZMM19,%ZMM0,%ZMM20 |
0x212aef VPERMT2PD %ZMM19,%ZMM1,%ZMM21 |
0x212af5 VPERMT2PD %ZMM19,%ZMM2,%ZMM18 |
0x212afb VMOVUPD (%R15,%RCX,1),%ZMM19 [2] |
0x212b02 VMOVAPD %ZMM19,%ZMM23 |
0x212b08 VPERMT2PD %ZMM22,%ZMM0,%ZMM23 |
0x212b0e VMOVAPD %ZMM19,%ZMM24 |
0x212b14 VPERMT2PD %ZMM22,%ZMM1,%ZMM24 |
0x212b1a VPERMT2PD %ZMM22,%ZMM2,%ZMM19 |
0x212b20 VFMADD231PD %YMM20,%YMM17,%YMM23 |
0x212b26 VFMADD231PD %YMM21,%YMM17,%YMM24 |
0x212b2c VFMADD231PD %YMM18,%YMM17,%YMM19 |
0x212b32 VINSERTF64X4 $0x1,%YMM24,%ZMM23,%ZMM17 |
0x212b39 VMOVAPD %ZMM17,%ZMM18 |
0x212b3f VPERMT2PD %ZMM19,%ZMM3,%ZMM18 |
0x212b45 VPERMT2PD %ZMM19,%ZMM4,%ZMM17 |
0x212b4b VMOVUPD %ZMM17,(%R15,%RCX,1) [2] |
0x212b52 VMOVUPD %YMM18,0x40(%R15,%RCX,1) [2] |
0x212b5a ADD $0x60,%RCX |
0x212b5e ADD $0x4,%R8 |
0x212b62 JNE 212ac0 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78 |
-------------------------------------------------------------------------------- |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.89 |
CQA speedup if fully vectorized | 1.03 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.89 |
Bottlenecks | P9, P10, |
Function | .omp_outlined..244 |
Source | timestep.c:74-78 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | intermediate |
Unroll factor | 4 |
CQA cycles | 8.50 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 4.50 |
CQA cycles if fully vectorized | 8.25 |
Front-end cycles | 4.50 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 3.00 |
P5 cycles | 3.00 |
P6 cycles | 3.00 |
P7 cycles | 3.00 |
P8 cycles | 8.50 |
P9 cycles | 8.50 |
P10 cycles | 0.00 |
P11 cycles | 1.50 |
P12 cycles | 1.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 27.00 |
Nb uops | 27.00 |
Nb loads | 5.00 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.82 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 12.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 34.82 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 96.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 2.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 95.83 |
Vectorization ratio load | 80.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 93.33 |
Vector-efficiency ratio all | 81.77 |
Vector-efficiency ratio load | 62.50 |
Vector-efficiency ratio store | 75.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 90.83 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.89 |
CQA speedup if fully vectorized | 1.03 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.89 |
Bottlenecks | P9, P10, |
Function | .omp_outlined..244 |
Source | timestep.c:74-78 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | intermediate |
Unroll factor | 4 |
CQA cycles | 8.50 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 4.50 |
CQA cycles if fully vectorized | 8.25 |
Front-end cycles | 4.50 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 3.00 |
P5 cycles | 3.00 |
P6 cycles | 3.00 |
P7 cycles | 3.00 |
P8 cycles | 8.50 |
P9 cycles | 8.50 |
P10 cycles | 0.00 |
P11 cycles | 1.50 |
P12 cycles | 1.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 27.00 |
Nb uops | 27.00 |
Nb loads | 5.00 |
Nb stores | 2.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.82 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 12.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 34.82 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 96.00 |
Stride 0 | 1.00 |
Stride 1 | 0.00 |
Stride n | 2.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 95.83 |
Vectorization ratio load | 80.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 93.33 |
Vector-efficiency ratio all | 81.77 |
Vector-efficiency ratio load | 62.50 |
Vector-efficiency ratio store | 75.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 90.83 |
Path / |
Function | .omp_outlined..244 |
Source file and lines | timestep.c:74-78 |
Module | exec |
nb instructions | 27 |
nb uops | 27 |
loop length | 168 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 8 |
used zmm registers | 13 |
nb stack references | 0 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 2.33 | 2.33 | 2.33 | 3.00 | 8.50 | 8.50 | 0.00 | 1.50 | 1.50 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 3.00 | 3.00 | 3.00 | 3.00 | 8.50 | 8.50 | 0.00 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 4.50 |
Dispatch | 8.50 |
Data deps. | 1.00 |
Overall L1 | 8.50 |
all | 95% |
load | 80% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 93% |
all | 81% |
load | 62% |
store | 75% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 90% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R12,%RCX,1),%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%R12,%RCX,1),%YMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD 0x40(%R15,%RCX,1),%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD (%RBX),%YMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %ZMM18,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVAPD %ZMM18,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPERMT2PD %ZMM19,%ZMM0,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VPERMT2PD %ZMM19,%ZMM1,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VPERMT2PD %ZMM19,%ZMM2,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VMOVUPD (%R15,%RCX,1),%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM19,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPERMT2PD %ZMM22,%ZMM0,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VMOVAPD %ZMM19,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPERMT2PD %ZMM22,%ZMM1,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VPERMT2PD %ZMM22,%ZMM2,%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VFMADD231PD %YMM20,%YMM17,%YMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM21,%YMM17,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM18,%YMM17,%YMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VINSERTF64X4 $0x1,%YMM24,%ZMM23,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMOVAPD %ZMM17,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPERMT2PD %ZMM19,%ZMM3,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VPERMT2PD %ZMM19,%ZMM4,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VMOVUPD %ZMM17,(%R15,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %YMM18,0x40(%R15,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 1 |
ADD $0x60,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD $0x4,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 212ac0 <.omp_outlined..244+0x3a0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | .omp_outlined..244 |
Source file and lines | timestep.c:74-78 |
Module | exec |
nb instructions | 27 |
nb uops | 27 |
loop length | 168 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 8 |
used zmm registers | 13 |
nb stack references | 0 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 2.33 | 2.33 | 2.33 | 3.00 | 8.50 | 8.50 | 0.00 | 1.50 | 1.50 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 3.00 | 3.00 | 3.00 | 3.00 | 8.50 | 8.50 | 0.00 | 1.50 | 1.50 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 4.50 |
Dispatch | 8.50 |
Data deps. | 1.00 |
Overall L1 | 8.50 |
all | 95% |
load | 80% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 93% |
all | 81% |
load | 62% |
store | 75% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 90% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD (%R12,%RCX,1),%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD 0x40(%R12,%RCX,1),%YMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVUPD 0x40(%R15,%RCX,1),%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VBROADCASTSD (%RBX),%YMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VMOVAPD %ZMM18,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVAPD %ZMM18,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPERMT2PD %ZMM19,%ZMM0,%ZMM20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VPERMT2PD %ZMM19,%ZMM1,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VPERMT2PD %ZMM19,%ZMM2,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VMOVUPD (%R15,%RCX,1),%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVAPD %ZMM19,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPERMT2PD %ZMM22,%ZMM0,%ZMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VMOVAPD %ZMM19,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPERMT2PD %ZMM22,%ZMM1,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VPERMT2PD %ZMM22,%ZMM2,%ZMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VFMADD231PD %YMM20,%YMM17,%YMM23 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM21,%YMM17,%YMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VFMADD231PD %YMM18,%YMM17,%YMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VINSERTF64X4 $0x1,%YMM24,%ZMM23,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 1 |
VMOVAPD %ZMM17,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VPERMT2PD %ZMM19,%ZMM3,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VPERMT2PD %ZMM19,%ZMM4,%ZMM17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 5 | 1 |
VMOVUPD %ZMM17,(%R15,%RCX,1) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %YMM18,0x40(%R15,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 4 | 1 |
ADD $0x60,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
ADD $0x4,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 212ac0 <.omp_outlined..244+0x3a0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |