OV - - Loop 69

	Loop Id: 69	Module: exec	Source: haloExchange.c:380-389	Coverage: 0.09%

0x40b230 MOV	(%R11,%R12,4),%ESI    [6]

0x40b234 MOV	%ESI,(%R13)    [4]

0x40b238 MOV	(%RBX,%R12,4),%ESI    [5]

0x40b23c MOV	%ESI,0x4(%R13)    [4]

0x40b240 MOVUPD	-0x10(%R14,%RDX,4),%XMM2    [2]

0x40b247 ADDPD	%XMM0,%XMM2

0x40b24b MOVUPD	%XMM2,0x8(%R13)    [4]

0x40b251 MOVSD	(%R14,%RDX,4),%XMM2    [2]

0x40b257 ADDSD	%XMM1,%XMM2

0x40b25b MOVSD	%XMM2,0x18(%R13)    [4]

0x40b261 MOVUPS	-0x10(%R15,%RDX,4),%XMM2    [1]

0x40b267 MOVUPS	%XMM2,0x20(%R13)    [4]

0x40b26c MOVSD	(%R15,%RDX,4),%XMM2    [1]

0x40b272 MOVSD	%XMM2,0x30(%R13)    [4]

0x40b278 INC	%R12

0x40b27b MOVSXD	(%R8,%R10,4),%RSI    [3]

0x40b27f ADD	%RCX,%RSI

0x40b282 ADD	$0x38,%R13

0x40b286 INC	%EDI

0x40b288 ADD	$0x6,%RDX

0x40b28c CMP	%RSI,%R12

0x40b28f JL	40b230

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 380 - 389

--------------------------------------------------------------------------------

380:       for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii)

381:       {

382:          buf[nBuf].gid  = s->atoms->gid[ii];

383:          buf[nBuf].type = s->atoms->iSpecies[ii];

384:          buf[nBuf].rx = s->atoms->r[ii][0] + shift[0];

385:          buf[nBuf].ry = s->atoms->r[ii][1] + shift[1];

386:          buf[nBuf].rz = s->atoms->r[ii][2] + shift[2];

387:          buf[nBuf].px = s->atoms->p[ii][0];

388:          buf[nBuf].py = s->atoms->p[ii][1];

389:          buf[nBuf].pz = s->atoms->p[ii][2];

Path /

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.24
CQA speedup if fully vectorized	4.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P5, P6, P7,
Function	loadAtomsBuffer.A
Source	haloExchange.c:380-389
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.96
Front-end cycles	3.50
DIV/SQRT cycles	1.75
P0 cycles	1.75
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	0.50
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	21.00
Nb loads	7.00
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.69
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.77
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	56.00
Stride 0	1.00
Stride 1	2.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	38.46
Vectorization ratio load	50.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	33.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	15.87
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	14.58
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	14.58
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.24
CQA speedup if fully vectorized	4.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.24
Bottlenecks	P5, P6, P7,
Function	loadAtomsBuffer.A
Source	haloExchange.c:380-389
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.96
Front-end cycles	3.50
DIV/SQRT cycles	1.75
P0 cycles	1.75
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	0.50
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	21.00
Nb loads	7.00
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.69
Nb FLOP add-sub	3.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.77
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	56.00
Stride 0	1.00
Stride 1	2.00
Stride n	3.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	38.46
Vectorization ratio load	50.00
Vectorization ratio store	33.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	33.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	15.87
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	14.58
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	14.58
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	loadAtomsBuffer.A
Source file and lines	haloExchange.c:380-389
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:380-389.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.33 to 3.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.33 to 0.96 cycles (4.52x speedup).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 4.33 to 3.50 cycles (1.24x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences
MOVUPS: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	22
nb uops	21
loop length	97
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	0.50	4.33	4.33	4.33	0.00	0.00	1.00	1.00	2.00	2.00
cycles	1.75	1.75	1.50	1.50	0.50	4.33	4.33	4.33	0.00	0.00	1.00	1.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Dispatch	4.33
Data deps.	1.00
Overall L1	4.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	50%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	18%
load	18%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	18%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

14% of peak load performance is reached (13.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (12.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b230

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV (%R11,%R12,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %ESI,(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%RBX,%R12,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %ESI,0x4(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVUPD -0x10(%R14,%RDX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM2,0x8(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVSD (%R14,%RDX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADDSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM2,0x18(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
MOVUPS -0x10(%R15,%RDX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVUPS %XMM2,0x20(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVSD (%R15,%RDX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOVSD %XMM2,0x30(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSXD (%R8,%R10,4),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x38,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x6,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RSI,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JL 40b230 <loadAtomsBuffer.A+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

Function	loadAtomsBuffer.A
Source file and lines	haloExchange.c:380-389
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.33 to 3.00 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 4.33 to 3.50 cycles (1.24x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences
MOVUPS: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary loop is loading 60 bytes (7 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	22
nb uops	21
loop length	97
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	0.50	4.33	4.33	4.33	0.00	0.00	1.00	1.00	2.00	2.00
cycles	1.75	1.75	1.50	1.50	0.50	4.33	4.33	4.33	0.00	0.00	1.00	1.00	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Dispatch	4.33
Data deps.	1.00
Overall L1	4.33

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	50%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	18%
load	18%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	18%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

14% of peak load performance is reached (13.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (12.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b230

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV (%R11,%R12,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %ESI,(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOV (%RBX,%R12,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.33
MOV %ESI,0x4(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	4	0.50
MOVUPD -0x10(%R14,%RDX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM2,0x8(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVSD (%R14,%RDX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
ADDSD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM2,0x18(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
MOVUPS -0x10(%R15,%RDX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	3	0.50
MOVUPS %XMM2,0x20(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	4	1
MOVSD (%R15,%RDX,4),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50
MOVSD %XMM2,0x30(%R13)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	1	1
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
MOVSXD (%R8,%R10,4),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	1	0.33
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x38,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
INC %EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
ADD $0x6,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
CMP %RSI,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	1	0.25
JL 40b230 <loadAtomsBuffer.A+0xc0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.79	0.02	0.75	0.03	0.68	0.04	0.84	0.01	0.84	0.01	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.3	0.09
2x2	2	0.79	1.59	2	0.36	0.11
2x4	2	0.75	3	4	0.4	0.11
2x8	2	0.68	5.4	8	0.38	0.11
2x16	2	0.84	13.5	16	0.38	0.09
2x32	2	0.84	27	32	0.4	0.06
2x64	2	1	1	64	0.32	0.04
2x96	2	1	1	96	0.34	0.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency