OV - - Loop 159

	Loop Id: 159	Module: exec	Source: timestep.c:110-116	Coverage: 0.06%

0x418620 MOVUPD	0x40(%R14),%XMM7    [6]

0x418626 MOVUPD	0x50(%R14),%XMM12    [6]

0x41862c MOVUPD	(%R14),%XMM11    [6]

0x418631 MOVUPD	0x10(%R14),%XMM8    [6]

0x418637 MOVDQU	(%R15,%RDX,4),%XMM9    [1]

0x41863d MOVUPD	0x20(%R14),%XMM13    [6]

0x418643 MOVUPD	0x30(%R14),%XMM10    [6]

0x418649 MULPD	%XMM13,%XMM13

0x41864e MULPD	%XMM12,%XMM12

0x418653 MULPD	%XMM11,%XMM11

0x418658 MULPD	%XMM8,%XMM8

0x41865d MULPD	%XMM7,%XMM7

0x418661 MULPD	%XMM10,%XMM10

0x418666 MOVAPD	%XMM7,%XMM14

0x41866b MOVSD	%XMM10,%XMM14

0x418670 MOVAPD	%XMM8,%XMM15

0x418675 MOVSD	%XMM11,%XMM15

0x41867a SHUFPD	$0x1,%XMM12,%XMM10

0x418680 SHUFPD	$0x2,%XMM13,%XMM8

0x418686 SHUFPD	$0x2,%XMM12,%XMM7

0x41868c SHUFPD	$0x1,%XMM13,%XMM11

0x418692 XORPD	%XMM12,%XMM12

0x418697 PCMPGTD	%XMM9,%XMM12

0x41869c PSHUFD	$-0x12,%XMM9,%XMM13

0x4186a2 ADDPD	%XMM14,%XMM10

0x4186a7 PUNPCKLDQ	%XMM12,%XMM9

0x4186ac PXOR	%XMM12,%XMM12

0x4186b1 PCMPGTD	%XMM13,%XMM12

0x4186b6 ADDPD	%XMM15,%XMM11

0x4186bb PUNPCKLDQ	%XMM12,%XMM13

0x4186c0 PSLLQ	$0x4,%XMM13

0x4186c6 PADDQ	%XMM4,%XMM13

0x4186cb ADDPD	%XMM11,%XMM8

0x4186d0 PSLLQ	$0x4,%XMM9

0x4186d6 PADDQ	%XMM4,%XMM9

0x4186db MOVQ	%XMM9,%RAX

0x4186e0 ADDPD	%XMM10,%XMM7

0x4186e5 PSHUFD	$-0x12,%XMM9,%XMM9

0x4186eb MOVQ	%XMM9,%RCX

0x4186f0 MOVQ	%XMM13,%R12

0x4186f5 MULPD	%XMM2,%XMM8

0x4186fa PSHUFD	$-0x12,%XMM13,%XMM9

0x418700 MOVQ	%XMM9,%R10

0x418705 MOVSD	(%RAX),%XMM9    [4]

0x41870a MULPD	%XMM2,%XMM7

0x41870e MOVHPD	(%RCX),%XMM9    [3]

0x418713 MOVSD	(%R12),%XMM10    [5]

0x418719 DIVPD	%XMM9,%XMM8

0x41871e MOVHPD	(%R10),%XMM10    [2]

0x418723 DIVPD	%XMM10,%XMM7

0x418728 ADDPD	%XMM8,%XMM5

0x41872d ADDPD	%XMM7,%XMM6

0x418731 ADD	$0x60,%R14

0x418735 ADD	$0x4,%RDX

0x418739 CMP	%EBX,%EDX

0x41873b JLE	418620

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116

--------------------------------------------------------------------------------

110:       for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++)

111:       {

112:          int iSpecies = s->atoms->iSpecies[iOff];

113:          real_t invMass = 0.5/s->species[iSpecies].mass;

114:          kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] +

115:          s->atoms->p[iOff][1] * s->atoms->p[iOff][1] +

116:          s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.48
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P8, P9,
Function	kineticEnergy.extracted
Source	timestep.c:110-116
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	5.00
Front-end cycles	9.17
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.67
P7 cycles	8.75
P8 cycles	8.75
P9 cycles	8.75
P10 cycles	8.75
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	10.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	55.00
Nb loads	11.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.20
Nb FLOP add-sub	12.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.40
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	80.77
Vectorization ratio load	63.64
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	73.91
Vector-efficiency ratio all	22.12
Vector-efficiency ratio load	20.45
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	20.65

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.48
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P8, P9,
Function	kineticEnergy.extracted
Source	timestep.c:110-116
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	10.00
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	5.00
Front-end cycles	9.17
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	3.67
P5 cycles	3.67
P6 cycles	3.67
P7 cycles	8.75
P8 cycles	8.75
P9 cycles	8.75
P10 cycles	8.75
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	10.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	55.00
Nb loads	11.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.20
Nb FLOP add-sub	12.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.40
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	80.77
Vectorization ratio load	63.64
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	73.91
Vector-efficiency ratio all	22.12
Vector-efficiency ratio load	20.45
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	20.65

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	kineticEnergy.extracted
Source file and lines	timestep.c:110-116
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c:110-116.

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 10.00 to 5.00 cycles (2.00x speedup).

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

63% of SSE/AVX loads are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.00 to 9.17 cycles (1.09x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.00 to 9.17 cycles (1.09x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 2 occurrences
MOVUPD: 6 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

12: addition or subtraction
16: multiply
4: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	56
nb uops	55
loop length	289
used x86 registers	8
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.75

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	3.67	3.67	3.67	8.75	8.75	8.75	8.75	2.00	2.00
cycles	0.75	0.75	0.50	0.50	0.50	3.67	3.67	3.67	8.75	8.75	8.75	8.75	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	10.00
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	9.17
Dispatch	8.75
DIV/SQRT	10.00
Data deps.	3.00
Overall L1	10.00

Vectorization ratios

INT

all	76%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	71%

all	82%
load	60%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	77%

INT+FP

all	80%
load	63%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	73%

Vector efficiency ratios

INT

all	20%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	22%

INT+FP

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

15% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418620

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVUPD 0x40(%R14),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x50(%R14),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD (%R14),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x10(%R14),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVDQU (%R15,%RDX,4),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x20(%R14),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x30(%R14),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM7,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSD %XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MOVAPD %XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSD %XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
SHUFPD $0x1,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPD $0x2,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPD $0x2,%XMM12,%XMM7	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPD $0x1,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
XORPD %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PCMPGTD %XMM9,%XMM12	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PSHUFD $-0x12,%XMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
ADDPD %XMM14,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PUNPCKLDQ %XMM12,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
PXOR %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
PCMPGTD %XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
ADDPD %XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PUNPCKLDQ %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
PSLLQ $0x4,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
PADDQ %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
ADDPD %XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PSLLQ $0x4,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
PADDQ %XMM4,%XMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MOVQ %XMM9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADDPD %XMM10,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PSHUFD $-0x12,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVQ %XMM9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVQ %XMM13,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MULPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
PSHUFD $-0x12,%XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVQ %XMM9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSD (%RAX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVHPD (%RCX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD (%R12),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
DIVPD %XMM9,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
MOVHPD (%R10),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
DIVPD %XMM10,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
ADDPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM7,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD $0x60,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EBX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 418620 <kineticEnergy.extracted+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	kineticEnergy.extracted
Source file and lines	timestep.c:110-116
Module	exec

gain
potential
hint
expert

Vectorization

Details

80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

63% of SSE/AVX loads are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.00 to 9.17 cycles (1.09x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

MOVHPD: 2 occurrences
MOVUPD: 6 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

16 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

12: addition or subtraction
16: multiply
4: divide

The binary loop is loading 144 bytes (18 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	56
nb uops	55
loop length	289
used x86 registers	8
used mmx registers	0
used xmm registers	13
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.75

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	3.67	3.67	3.67	8.75	8.75	8.75	8.75	2.00	2.00
cycles	0.75	0.75	0.50	0.50	0.50	3.67	3.67	3.67	8.75	8.75	8.75	8.75	2.00	2.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	10.00
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	9.17
Dispatch	8.75
DIV/SQRT	10.00
Data deps.	3.00
Overall L1	10.00

Vectorization ratios

INT

all	76%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	71%

all	82%
load	60%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	77%

INT+FP

all	80%
load	63%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	73%

Vector efficiency ratios

INT

all	20%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	22%

INT+FP

all	22%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.00 cycles. At this rate:

15% of peak load performance is reached (14.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 418620

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOVUPD 0x40(%R14),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x50(%R14),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD (%R14),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x10(%R14),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVDQU (%R15,%RDX,4),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x20(%R14),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x30(%R14),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MULPD %XMM13,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM7,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULPD %XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM7,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSD %XMM10,%XMM14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MOVAPD %XMM8,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVSD %XMM11,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
SHUFPD $0x1,%XMM12,%XMM10	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPD $0x2,%XMM13,%XMM8	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPD $0x2,%XMM12,%XMM7	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
SHUFPD $0x1,%XMM13,%XMM11	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
XORPD %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PCMPGTD %XMM9,%XMM12	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PSHUFD $-0x12,%XMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
ADDPD %XMM14,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PUNPCKLDQ %XMM12,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
PXOR %XMM12,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
PCMPGTD %XMM13,%XMM12	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
ADDPD %XMM15,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PUNPCKLDQ %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
PSLLQ $0x4,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
PADDQ %XMM4,%XMM13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
ADDPD %XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PSLLQ $0x4,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
PADDQ %XMM4,%XMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
MOVQ %XMM9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
ADDPD %XMM10,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
PSHUFD $-0x12,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVQ %XMM9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVQ %XMM13,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MULPD %XMM2,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
PSHUFD $-0x12,%XMM13,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVQ %XMM9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
MOVSD (%RAX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MULPD %XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVHPD (%RCX),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
MOVSD (%R12),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
DIVPD %XMM9,%XMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
MOVHPD (%R10),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	1	0.50
DIVPD %XMM10,%XMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
ADDPD %XMM8,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADDPD %XMM7,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD $0x60,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD $0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %EBX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 418620 <kineticEnergy.extracted+0x1b0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1.06	-0	1.19	0	1.19	0	1.19	0	1	0	0.3	0.04	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.19	0.06
2x2	4	1.06	2.11	2	0.1	0.06
2x4	8	1.19	4.75	4	0.06	0.05
2x8	16	1.19	9.5	8	0.03	0.04
2x16	32	1.19	19	16	0.01	0.03
2x32	64	1	1	32	0.01	0.02
2x64	127	0.3	19	64	0.01	0.05
2x96	177	1	1	96	0	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency