OV - - Loop 145

	Loop Id: 145	Module: exec	Source: ljForce.c:191-216 [...]	Coverage: 93.14%

0x4110b0 ADD	$0x18,%RSI

0x4110b4 DEC	%R12

0x4110b7 JE	411090

0x4110b9 MOVUPD	(%R15),%XMM11    [1]

0x4110be MOVUPD	-0x10(%RSI),%XMM12    [4]

0x4110c4 SUBPD	%XMM12,%XMM11

0x4110c9 MOVAPD	%XMM11,%XMM12

0x4110ce MULPD	%XMM11,%XMM12

0x4110d3 MOVAPD	%XMM12,%XMM13

0x4110d8 UNPCKHPD	%XMM12,%XMM13

0x4110dd ADDSD	%XMM12,%XMM13

0x4110e2 MOVSD	0x10(%R15),%XMM12    [1]

0x4110e8 SUBSD	(%RSI),%XMM12    [4]

0x4110ed MOVAPD	%XMM12,%XMM14

0x4110f2 MULSD	%XMM12,%XMM14

0x4110f7 ADDSD	%XMM13,%XMM14

0x4110fc UCOMISD	%XMM2,%XMM14

0x411101 JA	4110b0

0x411103 UCOMISD	%XMM4,%XMM14

0x411108 JBE	4110b0

0x41110a MOVAPD	%XMM6,%XMM13

0x41110f DIVSD	%XMM14,%XMM13

0x411114 MOVAPD	%XMM13,%XMM14

0x411119 MULSD	%XMM13,%XMM14

0x41111e MOVDQA	%XMM1,%XMM15

0x411123 MULSD	%XMM13,%XMM15

0x411128 MULSD	%XMM14,%XMM15

0x41112d MOVAPD	%XMM15,%XMM14

0x411132 ADDSD	%XMM7,%XMM14

0x411137 MULSD	%XMM15,%XMM14

0x41113c SUBSD	0x10(%RBP),%XMM14    [6]

0x411142 MULSD	%XMM8,%XMM14

0x411147 MOV	0x30(%R13),%R10    [3]

0x41114b MOVSD	(%R10,%RAX,8),%XMM0    [5]

0x411151 ADDSD	%XMM14,%XMM0

0x411156 MOVSD	%XMM0,(%R10,%RAX,8)    [5]

0x41115c MULSD	%XMM3,%XMM13

0x411161 MULSD	%XMM15,%XMM13

0x411166 MULSD	%XMM9,%XMM15

0x41116b ADDSD	%XMM10,%XMM15

0x411170 MULSD	%XMM15,%XMM13

0x411175 MOV	0x28(%R13),%R10    [3]

0x411179 MOVAPD	%XMM13,%XMM0

0x41117e UNPCKLPD	%XMM13,%XMM0

0x411183 MULPD	%XMM11,%XMM0

0x411188 MOVUPD	(%R10,%RDI,8),%XMM11    [2]

0x41118e ADDPD	%XMM0,%XMM11

0x411193 MOVUPD	%XMM11,(%R10,%RDI,8)    [2]

0x411199 MULSD	%XMM12,%XMM13

0x41119e ADDSD	0x10(%R10,%RDI,8),%XMM13    [2]

0x4111a5 MOVSD	%XMM13,0x10(%R10,%RDI,8)    [2]

0x4111ac ADDSD	%XMM14,%XMM5

0x4111b1 JMP	4110b0

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 191 - 216

--------------------------------------------------------------------------------

191:             for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++)

[...]

197:                   dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m];

198:                   r2+=dr[m]*dr[m];

199:                }

200:

201:                if ( r2 <= rCut2 && r2 > 0.0)

202:                {

203:

204:                   // Important note:

205:                   // from this point on r actually refers to 1.0/r

206:                   r2 = 1.0/r2;

207:                   real_t r6 = s6 * (r2*r2*r2);

208:                   real_t eLocal = r6 * (r6 - 1.0) - eShift;

209:                   s->atoms->U[iOff] += 0.5*eLocal;

210:                   ePot += 0.5*eLocal;

211:

212:                   // different formulation to avoid sqrt computation

213:                   real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0);

214:                   for (int m=0; m<3; m++)

215:                   {

216:                      s->atoms->f[iOff][m] -= dr[m]*fr;

Path /

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	2.31
CQA speedup if fully vectorized	4.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks
Function	ljForce.extracted
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.33
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	2.31
CQA cycles if fully vectorized	1.16
Front-end cycles	5.33
DIV/SQRT cycles	1.50
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	0.50
P3 cycles	1.50
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	2.33
P7 cycles	3.00
P8 cycles	3.78
P9 cycles	4.33
P10 cycles	4.22
P11 cycles	1.33
P12 cycles	1.33
P13 cycles	1.67
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.33
Nb uops	32.00
Nb loads	6.00
Nb stores	1.00
Nb stack references	0.33
FLOP/cycle	2.81
Nb FLOP add-sub	7.67
Nb FLOP mul	7.00
Nb FLOP fma	0.00
Nb FLOP div	0.33
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.36
Bytes prefetched	0.00
Bytes loaded	66.67
Bytes stored	10.67
Stride 0	1.67
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.67
Vectorization ratio all	44.07
Vectorization ratio load	45.83
Vectorization ratio store	33.33
Vectorization ratio mul	38.46
Vectorization ratio add_sub	22.73
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	58.89
Vector-efficiency ratio all	18.01
Vector-efficiency ratio load	18.23
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	17.31
Vector-efficiency ratio add_sub	15.34
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	19.86

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	2.17
CQA speedup if fully vectorized	4.61
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	ljForce.extracted
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.17
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.46
CQA cycles if fully vectorized	0.69
Front-end cycles	3.17
DIV/SQRT cycles	1.00
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	0.50
P3 cycles	1.00
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.00
P8 cycles	2.00
P9 cycles	2.50
P10 cycles	2.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	19.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.53
Nb FLOP add-sub	5.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.16
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	50.00
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	50.00
Vectorization ratio add_sub	25.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	60.00
Vector-efficiency ratio all	18.75
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	15.63
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	20.00

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	2.39
CQA speedup if fully vectorized	4.49
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	micro-operation queue,
Function	ljForce.extracted
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.17
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	2.04
Front-end cycles	9.17
DIV/SQRT cycles	2.00
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	0.50
P3 cycles	2.00
P4 cycles	4.33
P5 cycles	4.33
P6 cycles	4.33
P7 cycles	7.00
P8 cycles	7.33
P9 cycles	7.50
P10 cycles	7.17
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	5.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	55.00
Nb loads	10.00
Nb stores	3.00
Nb stack references	1.00
FLOP/cycle	3.16
Nb FLOP add-sub	13.00
Nb FLOP mul	15.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.84
Bytes prefetched	0.00
Bytes loaded	104.00
Bytes stored	32.00
Stride 0	3.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	35.56
Vectorization ratio load	37.50
Vectorization ratio store	33.33
Vectorization ratio mul	15.38
Vectorization ratio add_sub	18.18
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	66.67
Vector-efficiency ratio all	16.94
Vector-efficiency ratio load	17.19
Vector-efficiency ratio store	16.67
Vector-efficiency ratio mul	14.42
Vector-efficiency ratio add_sub	14.77
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	20.83

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	2.26
CQA speedup if fully vectorized	4.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	micro-operation queue,
Function	ljForce.extracted
Source	ljForce.c:191-191,ljForce.c:197-216
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.67
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	1.63
CQA cycles if fully vectorized	0.75
Front-end cycles	3.67
DIV/SQRT cycles	1.50
P0 cycles	0.75
P1 cycles	0.75
P2 cycles	0.50
P3 cycles	1.50
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.33
P7 cycles	1.00
P8 cycles	2.00
P9 cycles	3.00
P10 cycles	3.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	22.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.18
Nb FLOP add-sub	5.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.09
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	46.67
Vectorization ratio load	50.00
Vectorization ratio store	NA
Vectorization ratio mul	50.00
Vectorization ratio add_sub	25.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	18.33
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	15.63
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce.extracted
Source file and lines	ljForce.c:191-216
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:191,197-216.

The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 5.33 to 1.16 cycles (4.60x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

45% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
22% of SSE/AVX addition or subtraction instructions are used in vector version.
38% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
58% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 1.67 occurrences

Type of elements and instruction set

11 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15 FP arithmetical operations:

7.67: addition or subtraction
7: multiply
0.33: divide

The binary loop is loading 66 bytes (8 double precision FP elements). The binary loop is storing 10 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	30.33
nb uops	32
loop length	145
used x86 registers	4.67
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	0.33
ADD-SUB / MUL ratio	1.62

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	5.33 cycles
front end	5.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	0.75	0.75	0.50	1.50	2.33	2.33	2.33	3.00	3.78	4.33	4.22	1.33	1.33
cycles	1.50	0.75	0.75	0.50	1.50	2.33	2.33	2.33	3.00	3.78	4.33	4.22	1.33	1.33

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	1.67
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	5.33
Dispatch	4.33
DIV/SQRT	1.67
Data deps.	3.00
Overall L1	5.33

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	43%
load	45%
store	33%
mul	38%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	57%

INT+FP

all	44%
load	45%
store	33%
mul	38%
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	58%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	17%
load	18%
store	16%
mul	17%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	19%

INT+FP

all	18%
load	18%
store	16%
mul	17%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.33 cycles. At this rate:

13% of peak load performance is reached (13.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.16 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Function	ljForce.extracted
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.17 to 3.00 cycles (1.06x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 3.17 to 0.69 cycles (4.61x speedup).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

5: addition or subtraction
3: multiply

The binary loop is loading 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	18
nb uops	19
loop length	83
used x86 registers	3
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.17 cycles
front end	3.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	0.75	0.75	0.50	1.00	1.33	1.33	1.33	1.00	2.00	2.50	2.50	0.50	0.50
cycles	1.00	0.75	0.75	0.50	1.00	1.33	1.33	1.33	1.00	2.00	2.50	2.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	3.17
Dispatch	2.50
Data deps.	3.00
Overall L1	3.17

Vectorization ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

Vector efficiency ratios

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	18%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.17 cycles. At this rate:

15% of peak load performance is reached (15.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.17 to 2.50 cycles (1.27x speedup).

ASM code

In the binary file, the address of the loop is: 4110b9

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
DEC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 411090 <ljForce.extracted+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVUPD (%R15),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD -0x10(%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPD %XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
ADDSD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD 0x10(%R15),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SUBSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UCOMISD %XMM2,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JA 4110b0 <ljForce.extracted+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	ljForce.extracted
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.17 to 8.50 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 9.17 to 2.04 cycles (4.49x speedup).

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

37% of SSE/AVX loads are used in vector version.
33% of SSE/AVX stores are used in vector version.
18% of SSE/AVX addition or subtraction instructions are used in vector version.
15% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
66% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

23 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 29 FP arithmetical operations:

13: addition or subtraction
15: multiply
1: divide

The binary loop is loading 104 bytes (13 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	53
nb uops	55
loop length	262
used x86 registers	8
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	0.85

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	0.75	0.75	0.50	2.00	4.33	4.33	4.33	7.00	7.33	7.50	7.17	2.50	2.50
cycles	2.00	0.75	0.75	0.50	2.00	4.33	4.33	4.33	7.00	7.33	7.50	7.17	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	5.00
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	9.17
Dispatch	7.50
DIV/SQRT	5.00
Data deps.	3.00
Overall L1	9.17

Vectorization ratios

INT

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	34%
load	37%
store	33%
mul	15%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	63%

INT+FP

all	35%
load	37%
store	33%
mul	15%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	66%

Vector efficiency ratios

INT

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	16%
load	17%
store	16%
mul	14%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

INT+FP

all	16%
load	17%
store	16%
mul	14%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.17 cycles. At this rate:

11% of peak load performance is reached (11.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.49 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4110b9

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
DEC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 411090 <ljForce.extracted+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVUPD (%R15),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD -0x10(%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPD %XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
ADDSD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD 0x10(%R15),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SUBSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UCOMISD %XMM2,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JA 4110b0 <ljForce.extracted+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
UCOMISD %XMM4,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 4110b0 <ljForce.extracted+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVAPD %XMM6,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
DIVSD %XMM14,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
MOVAPD %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVDQA %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD %XMM13,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULSD %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADDSD %XMM7,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULSD %XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
SUBSD 0x10(%RBP),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULSD %XMM8,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV 0x30(%R13),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVSD (%R10,%RAX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADDSD %XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM0,(%R10,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MULSD %XMM3,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULSD %XMM15,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MULSD %XMM9,%XMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD %XMM10,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULSD %XMM15,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOV 0x28(%R13),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVAPD %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKLPD %XMM13,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
MULPD %XMM11,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVUPD (%R10,%RDI,8),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADDPD %XMM0,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVUPD %XMM11,(%R10,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MULSD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD 0x10(%R10,%RDI,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVSD %XMM13,0x10(%R10,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
ADDSD %XMM14,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
JMP 4110b0 <ljForce.extracted+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	ljForce.extracted
Source file and lines	ljForce.c:191-216
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

46% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 2 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 2 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

5: addition or subtraction
3: multiply

The binary loop is loading 48 bytes (6 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	22
loop length	90
used x86 registers	3
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	0.75	0.75	0.50	1.50	1.33	1.33	1.33	1.00	2.00	3.00	3.00	1.00	1.00
cycles	1.50	0.75	0.75	0.50	1.50	1.33	1.33	1.33	1.00	2.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	3.67
Dispatch	3.00
Data deps.	3.00
Overall L1	3.67

Vectorization ratios

all	46%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	18%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.67 cycles. At this rate:

13% of peak load performance is reached (13.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4110b9

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ADD $0x18,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
DEC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 411090 <ljForce.extracted+0x260>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVUPD (%R15),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD -0x10(%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
SUBPD %XMM12,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULPD %XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
UNPCKHPD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
ADDSD %XMM12,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVSD 0x10(%R15),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
SUBSD (%RSI),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MOVAPD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MULSD %XMM12,%XMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ADDSD %XMM13,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
UCOMISD %XMM2,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JA 4110b0 <ljForce.extracted+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
UCOMISD %XMM4,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1
JBE 4110b0 <ljForce.extracted+0x280>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0.08	0.99	0.5	0.99	0.73	0.98	1.18	0.97	1.3	0.97	1.11	0.88	3.44

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	270.53	93.14
2x2	4	1	2	2	135.18	90.16
2x4	8	0.99	3.98	4	68.29	85.25
2x8	16	0.99	7.93	8	34.03	78.92
2x16	32	0.98	15.72	16	17.33	68.12
2x32	64	0.97	31.16	32	9.72	49.41
2x64	128	0.97	62.03	64	5.23	35.94
2x96	192	0.88	84.51	96	3.86	28.74

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code