OV - - Loop 131

	Loop Id: 131	Module: exec	Source: linkCells.c:295-378 [...]	Coverage: 0.83%

0x40fa20 INC	%R12D

0x40fa23 MOV	0x78(%R14),%RCX    [1]

0x40fa27 CMP	(%RCX,%R15,4),%R12D    [2]

0x40fa2b JGE	40f9f0

0x40fa2d MOV	0x18(%RBX),%RAX    [4]

0x40fa31 LEA	(%R12,%R13,1),%ECX

0x40fa35 MOVSXD	%ECX,%RCX

0x40fa38 LEA	(%RCX,%RCX,2),%RCX

0x40fa3c MOVSD	(%RAX,%RCX,8),%XMM0    [3]

0x40fa41 MOVSD	%XMM0,-0x68(%RBP)    [5]

0x40fa46 MOVUPD	0x8(%RAX,%RCX,8),%XMM2    [3]

0x40fa4c MOVUPD	0x20(%R14),%XMM0    [1]

0x40fa52 MOVUPD	0x68(%R14),%XMM1    [1]

0x40fa58 MOVAPD	%XMM2,-0x60(%RBP)    [5]

0x40fa5d SUBPD	%XMM0,%XMM2

0x40fa61 MULPD	%XMM1,%XMM2

0x40fa65 MOVAPD	%XMM2,-0x40(%RBP)    [5]

0x40fa6a MOVAPD	%XMM2,%XMM0

0x40fa6e CALL	418d00 <floor>

0x40fa73 MOVAPD	%XMM0,-0x50(%RBP)    [5]

0x40fa78 MOVAPD	-0x40(%RBP),%XMM0    [5]

0x40fa7d UNPCKHPD	%XMM0,%XMM0

0x40fa81 CALL	418d00 <floor>

0x40fa86 MOVSD	-0x68(%RBP),%XMM1    [5]

0x40fa8b UCOMISD	0x30(%R14),%XMM1    [1]

0x40fa91 JAE	40fad0

0x40fa93 MOVAPD	%XMM0,-0x40(%RBP)    [5]

0x40fa98 SUBSD	0x18(%R14),%XMM1    [1]

0x40fa9e MULSD	0x60(%R14),%XMM1    [1]

0x40faa4 MOVAPD	%XMM1,%XMM0

0x40faa8 CALL	418d00 <floor>

0x40faad CVTTSD2SI	%XMM0,%ESI

0x40fab1 MOV	(%R14),%EAX    [1]

0x40fab4 CMP	%ESI,%EAX

0x40fab6 JNE	40fabc

0x40fab8 DEC	%EAX

0x40faba MOV	%EAX,%ESI

0x40fabc MOVAPD	-0x60(%RBP),%XMM2    [5]

0x40fac1 MOVAPD	-0x50(%RBP),%XMM1    [5]

0x40fac6 MOVAPD	-0x40(%RBP),%XMM0    [5]

0x40facb JMP	40fadd

0x40fad0 MOV	(%R14),%ESI    [1]

0x40fad3 MOVAPD	-0x60(%RBP),%XMM2    [5]

0x40fad8 MOVAPD	-0x50(%RBP),%XMM1    [5]

0x40fadd UNPCKLPD	%XMM0,%XMM1

0x40fae1 CVTTPD2DQ	%XMM1,%XMM0

0x40fae5 MOV	0x4(%R14),%RCX    [1]

0x40fae9 MOVQ	%RCX,%XMM1

0x40faee PCMPEQD	%XMM0,%XMM1

0x40faf2 PSHUFD	$0x50,%XMM1,%XMM1

0x40faf7 MOVMSKPD	%XMM1,%EAX

0x40fafb TEST	$0x1,%AL

0x40fafd JNE	40fb10

0x40faff MOVD	%XMM0,%EDX

0x40fb03 JMP	40fb13

0x40fb10 LEA	-0x1(%RCX),%EDX

0x40fb13 UCOMISD	0x38(%R14),%XMM2    [1]

0x40fb19 CMOVAE	%ECX,%EDX

0x40fb1c SHR	$0x20,%RCX

0x40fb20 TEST	$0x2,%AL

0x40fb22 JNE	40fb30

0x40fb24 PSHUFD	$0x55,%XMM0,%XMM0

0x40fb29 MOVD	%XMM0,%EAX

0x40fb2d JMP	40fb33

0x40fb30 LEA	-0x1(%RCX),%EAX

0x40fb33 UNPCKHPD	%XMM2,%XMM2

0x40fb37 UCOMISD	0x40(%R14),%XMM2    [1]

0x40fb3d CMOVB	%EAX,%ECX

0x40fb40 MOV	%R14,%RDI

0x40fb43 CALL	40f540 <getBoxFromTuple.A>

0x40fb48 MOV	%EAX,%ECX

0x40fb4a CMP	%RCX,%R15

0x40fb4d JE	40fa20

0x40fb53 MOV	%R14,%RDI

0x40fb56 MOV	%RBX,%RSI

0x40fb59 MOV	%R12D,%EDX

0x40fb5c MOV	%R15D,%ECX

0x40fb5f MOV	%EAX,%R8D

0x40fb62 CALL	40f810 <moveAtom.A>

0x40fb67 JMP	40fa23

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 295 - 378

--------------------------------------------------------------------------------

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

378:    return getBoxFromTuple(boxes, ix, iy, iz);

Path /

Metric	Value
CQA speedup if no scalar integer	1.70
CQA speedup if FP arith vectorized	1.84
CQA speedup if fully vectorized	5.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue,
Function	updateLinkCells.A
Source	linkCells.c:295-301,linkCells.c:352-365,linkCells.c:371-371,linkCells.c:378-378
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	8.17
CQA cycles if fully vectorized	2.94
Front-end cycles	15.00
DIV/SQRT cycles	7.50
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	7.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	3.00
P8 cycles	4.33
P9 cycles	4.50
P10 cycles	4.17
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	90.00
Nb loads	22.00
Nb stores	5.00
Nb stack references	4.00
FLOP/cycle	0.40
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.53
Bytes prefetched	0.00
Bytes loaded	236.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	46.81
Vectorization ratio load	50.00
Vectorization ratio store	80.00
Vectorization ratio mul	50.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	26.92
Vector-efficiency ratio all	17.15
Vector-efficiency ratio load	18.06
Vector-efficiency ratio store	22.50
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.94

Metric	Value
CQA speedup if no scalar integer	1.70
CQA speedup if FP arith vectorized	1.84
CQA speedup if fully vectorized	5.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	micro-operation queue,
Function	updateLinkCells.A
Source	linkCells.c:295-301,linkCells.c:352-365,linkCells.c:371-371,linkCells.c:378-378
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	8.83
CQA cycles if FP arith vectorized	8.17
CQA cycles if fully vectorized	2.94
Front-end cycles	15.00
DIV/SQRT cycles	7.50
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	7.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	3.00
P8 cycles	4.33
P9 cycles	4.50
P10 cycles	4.17
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	90.00
Nb loads	22.00
Nb stores	5.00
Nb stack references	4.00
FLOP/cycle	0.40
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.53
Bytes prefetched	0.00
Bytes loaded	236.00
Bytes stored	72.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	46.81
Vectorization ratio load	50.00
Vectorization ratio store	80.00
Vectorization ratio mul	50.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	26.92
Vector-efficiency ratio all	17.15
Vector-efficiency ratio load	18.06
Vector-efficiency ratio store	22.50
Vector-efficiency ratio mul	18.75
Vector-efficiency ratio add_sub	18.75
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	13.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	updateLinkCells.A
Source file and lines	linkCells.c:295-378
Module	exec

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:295-301,352-365,371,378.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=24
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 24 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 8.83 cycles (1.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 15.00 to 2.94 cycles (5.11x speedup).

Details

46% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
80% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
26% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

floor: 3 occurrences
getBoxFromTuple: 1 occurrences
moveAtom: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CVTTSD2SI: 1 occurrences
MOVQ: 1 occurrences
UCOMISD: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences
CVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 236 bytes (29 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	80
nb uops	90
loop length	317
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.50	5.00	5.00	5.00	7.50	10.67	10.67	10.67	3.00	4.33	4.50	4.17	6.00	6.00
cycles	7.50	5.00	5.00	5.00	7.50	10.67	10.67	10.67	3.00	4.33	4.50	4.17	6.00	6.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.00
Dispatch	10.67
Overall L1	15.00

Vectorization ratios

INT

all	18%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	61%
load	56%
store	80%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

INT+FP

all	46%
load	50%
store	80%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Vector efficiency ratios

INT

all	11%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	19%
store	22%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	17%
load	18%
store	22%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

16% of peak load performance is reached (15.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 10.67 cycles (1.41x speedup).

ASM code

In the binary file, the address of the loop is: 40fa2d

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x78(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP (%RCX,%R15,4),%R12D	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40f9f0 <updateLinkCells.A+0x60>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R12,%R13,1),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %ECX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD (%RAX,%RCX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVUPD 0x8(%RAX,%RCX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x20(%R14),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x68(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
SUBPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM2,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD %XMM0,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD -0x40(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKHPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVSD -0x68(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
UCOMISD 0x30(%R14),%XMM1	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
JAE 40fad0 <updateLinkCells.A+0x140>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVAPD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
SUBSD 0x18(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULSD 0x60(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
CVTTSD2SI %XMM0,%ESI	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	9	1
MOV (%R14),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40fabc <updateLinkCells.A+0x12c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
DEC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD -0x60(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x50(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x40(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
JMP 40fadd <updateLinkCells.A+0x14d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV (%R14),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVAPD -0x60(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x50(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKLPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
CVTTPD2DQ %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOV 0x4(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ %RCX,%XMM1	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1
PCMPEQD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PSHUFD $0x50,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVMSKPD %XMM1,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	1
TEST $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40fb10 <updateLinkCells.A+0x180>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVD %XMM0,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
JMP 40fb13 <updateLinkCells.A+0x183>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
LEA -0x1(%RCX),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
UCOMISD 0x38(%R14),%XMM2	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %ECX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TEST $0x2,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40fb30 <updateLinkCells.A+0x1a0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
PSHUFD $0x55,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVD %XMM0,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
JMP 40fb33 <updateLinkCells.A+0x1a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
LEA -0x1(%RCX),%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
UNPCKHPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
UCOMISD 0x40(%R14),%XMM2	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVB %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 40f540 <getBoxFromTuple.A>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RCX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40fa20 <updateLinkCells.A+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 40f810 <moveAtom.A>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
JMP 40fa23 <updateLinkCells.A+0x93>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	updateLinkCells.A
Source file and lines	linkCells.c:295-378
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=24
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 8.83 cycles (1.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

46% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
80% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
26% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

floor: 3 occurrences
getBoxFromTuple: 1 occurrences
moveAtom: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CVTTSD2SI: 1 occurrences
MOVQ: 1 occurrences
UCOMISD: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

MOVUPD: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences
CVTTSD2SI (FP64 to INT32/64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction
3: multiply

The binary loop is loading 236 bytes (29 double precision FP elements). The binary loop is storing 72 bytes (9 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	80
nb uops	90
loop length	317
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	4
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.50	5.00	5.00	5.00	7.50	10.67	10.67	10.67	3.00	4.33	4.50	4.17	6.00	6.00
cycles	7.50	5.00	5.00	5.00	7.50	10.67	10.67	10.67	3.00	4.33	4.50	4.17	6.00	6.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.00
Dispatch	10.67
Overall L1	15.00

Vectorization ratios

INT

all	18%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	61%
load	56%
store	80%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

INT+FP

all	46%
load	50%
store	80%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Vector efficiency ratios

INT

all	11%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	20%
load	19%
store	22%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	17%
load	18%
store	22%
mul	18%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

16% of peak load performance is reached (15.73 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.80 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 40fa2d

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
INC %R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x78(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP (%RCX,%R15,4),%R12D	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40f9f0 <updateLinkCells.A+0x60>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%R12,%R13,1),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %ECX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSD (%RAX,%RCX,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOVSD %XMM0,-0x68(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
MOVUPD 0x8(%RAX,%RCX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x20(%R14),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVUPD 0x68(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD %XMM2,-0x60(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
SUBPD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MULPD %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM2,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVAPD %XMM0,-0x50(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
MOVAPD -0x40(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKHPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOVSD -0x68(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
UCOMISD 0x30(%R14),%XMM1	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
JAE 40fad0 <updateLinkCells.A+0x140>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVAPD %XMM0,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
SUBSD 0x18(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
MULSD 0x60(%R14),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
MOVAPD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 418d00 <floor>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
CVTTSD2SI %XMM0,%ESI	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	9	1
MOV (%R14),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP %ESI,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40fabc <updateLinkCells.A+0x12c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
DEC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVAPD -0x60(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x50(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x40(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
JMP 40fadd <updateLinkCells.A+0x14d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV (%R14),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVAPD -0x60(%RBP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOVAPD -0x50(%RBP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
UNPCKLPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
CVTTPD2DQ %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOV 0x4(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVQ %RCX,%XMM1	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1
PCMPEQD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
PSHUFD $0x50,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVMSKPD %XMM1,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	1
TEST $0x1,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40fb10 <updateLinkCells.A+0x180>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOVD %XMM0,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
JMP 40fb13 <updateLinkCells.A+0x183>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
LEA -0x1(%RCX),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
UCOMISD 0x38(%R14),%XMM2	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVAE %ECX,%EDX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
SHR $0x20,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TEST $0x2,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 40fb30 <updateLinkCells.A+0x1a0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
PSHUFD $0x55,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
MOVD %XMM0,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	1
JMP 40fb33 <updateLinkCells.A+0x1a3>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
LEA -0x1(%RCX),%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
UNPCKHPD %XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.40
UCOMISD 0x40(%R14),%XMM2	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0.50	0.50	7	1
CMOVB %EAX,%ECX	1	0.50	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 40f540 <getBoxFromTuple.A>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RCX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 40fa20 <updateLinkCells.A+0x90>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R12D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 40f810 <moveAtom.A>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
JMP 40fa23 <updateLinkCells.A+0x93>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.81	0.19	0.66	0.39	0.75	0.23	0.75	0.2	0.63	0.25	0.75	0.11	0.63	0.13

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	2.41	0.83
2x2	2	0.81	1.62	2	3.55	0.99
2x4	2	0.66	2.65	4	4.21	1.14
2x8	2	0.75	6.03	8	3.57	0.93
2x16	2	0.75	12.05	16	3.56	0.8
2x32	2	0.63	20.08	32	4.43	0.66
2x64	2	0.75	48.2	64	3.6	0.43
2x96	2	0.63	60.25	96	4.09	0.34

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency