OV - - Function randomDisplacements.extracted

	Function: randomDisplacements.extracted	Module: exec	Source: initAtoms.c:194-202	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 194 - 202

--------------------------------------------------------------------------------

194:    #pragma omp parallel for

195:    for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox)

196:    {

197:       for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff)

198:       {

199:          uint64_t seed = mkSeed(s->atoms->gid[iOff], 457);

200:          s->atoms->r[iOff][0] += (2.0*lcg61(&seed)-1.0) * delta;

201:          s->atoms->r[iOff][1] += (2.0*lcg61(&seed)-1.0) * delta;

202:          s->atoms->r[iOff][2] += (2.0*lcg61(&seed)-1.0) * delta;

0x40e5f0 PUSH	%RBP

0x40e5f1 MOV	%RSP,%RBP

0x40e5f4 PUSH	%R15

0x40e5f6 PUSH	%R14

0x40e5f8 PUSH	%R13

0x40e5fa PUSH	%R12

0x40e5fc PUSH	%RBX

0x40e5fd SUB	$0x48,%RSP

0x40e601 MOV	%RCX,%R15

0x40e604 MOV	%RDX,%R14

0x40e607 MOVL	$0,-0x4c(%RBP)

0x40e60e MOV	(%RDI),%ESI

0x40e610 MOVL	$0,-0x34(%RBP)

0x40e617 MOV	%R9D,-0x30(%RBP)

0x40e61b MOVL	$0x1,-0x48(%RBP)

0x40e622 SUB	$0x8,%RSP

0x40e626 LEA	-0x48(%RBP),%RAX

0x40e62a LEA	-0x4c(%RBP),%RCX

0x40e62e LEA	-0x34(%RBP),%R8

0x40e632 LEA	-0x30(%RBP),%R9

0x40e636 MOV	$0x4387f0,%EDI

0x40e63b MOV	%ESI,-0x44(%RBP)

0x40e63e MOV	$0x22,%EDX

0x40e643 PUSH	$0x1

0x40e645 PUSH	$0x1

0x40e647 PUSH	%RAX

0x40e648 CALL	405320 <__kmpc_for_static_init_4@plt>

0x40e64d ADD	$0x20,%RSP

0x40e651 MOV	-0x34(%RBP),%R13D

0x40e655 MOV	-0x30(%RBP),%EAX

0x40e658 MOV	%RAX,-0x58(%RBP)

0x40e65c CMP	%EAX,%R13D

0x40e65f JBE	40e67d

0x40e661 MOV	$0x438810,%EDI

0x40e666 MOV	-0x44(%RBP),%ESI

0x40e669 CALL	405150 <__kmpc_for_static_fini@plt>

0x40e66e ADD	$0x48,%RSP

0x40e672 POP	%RBX

0x40e673 POP	%R12

0x40e675 POP	%R13

0x40e677 POP	%R14

0x40e679 POP	%R15

0x40e67b POP	%RBP

0x40e67c RET

0x40e67d MOVQ	%R15,%XMM1

0x40e682 MOV	%R13D,%EAX

0x40e685 SAL	$0x6,%EAX

0x40e688 MOV	%EAX,-0x2c(%RBP)

0x40e68b INCQ	-0x58(%RBP)

0x40e68f MOV	0x18(%R14),%RAX

0x40e693 LEA	-0x68(%RBP),%R15

0x40e697 MOVQ	%XMM1,-0x40(%RBP)

0x40e69c JMP	40e6ad

0x40e69e XCHG	%AX,%AX

(121) 0x40e6a0 INC	%R13

(121) 0x40e6a3 ADDL	$0x40,-0x2c(%RBP)

(121) 0x40e6a7 CMP	-0x58(%RBP),%R13

(121) 0x40e6ab JE	40e661

(121) 0x40e6ad MOV	0x78(%RAX),%RCX

(121) 0x40e6b1 CMPL	$0,(%RCX,%R13,4)

(121) 0x40e6b6 JLE	40e6a0

(121) 0x40e6b8 MOV	-0x2c(%RBP),%ECX

(121) 0x40e6bb LEA	(,%RCX,8),%RAX

(121) 0x40e6c3 LEA	(%RAX,%RAX,2),%RBX

(121) 0x40e6c7 SAL	$0x2,%RCX

(121) 0x40e6cb MOV	%RCX,-0x60(%RBP)

(121) 0x40e6cf MOV	0x20(%R14),%RCX

(121) 0x40e6d3 XOR	%R12D,%R12D

(121) 0x40e6d6 NOPW	%CS:(%RAX,%RAX,1)

  (122) 0x40e6e0 MOV	0x8(%RCX),%RAX

  (122) 0x40e6e4 ADD	-0x60(%RBP),%RAX

  (122) 0x40e6e8 MOV	(%RAX,%R12,4),%EDI

  (122) 0x40e6ec MOV	$0x1c9,%ESI

  (122) 0x40e6f1 CALL	405040 <@plt>

  (122) 0x40e6f6 MOV	%RAX,-0x68(%RBP)

  (122) 0x40e6fa MOV	%R15,%RDI

  (122) 0x40e6fd CALL	417850 <lcg61>

  (122) 0x40e702 ADDSD	%XMM0,%XMM0

  (122) 0x40e706 ADDSD	0x1dfb2(%RIP),%XMM0

  (122) 0x40e70e MULSD	-0x40(%RBP),%XMM0

  (122) 0x40e713 MOV	0x20(%R14),%RAX

  (122) 0x40e717 MOV	0x18(%RAX),%RAX

  (122) 0x40e71b ADDSD	(%RAX,%RBX,1),%XMM0

  (122) 0x40e720 MOVSD	%XMM0,(%RAX,%RBX,1)

  (122) 0x40e725 MOV	%R15,%RDI

  (122) 0x40e728 CALL	417850 <lcg61>

  (122) 0x40e72d ADDSD	%XMM0,%XMM0

  (122) 0x40e731 ADDSD	0x1df87(%RIP),%XMM0

  (122) 0x40e739 MULSD	-0x40(%RBP),%XMM0

  (122) 0x40e73e MOV	0x20(%R14),%RAX

  (122) 0x40e742 MOV	0x18(%RAX),%RAX

  (122) 0x40e746 ADDSD	0x8(%RAX,%RBX,1),%XMM0

  (122) 0x40e74c MOVSD	%XMM0,0x8(%RAX,%RBX,1)

  (122) 0x40e752 MOV	%R15,%RDI

  (122) 0x40e755 CALL	417850 <lcg61>

  (122) 0x40e75a MOVSD	0x1df5e(%RIP),%XMM2

  (122) 0x40e762 MOVSD	-0x40(%RBP),%XMM1

  (122) 0x40e767 ADDSD	%XMM0,%XMM0

  (122) 0x40e76b ADDSD	%XMM2,%XMM0

  (122) 0x40e76f MULSD	%XMM1,%XMM0

  (122) 0x40e773 MOV	0x20(%R14),%RCX

  (122) 0x40e777 MOV	0x18(%RCX),%RAX

  (122) 0x40e77b ADDSD	0x10(%RAX,%RBX,1),%XMM0

  (122) 0x40e781 MOVSD	%XMM0,0x10(%RAX,%RBX,1)

  (122) 0x40e787 MOV	0x18(%R14),%RAX

  (122) 0x40e78b MOV	0x78(%RAX),%RDX

  (122) 0x40e78f ADD	$0x18,%RBX

  (122) 0x40e793 INC	%R12

  (122) 0x40e796 CMP	(%RDX,%R13,4),%R12D

  (122) 0x40e79a JL	40e6e0

(121) 0x40e7a0 JMP	40e6a0

0x40e7a5 NOPW	%CS:(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	initAtoms.c:194-202
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:194-202.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.00 cycles (9.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.50 to 0.66 cycles (14.43x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_fini@plt: 1 occurrences
__kmpc_for_static_init_4@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences
MOVQ: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	55
nb uops	57
loop length	187
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.25	4.25	2.50	5.33	5.33	5.33	0.25	0.25	0.25	0.25	0.50	0.50
cycles	4.50	4.50	4.25	4.25	2.50	5.33	5.33	5.33	0.25	0.25	0.25	0.25	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	5.33
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (5.05 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.50 to 5.33 cycles (1.78x speedup).

ASM code

In the binary file, the address of the function is: 40e5f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x4c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R9D,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x4c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x34(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x4387f0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 405320 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x34(%RBP),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %EAX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 40e67d <randomDisplacements.extracted+0x8d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV $0x438810,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CALL 405150 <__kmpc_for_static_fini@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVQ %R15,%XMM1	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
INCQ -0x58(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x18(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA -0x68(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ %XMM1,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
JMP 40e6ad <randomDisplacements.extracted+0xbd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	initAtoms.c:194-202
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c:194-202.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.00 cycles (9.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_fini@plt: 1 occurrences
__kmpc_for_static_init_4@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

INC: 1 occurrences
MOVQ: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	55
nb uops	57
loop length	187
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	4.50	4.50	4.25	4.25	2.50	5.33	5.33	5.33	0.25	0.25	0.25	0.25	0.50	0.50
cycles	4.50	4.50	4.25	4.25	2.50	5.33	5.33	5.33	0.25	0.25	0.25	0.25	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.50
Dispatch	5.33
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

3% of peak load performance is reached (3.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (5.05 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40e5f0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x4c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV (%RDI),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV %R9D,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVL $0x1,-0x48(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x48(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x4c(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x34(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x30(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV $0x4387f0,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 405320 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x34(%RBP),%R13D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV -0x30(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
CMP %EAX,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 40e67d <randomDisplacements.extracted+0x8d>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV $0x438810,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CALL 405150 <__kmpc_for_static_fini@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVQ %R15,%XMM1	2	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	6	1
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
INCQ -0x58(%RBP)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
MOV 0x18(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA -0x68(%RBP),%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVQ %XMM1,-0x40(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
JMP 40e6ad <randomDisplacements.extracted+0xbd>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.75	0	0.75	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.03	0.01
2x2	4	0.75	1.5	2	0.03	0.01
2x4	8	0.75	3	4	0.02	0.01
2x8	13	1	1	8	0.01	0.01
2x16	18	1	1	16	0	0.01
2x32	30	1	1	32	0	0.01
2x64	60	1	1	64	0.01	0.02
2x96	111	1	1	96	0	0.03

Name	Coverage (%)	Time (s)
▼randomDisplacements.extracted–	0.01	0.03
▼Loop 121 - initAtoms.c:194-202 - exec–	0	0
○Loop 122 - initAtoms.c:197-202 - exec	0.01	0.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency