OV - - Function sortAtomsInCell.A

	Function: sortAtomsInCell.A	Module: exec	Source: haloExchange.c:614-645	Coverage: 0.99%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 614 - 645

--------------------------------------------------------------------------------

614: {

615:    int nAtoms = boxes->nAtoms[iBox];

616:

617:    AtomMsg tmp[nAtoms];

618:

619:    int begin = iBox*MAXATOMS;

620:    int end = begin + nAtoms;

621:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

622:    {

623:       tmp[iTmp].gid  = atoms->gid[ii];

624:       tmp[iTmp].type = atoms->iSpecies[ii];

625:       tmp[iTmp].rx =   atoms->r[ii][0];

626:       tmp[iTmp].ry =   atoms->r[ii][1];

627:       tmp[iTmp].rz =   atoms->r[ii][2];

628:       tmp[iTmp].px =   atoms->p[ii][0];

629:       tmp[iTmp].py =   atoms->p[ii][1];

630:       tmp[iTmp].pz =   atoms->p[ii][2];

631:    }

632:    qsort(&tmp, nAtoms, sizeof(AtomMsg), sortAtomsById);

633:    for (int ii=begin, iTmp=0; ii<end; ++ii, ++iTmp)

634:    {

635:       atoms->gid[ii]   = tmp[iTmp].gid;

636:       atoms->iSpecies[ii] = tmp[iTmp].type;

637:       atoms->r[ii][0]  = tmp[iTmp].rx;

638:       atoms->r[ii][1]  = tmp[iTmp].ry;

639:       atoms->r[ii][2]  = tmp[iTmp].rz;

640:       atoms->p[ii][0]  = tmp[iTmp].px;

641:       atoms->p[ii][1]  = tmp[iTmp].py;

642:       atoms->p[ii][2]  = tmp[iTmp].pz;

643:    }

644:

645: }

0x40be30 PUSH	%RBP

0x40be31 MOV	%RSP,%RBP

0x40be34 PUSH	%R15

0x40be36 PUSH	%R14

0x40be38 PUSH	%R12

0x40be3a PUSH	%RBX

0x40be3b MOV	0x78(%RSI),%RAX

0x40be3f MOVSXD	%EDX,%RCX

0x40be42 MOV	(%RAX,%RCX,4),%ESI

0x40be45 IMUL	$0x38,%RSI,%RAX

0x40be49 ADD	$0xf,%RAX

0x40be4d AND	$-0x10,%RAX

0x40be51 MOV	%RSP,%RBX

0x40be54 SUB	%RAX,%RBX

0x40be57 MOV	%RBX,%RSP

0x40be5a TEST	%ESI,%ESI

0x40be5c JLE	40bf67

0x40be62 MOV	%RDI,%R14

0x40be65 SAL	$0x6,%EDX

0x40be68 LEA	(%RSI,%RDX,1),%R9D

0x40be6c MOV	0x8(%RDI),%RAX

0x40be70 MOV	0x10(%RDI),%RCX

0x40be74 MOV	0x18(%RDI),%RDI

0x40be78 MOV	0x20(%R14),%R8

0x40be7c MOVSXD	%EDX,%R15

0x40be7f MOVSXD	%R9D,%R12

0x40be82 LEA	(%R15,%R15,1),%RDX

0x40be86 LEA	(%RDX,%RDX,2),%RDX

0x40be8a ADD	$0x4,%RDX

0x40be8e MOV	%RBX,%R9

0x40be91 MOV	%R15,%R10

0x40be94 NOPW	%CS:(%RAX,%RAX,1)

(84) 0x40bea0 MOV	(%RAX,%R10,4),%R11D

(84) 0x40bea4 MOV	%R11D,(%R9)

(84) 0x40bea7 MOV	(%RCX,%R10,4),%R11D

(84) 0x40beab MOV	%R11D,0x4(%R9)

(84) 0x40beaf MOVUPS	-0x10(%RDI,%RDX,4),%XMM0

(84) 0x40beb4 MOVUPS	%XMM0,0x8(%R9)

(84) 0x40beb9 MOVSD	(%RDI,%RDX,4),%XMM0

(84) 0x40bebe MOVSD	%XMM0,0x18(%R9)

(84) 0x40bec4 MOVUPS	-0x10(%R8,%RDX,4),%XMM0

(84) 0x40beca MOVUPS	%XMM0,0x20(%R9)

(84) 0x40becf MOVSD	(%R8,%RDX,4),%XMM0

(84) 0x40bed5 MOVSD	%XMM0,0x30(%R9)

(84) 0x40bedb INC	%R10

(84) 0x40bede ADD	$0x6,%RDX

(84) 0x40bee2 ADD	$0x38,%R9

(84) 0x40bee6 CMP	%R12,%R10

(84) 0x40bee9 JL	40bea0

0x40beeb MOV	$0x38,%EDX

0x40bef0 MOV	$0x40bf90,%ECX

0x40bef5 MOV	%RBX,%RDI

0x40bef8 CALL	405380 <qsort@plt>

0x40befd MOV	0x8(%R14),%RAX

0x40bf01 MOV	0x10(%R14),%RCX

0x40bf05 MOV	0x18(%R14),%RDX

0x40bf09 MOV	0x20(%R14),%RSI

0x40bf0d LEA	(%R15,%R15,2),%RDI

0x40bf11 LEA	0x10(,%RDI,8),%RDI

0x40bf19 NOPL	(%RAX)

(85) 0x40bf20 MOV	(%RBX),%R8D

(85) 0x40bf23 MOV	%R8D,(%RAX,%R15,4)

(85) 0x40bf27 MOV	0x4(%RBX),%R8D

(85) 0x40bf2b MOV	%R8D,(%RCX,%R15,4)

(85) 0x40bf2f MOVUPS	0x8(%RBX),%XMM0

(85) 0x40bf33 MOVUPS	%XMM0,-0x10(%RDX,%RDI,1)

(85) 0x40bf38 MOVSD	0x18(%RBX),%XMM0

(85) 0x40bf3d MOVSD	%XMM0,(%RDX,%RDI,1)

(85) 0x40bf42 MOVUPS	0x20(%RBX),%XMM0

(85) 0x40bf46 MOVUPS	%XMM0,-0x10(%RSI,%RDI,1)

(85) 0x40bf4b MOVSD	0x30(%RBX),%XMM0

(85) 0x40bf50 MOVSD	%XMM0,(%RSI,%RDI,1)

(85) 0x40bf55 INC	%R15

(85) 0x40bf58 ADD	$0x18,%RDI

(85) 0x40bf5c ADD	$0x38,%RBX

(85) 0x40bf60 CMP	%R12,%R15

(85) 0x40bf63 JL	40bf20

0x40bf65 JMP	40bf7c

0x40bf67 MOVSXD	%ESI,%RSI

0x40bf6a MOV	$0x38,%EDX

0x40bf6f MOV	$0x40bf90,%ECX

0x40bf74 MOV	%RBX,%RDI

0x40bf77 CALL	405380 <qsort@plt>

0x40bf7c LEA	-0x20(%RBP),%RSP

0x40bf80 POP	%RBX

0x40bf81 POP	%R12

0x40bf83 POP	%R14

0x40bf85 POP	%R15

0x40bf87 POP	%RBP

0x40bf88 RET

0x40bf89 NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	haloExchange.c:614-645
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:614-645.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.33 to 0.83 cycles (11.20x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

qsort@plt: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes.

General properties

nb instructions	57
nb uops	56
loop length	208
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	5.75	5.75	2.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.00	6.00	5.75	5.75	2.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.33
Dispatch	6.00
Overall L1	9.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.33 cycles. At this rate:

8% of peak load performance is reached (8.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.33 to 6.00 cycles (1.56x speedup).

ASM code

In the binary file, the address of the function is: 40be30

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
MOV 0x78(%RSI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD %EDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RAX,%RCX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL $0x38,%RSI,%RAX	1	0	1	0	0	0	0	0	0	3	1
ADD $0xf,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
AND $-0x10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RSP,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
SUB %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RBX,%RSP	1	0	0	0	0	0	0	0	0	0	0.17
TEST %ESI,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 40bf67 <sortAtomsInCell.A+0x137>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EDX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
LEA (%RSI,%RDX,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x8(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x10(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x20(%R14),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD %EDX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVSXD %R9D,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R15,%R15,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%RDX,%RDX,2),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0.17
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV $0x38,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x40bf90,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 405380 <qsort@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x8(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x10(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%R14),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x20(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%R15,%R15,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x10(,%RDI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
JMP 40bf7c <sortAtomsInCell.A+0x14c>	1	0.50	0	0	0	0.50	0	0	0	0	1
MOVSXD %ESI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x38,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x40bf90,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 405380 <qsort@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	haloExchange.c:614-645
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c:614-645.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

qsort@plt: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes.

General properties

nb instructions	57
nb uops	56
loop length	208
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.33 cycles
front end	9.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	6.00	6.00	5.75	5.75	2.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.00	6.00	5.75	5.75	2.50	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.33
Dispatch	6.00
Overall L1	9.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.33 cycles. At this rate:

8% of peak load performance is reached (8.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40be30

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
MOV 0x78(%RSI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD %EDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV (%RAX,%RCX,4),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
IMUL $0x38,%RSI,%RAX	1	0	1	0	0	0	0	0	0	3	1
ADD $0xf,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
AND $-0x10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RSP,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
SUB %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RBX,%RSP	1	0	0	0	0	0	0	0	0	0	0.17
TEST %ESI,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 40bf67 <sortAtomsInCell.A+0x137>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%EDX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
LEA (%RSI,%RDX,1),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x8(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x10(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RDI),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x20(%R14),%R8	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD %EDX,%R15	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVSXD %R9D,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R15,%R15,1),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%RDX,%RDX,2),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x4,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0.17
MOV %R15,%R10	1	0	0	0	0	0	0	0	0	0	0.17
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
MOV $0x38,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x40bf90,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 405380 <qsort@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x8(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x10(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%R14),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x20(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (%R15,%R15,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x10(,%RDI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
JMP 40bf7c <sortAtomsInCell.A+0x14c>	1	0.50	0	0	0	0.50	0	0	0	0	1
MOVSXD %ESI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x38,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV $0x40bf90,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 405380 <qsort@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
LEA -0x20(%RBP),%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.72	0.38	0.52	0.84	0.37	1.44	0.33	1.43	0.3	1.2	0.19	1.62	0.17	1.36

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	2.96	0.99
2x2	4	0.72	1.43	2	3.06	1.34
2x4	8	0.52	2.07	4	1.7	1.74
2x8	16	0.37	2.94	8	1.58	2.28
2x16	32	0.33	5.33	16	0.87	2.14
2x32	64	0.3	9.6	32	0.57	1.71
2x64	128	0.19	12	64	0.43	1.99
2x96	192	0.17	16	96	0.34	1.63

Name	Coverage (%)	Time (s)
▼sortAtomsInCell.A–	0.99	2.88
○Loop 84 - haloExchange.c:621-630 - exec	0.83	2.41
○Loop 85 - haloExchange.c:633-642 - exec	0.14	0.39

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Vectorization

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Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

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ASM code

Vectorization

Details

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Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency