OV - - Function __libm_log

	Function: __libm_log_z0	Module: exec	Source: :0-0	Coverage: 0.01%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x41a3a0 ENDBR64

0x41a3a4 SUB	$0x18,%RSP

0x41a3a8 VMOVQ	%XMM0,%RAX

0x41a3ad SHR	$0x20,%RAX

0x41a3b1 LEA	-0x7ff00000(%RAX),%ECX

0x41a3b7 CMP	$-0x7fe00000,%ECX

0x41a3bd JB	41a4af

0x41a3c3 VPBROADCASTQ	0x16914(%RIP),%XMM1

0x41a3cc VPTERNLOGQ	$-0x8,0x16911(%RIP){1to2},%XMM0,%XMM1

0x41a3d7 VPSRLQ	$0x34,%XMM0,%XMM0

0x41a3dc VMOVD	%XMM0,%EAX

0x41a3e0 ADD	$-0x3ff,%EAX

0x41a3e5 VCVTSI2SD	%EAX,%XMM2,%XMM0

0x41a3e9 VMOVQ	%XMM1,%XMM2

0x41a3ed VPSRLQ	$0x1d,%XMM2,%XMM2

0x41a3f2 VRCPSS	%XMM2,%XMM2,%XMM2

0x41a3f6 VPADDD	0x16074(%RIP){1to4},%XMM2,%XMM2

0x41a400 VPSRLD	$0x10,%XMM2,%XMM2

0x41a405 VPSLLQ	$0x2d,%XMM2,%XMM3

0x41a40a VPORQ	0x168dc(%RIP){1to2},%XMM1,%XMM1

0x41a414 VFMADD213SD	0x122a3(%RIP),%XMM3,%XMM1

0x41a41d VMOVSD	0x1606b(%RIP),%XMM3

0x41a425 VFMADD213SD	0x1606a(%RIP),%XMM1,%XMM3

0x41a42e VMOVSD	0x1606a(%RIP),%XMM4

0x41a436 VFMADD213SD	0x16069(%RIP),%XMM1,%XMM4

0x41a43f VMOVSD	0x16069(%RIP),%XMM5

0x41a447 VFMADD213SD	0x16068(%RIP),%XMM1,%XMM5

0x41a450 VPADDQ	%XMM2,%XMM2,%XMM2

0x41a454 VMOVD	%XMM2,%EAX

0x41a458 AND	$0x1fe,%EAX

0x41a45d LEA	0x1(%RAX),%ECX

0x41a460 LEA	0x16899(%RIP),%RDX

0x41a467 VMOVSD	0x16051(%RIP),%XMM2

0x41a46f VFMADD213SD	(%RDX,%RCX,8),%XMM0,%XMM2

0x41a475 VMOVSD	0x1604b(%RIP),%XMM6

0x41a47d VFMADD213SD	(%RDX,%RAX,8),%XMM0,%XMM6

0x41a483 VADDSD	%XMM1,%XMM6,%XMM0

0x41a487 VSUBSD	%XMM6,%XMM0,%XMM6

0x41a48b VSUBSD	%XMM6,%XMM1,%XMM6

0x41a48f VADDSD	%XMM6,%XMM2,%XMM2

0x41a493 VMULSD	%XMM1,%XMM1,%XMM1

0x41a497 VFMADD231SD	%XMM3,%XMM1,%XMM4

0x41a49c VFMADD213SD	%XMM5,%XMM1,%XMM4

0x41a4a1 VFMADD213SD	%XMM2,%XMM1,%XMM4

0x41a4a6 VADDSD	%XMM4,%XMM0,%XMM0

0x41a4aa ADD	$0x18,%RSP

0x41a4ae RET

0x41a4af VXORPD	%XMM1,%XMM1,%XMM1

0x41a4b3 VADDSD	%XMM1,%XMM0,%XMM0

0x41a4b7 VMOVSD	%XMM0,0x10(%RSP)

0x41a4bd VMOVQ	%XMM0,%RCX

0x41a4c2 TEST	%RCX,%RCX

0x41a4c5 JE	41a509

0x41a4c7 CMP	$0xfffff,%EAX

0x41a4cc JA	41a509

0x41a4ce VMULSD	0x15faa(%RIP),%XMM0,%XMM0

0x41a4d6 VPBROADCASTQ	0x16801(%RIP),%XMM1

0x41a4df VPTERNLOGQ	$-0x8,0x167fe(%RIP){1to2},%XMM0,%XMM1

0x41a4ea VPSRLQ	$0x34,%XMM0,%XMM0

0x41a4ef VMOVD	%XMM0,%EAX

0x41a4f3 ADD	$-0x3ff,%EAX

0x41a4f8 VCVTSI2SD	%EAX,%XMM2,%XMM0

0x41a4fc VADDSD	0x15f84(%RIP),%XMM0,%XMM0

0x41a504 JMP	41a3e9

0x41a509 MOV	$0x7ff0000000000000,%RDX

0x41a513 CMP	%RDX,%RCX

0x41a516 JE	41a597

0x41a518 MOV	$0x3f,%AL

0x41a51a BZHI	%RAX,%RCX,%RAX

0x41a51f CMP	%RDX,%RAX

0x41a522 JBE	41a531

0x41a524 VADDSD	0x10e54(%RIP),%XMM0,%XMM0

0x41a52c ADD	$0x18,%RSP

0x41a530 RET

0x41a531 VMOVSS	0x15f37(%RIP),%XMM0

0x41a539 VRCPSS	%XMM0,%XMM0,%XMM0

0x41a53d VCVTSS2SD	%XMM0,%XMM0,%XMM0

0x41a541 TEST	%RAX,%RAX

0x41a544 JE	41a568

0x41a546 VMULSD	0x15f2a(%RIP),%XMM0,%XMM0

0x41a54e VMOVSD	%XMM0,0x8(%RSP)

0x41a554 LEA	0x10(%RSP),%RDI

0x41a559 LEA	0x8(%RSP),%RDX

0x41a55e MOV	%RDI,%RSI

0x41a561 MOV	$0x3,%ECX

0x41a566 JMP	41a58c

0x41a568 VMOVSD	0x12150(%RIP),%XMM1

0x41a570 VDIVSD	%XMM0,%XMM1,%XMM0

0x41a574 VMOVSD	%XMM0,0x8(%RSP)

0x41a57a LEA	0x10(%RSP),%RDI

0x41a57f LEA	0x8(%RSP),%RDX

0x41a584 MOV	%RDI,%RSI

0x41a587 MOV	$0x2,%ECX

0x41a58c CALL	419880 <__libm_error_support>

0x41a591 VMOVSD	0x8(%RSP),%XMM0

0x41a597 ADD	$0x18,%RSP

0x41a59b RET

0x41a59c NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines
Module	exec

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=10

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 10 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.50 to 11.33 cycles (1.46x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.50 to 2.44 cycles (6.77x speedup).

Details

17% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
20% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
32% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 9 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__libm_error_support: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSI2SD: 2 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 2 occurrences
VCVTSS2SD (FP32 to FP64, scalar): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 21 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 32 FP arithmetical operations:

17: addition or subtraction (9 inside FMA instructions)
12: multiply (9 inside FMA instructions)
1: divide
2: fast reciprocal

The binary function is loading 184 bytes (23 double precision FP elements). The binary function is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	98
nb uops	99
loop length	512
used x86 registers	6
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	2.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	8.00	8.00	8.00	8.00	6.00	9.33	9.33	9.33	9.25	9.25	9.25	9.25	4.00	4.00
cycles	8.00	8.00	8.00	8.00	6.00	9.33	9.33	9.33	9.25	9.25	9.25	9.25	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

5.00

Cycles summary

Front-end	16.50
Dispatch	9.33
DIV/SQRT	5.00
Overall L1	16.50

Vectorization ratios

INT

all	35%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	17%
load	16%
store	0%
mul	0%
add-sub	20%
fma	0%
div/sqrt	0%
other	32%

Vector efficiency ratios

INT

all	15%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	8%
other	15%

INT+FP

all	13%
load	14%
store	12%
mul	12%
add-sub	15%
fma	12%
div/sqrt	8%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.50 cycles. At this rate:

11% of peak load performance is reached (11.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.50 to 9.33 cycles (1.77x speedup).

ASM code

In the binary file, the address of the function is: 41a3a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ENDBR64
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x7ff00000(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x7fe00000,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 41a4af <__libm_log_z0+0x10f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VPBROADCASTQ 0x16914(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPTERNLOGQ $-0x8,0x16911(%RIP){1to2},%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VPSRLQ $0x34,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VMOVD %XMM0,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
ADD $-0x3ff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCVTSI2SD %EAX,%XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VMOVQ %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPSRLQ $0x1d,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VRCPSS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPADDD 0x16074(%RIP){1to4},%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VPSRLD $0x10,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VPSLLQ $0x2d,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VPORQ 0x168dc(%RIP){1to2},%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VFMADD213SD 0x122a3(%RIP),%XMM3,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x1606b(%RIP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD 0x1606a(%RIP),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x1606a(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD 0x16069(%RIP),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x16069(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD 0x16068(%RIP),%XMM1,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VPADDQ %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVD %XMM2,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
AND $0x1fe,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x16899(%RIP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x16051(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD (%RDX,%RCX,8),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x1604b(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM1,%XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM6,%XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM6,%XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM6,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM3,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SD %XMM5,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SD %XMM2,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM4,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM0,0x10(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM0,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
TEST %RCX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 41a509 <__libm_log_z0+0x169>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0xfffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JA 41a509 <__libm_log_z0+0x169>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMULSD 0x15faa(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VPBROADCASTQ 0x16801(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPTERNLOGQ $-0x8,0x167fe(%RIP){1to2},%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VPSRLQ $0x34,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VMOVD %XMM0,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
ADD $-0x3ff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCVTSI2SD %EAX,%XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VADDSD 0x15f84(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
JMP 41a3e9 <__libm_log_z0+0x49>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV $0x7ff0000000000000,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 41a597 <__libm_log_z0+0x1f7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV $0x3f,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
BZHI %RAX,%RCX,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 41a531 <__libm_log_z0+0x191>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VADDSD 0x10e54(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSS 0x15f37(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VRCPSS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VCVTSS2SD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 41a568 <__libm_log_z0+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMULSD 0x15f2a(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VMOVSD %XMM0,0x8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA 0x10(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x8(%RSP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x3,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 41a58c <__libm_log_z0+0x1ec>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VMOVSD 0x12150(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VDIVSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVSD %XMM0,0x8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA 0x10(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x8(%RSP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 419880 <__libm_error_support>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
VMOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines
Module	exec

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=10

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

17% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

16% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
20% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
32% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 9 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

CALL instructions

Detected function call instructions.

Details

__libm_error_support: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSI2SD: 2 occurrences

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSI2SD (INT32/64 to FP64, scalar): 2 occurrences
VCVTSS2SD (FP32 to FP64, scalar): 1 occurrences

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 32 FP arithmetical operations:

17: addition or subtraction (9 inside FMA instructions)
12: multiply (9 inside FMA instructions)
1: divide
2: fast reciprocal

The binary function is loading 184 bytes (23 double precision FP elements). The binary function is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	98
nb uops	99
loop length	512
used x86 registers	6
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	2.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	8.00	8.00	8.00	8.00	6.00	9.33	9.33	9.33	9.25	9.25	9.25	9.25	4.00	4.00
cycles	8.00	8.00	8.00	8.00	6.00	9.33	9.33	9.33	9.25	9.25	9.25	9.25	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

5.00

Cycles summary

Front-end	16.50
Dispatch	9.33
DIV/SQRT	5.00
Overall L1	16.50

Vectorization ratios

INT

all	35%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

INT+FP

all	17%
load	16%
store	0%
mul	0%
add-sub	20%
fma	0%
div/sqrt	0%
other	32%

Vector efficiency ratios

INT

all	15%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	12%
div/sqrt	8%
other	15%

INT+FP

all	13%
load	14%
store	12%
mul	12%
add-sub	15%
fma	12%
div/sqrt	8%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.50 cycles. At this rate:

11% of peak load performance is reached (11.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 41a3a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ENDBR64
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SHR $0x20,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x7ff00000(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x7fe00000,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 41a4af <__libm_log_z0+0x10f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VPBROADCASTQ 0x16914(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPTERNLOGQ $-0x8,0x16911(%RIP){1to2},%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VPSRLQ $0x34,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VMOVD %XMM0,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
ADD $-0x3ff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCVTSI2SD %EAX,%XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VMOVQ %XMM1,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPSRLQ $0x1d,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VRCPSS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPADDD 0x16074(%RIP){1to4},%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VPSRLD $0x10,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VPSLLQ $0x2d,%XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VPORQ 0x168dc(%RIP){1to2},%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VFMADD213SD 0x122a3(%RIP),%XMM3,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x1606b(%RIP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD 0x1606a(%RIP),%XMM1,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x1606a(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD 0x16069(%RIP),%XMM1,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x16069(%RIP),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD 0x16068(%RIP),%XMM1,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VPADDQ %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVD %XMM2,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
AND $0x1fe,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x16899(%RIP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x16051(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD (%RDX,%RCX,8),%XMM0,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x1604b(%RIP),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM1,%XMM6,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM6,%XMM0,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBSD %XMM6,%XMM1,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VADDSD %XMM6,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMULSD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VFMADD231SD %XMM3,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SD %XMM5,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213SD %XMM2,%XMM1,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD %XMM4,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VMOVSD %XMM0,0x10(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM0,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
TEST %RCX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 41a509 <__libm_log_z0+0x169>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0xfffff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JA 41a509 <__libm_log_z0+0x169>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMULSD 0x15faa(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VPBROADCASTQ 0x16801(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPTERNLOGQ $-0x8,0x167fe(%RIP){1to2},%XMM0,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VPSRLQ $0x34,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VMOVD %XMM0,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	1
ADD $-0x3ff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCVTSI2SD %EAX,%XMM2,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1.25
VADDSD 0x15f84(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
JMP 41a3e9 <__libm_log_z0+0x49>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
MOV $0x7ff0000000000000,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.33
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 41a597 <__libm_log_z0+0x1f7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV $0x3f,%AL	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
BZHI %RAX,%RCX,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 41a531 <__libm_log_z0+0x191>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VADDSD 0x10e54(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
VMOVSS 0x15f37(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VRCPSS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VCVTSS2SD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 41a568 <__libm_log_z0+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMULSD 0x15f2a(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VMOVSD %XMM0,0x8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA 0x10(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x8(%RSP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x3,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JMP 41a58c <__libm_log_z0+0x1ec>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VMOVSD 0x12150(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VDIVSD %XMM0,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	5
VMOVSD %XMM0,0x8(%RSP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
LEA 0x10(%RSP),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x8(%RSP),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x2,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CALL 419880 <__libm_error_support>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0	0	0	0	0.50
VMOVSD 0x8(%RSP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.05	0.01
2x2	4	1	2	2	0.02	0.01
2x4	8	1	4	4	0.01	0.01
2x8	16	1	1	8	0.01	0.01
2x16	30	1	1	16	0.01	0.01
2x32	41	1	1	32	0	0.01
2x64	58	1	1	64	0	0
2x96	64	1	1	96	0	0

Name	Coverage (%)	Time (s)
○__libm_log_z0	0.01	0.04

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Matching between your function (in the source code) and the binary function

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Code clean check

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FMA

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CALL instructions

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Complex instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency