OV - - Function mkSeed.A

	Function: mkSeed.A	Module: exec	Source: random.c:46-74 [...]	Coverage: 0.02%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 46 - 74

--------------------------------------------------------------------------------

46:    *seed %= UINT64_C(2305843009213693951);

[...]

66: {

67:    uint32_t s1 = id * UINT32_C(2654435761);

68:    uint32_t s2 = (id+callSite) * UINT32_C(2654435761);

69:

70:    uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2;

71:    for (unsigned jj=0; jj<10; ++jj)

72:       lcg61(&iSeed);

73:

74:    return iSeed;

0x4178a0 PUSH	%RBP

0x4178a1 MOV	%RSP,%RBP

0x4178a4 IMUL	$-0x61c8864f,%EDI,%EAX

0x4178aa ADD	%EDI,%ESI

0x4178ac IMUL	$-0x61c8864f,%ESI,%ESI

0x4178b2 SAL	$0x20,%RAX

0x4178b6 OR	%RAX,%RSI

0x4178b9 MOV	$0x613606df9756715,%RDI

0x4178c3 IMUL	%RDI,%RSI

0x4178c7 MOV	$0x9,%R8D

0x4178cd MOV	%RSI,%RAX

0x4178d0 MUL	%R8

0x4178d3 MOV	%RSI,%RCX

0x4178d6 SUB	%RDX,%RCX

0x4178d9 SHR	$0x1,%RCX

0x4178dc ADD	%RDX,%RCX

0x4178df SHR	$0x3c,%RCX

0x4178e3 MOV	%RCX,%RAX

0x4178e6 SAL	$0x3d,%RAX

0x4178ea SUB	%RAX,%RCX

0x4178ed ADD	%RSI,%RCX

0x4178f0 IMUL	%RDI,%RCX

0x4178f4 MOV	%RCX,%RAX

0x4178f7 MUL	%R8

0x4178fa MOV	%RCX,%RSI

0x4178fd SUB	%RDX,%RSI

0x417900 SHR	$0x1,%RSI

0x417903 ADD	%RDX,%RSI

0x417906 SHR	$0x3c,%RSI

0x41790a MOV	%RSI,%RAX

0x41790d SAL	$0x3d,%RAX

0x417911 SUB	%RAX,%RSI

0x417914 ADD	%RCX,%RSI

0x417917 IMUL	%RDI,%RSI

0x41791b MOV	%RSI,%RAX

0x41791e MUL	%R8

0x417921 MOV	%RSI,%RCX

0x417924 SUB	%RDX,%RCX

0x417927 SHR	$0x1,%RCX

0x41792a ADD	%RDX,%RCX

0x41792d SHR	$0x3c,%RCX

0x417931 MOV	%RCX,%RAX

0x417934 SAL	$0x3d,%RAX

0x417938 SUB	%RAX,%RCX

0x41793b ADD	%RSI,%RCX

0x41793e IMUL	%RDI,%RCX

0x417942 MOV	%RCX,%RAX

0x417945 MUL	%R8

0x417948 MOV	%RCX,%RSI

0x41794b SUB	%RDX,%RSI

0x41794e SHR	$0x1,%RSI

0x417951 ADD	%RDX,%RSI

0x417954 SHR	$0x3c,%RSI

0x417958 MOV	%RSI,%RAX

0x41795b SAL	$0x3d,%RAX

0x41795f SUB	%RAX,%RSI

0x417962 ADD	%RCX,%RSI

0x417965 IMUL	%RDI,%RSI

0x417969 MOV	%RSI,%RAX

0x41796c MUL	%R8

0x41796f MOV	%RSI,%RCX

0x417972 SUB	%RDX,%RCX

0x417975 SHR	$0x1,%RCX

0x417978 ADD	%RDX,%RCX

0x41797b SHR	$0x3c,%RCX

0x41797f MOV	%RCX,%RAX

0x417982 SAL	$0x3d,%RAX

0x417986 SUB	%RAX,%RCX

0x417989 ADD	%RSI,%RCX

0x41798c IMUL	%RDI,%RCX

0x417990 MOV	%RCX,%RAX

0x417993 MUL	%R8

0x417996 MOV	%RCX,%RSI

0x417999 SUB	%RDX,%RSI

0x41799c SHR	$0x1,%RSI

0x41799f ADD	%RDX,%RSI

0x4179a2 SHR	$0x3c,%RSI

0x4179a6 MOV	%RSI,%RAX

0x4179a9 SAL	$0x3d,%RAX

0x4179ad SUB	%RAX,%RSI

0x4179b0 ADD	%RCX,%RSI

0x4179b3 IMUL	%RDI,%RSI

0x4179b7 MOV	%RSI,%RAX

0x4179ba MUL	%R8

0x4179bd MOV	%RSI,%RCX

0x4179c0 SUB	%RDX,%RCX

0x4179c3 SHR	$0x1,%RCX

0x4179c6 ADD	%RDX,%RCX

0x4179c9 SHR	$0x3c,%RCX

0x4179cd MOV	%RCX,%RAX

0x4179d0 SAL	$0x3d,%RAX

0x4179d4 SUB	%RAX,%RCX

0x4179d7 ADD	%RSI,%RCX

0x4179da IMUL	%RDI,%RCX

0x4179de MOV	%RCX,%RAX

0x4179e1 MUL	%R8

0x4179e4 MOV	%RCX,%RSI

0x4179e7 SUB	%RDX,%RSI

0x4179ea SHR	$0x1,%RSI

0x4179ed ADD	%RDX,%RSI

0x4179f0 SHR	$0x3c,%RSI

0x4179f4 MOV	%RSI,%RAX

0x4179f7 SAL	$0x3d,%RAX

0x4179fb SUB	%RAX,%RSI

0x4179fe ADD	%RCX,%RSI

0x417a01 IMUL	%RDI,%RSI

0x417a05 MOV	%RSI,%RAX

0x417a08 MUL	%R8

0x417a0b MOV	%RSI,%RCX

0x417a0e SUB	%RDX,%RCX

0x417a11 SHR	$0x1,%RCX

0x417a14 ADD	%RDX,%RCX

0x417a17 SHR	$0x3c,%RCX

0x417a1b MOV	%RCX,%RAX

0x417a1e SAL	$0x3d,%RAX

0x417a22 SUB	%RAX,%RCX

0x417a25 ADD	%RSI,%RCX

0x417a28 IMUL	%RDI,%RCX

0x417a2c MOV	%RCX,%RAX

0x417a2f MUL	%R8

0x417a32 MOV	%RCX,%RAX

0x417a35 SUB	%RDX,%RAX

0x417a38 SHR	$0x1,%RAX

0x417a3b ADD	%RDX,%RAX

0x417a3e SHR	$0x3c,%RAX

0x417a42 MOV	%RAX,%RDX

0x417a45 SAL	$0x3d,%RDX

0x417a49 SUB	%RDX,%RAX

0x417a4c ADD	%RCX,%RAX

0x417a4f POP	%RBP

0x417a50 RET

0x417a51 NOPW	%CS:(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	random.c:46-74
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46,66-74.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 32.00 to 3.56 cycles (8.98x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	131
nb uops	141
loop length	433
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	22.25	32.00	31.00	22.25	0.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	22.25	32.00	31.00	22.25	0.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.50
Dispatch	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.00 cycles. At this rate:

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4178a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0.17
IMUL $-0x61c8864f,%EDI,%EAX	1	0	1	0	0	0	3	1
ADD %EDI,%ESI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL $-0x61c8864f,%ESI,%ESI	1	0	1	0	0	0	3	1
SAL $0x20,%RAX	1	0	0.50	0.50	0	0	1	0.50
OR %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
MOV $0x613606df9756715,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.33
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV $0x9,%R8D	1	0.25	0.25	0.25	0.25	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RSI	1	0	0	0	0	0	0	0.17
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RSI	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RSI	1	0	0.50	0.50	0	0	1	0.50
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RSI	1	0	0	0	0	0	0	0.17
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RSI	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RSI	1	0	0.50	0.50	0	0	1	0.50
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RSI	1	0	0	0	0	0	0	0.17
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RSI	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RSI	1	0	0.50	0.50	0	0	1	0.50
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RSI	1	0	0	0	0	0	0	0.17
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RSI	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RSI	1	0	0.50	0.50	0	0	1	0.50
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RAX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RAX	1	0	0.50	0.50	0	0	1	0.50
MOV %RAX,%RDX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDX	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
POP %RBP	1	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	1	0.50

Source file and lines	random.c:46-74
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c:46,66-74.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

MUL: 10 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	131
nb uops	141
loop length	433
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.50 cycles
front end	23.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	22.25	32.00	31.00	22.25	0.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	22.25	32.00	31.00	22.25	0.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.50
Dispatch	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 32.00 cycles. At this rate:

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4178a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0.17
IMUL $-0x61c8864f,%EDI,%EAX	1	0	1	0	0	0	3	1
ADD %EDI,%ESI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL $-0x61c8864f,%ESI,%ESI	1	0	1	0	0	0	3	1
SAL $0x20,%RAX	1	0	0.50	0.50	0	0	1	0.50
OR %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
MOV $0x613606df9756715,%RDI	1	0.25	0.25	0.25	0.25	0	1	0.33
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV $0x9,%R8D	1	0.25	0.25	0.25	0.25	0	1	0.25
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RSI	1	0	0	0	0	0	0	0.17
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RSI	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RSI	1	0	0.50	0.50	0	0	1	0.50
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RSI	1	0	0	0	0	0	0	0.17
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RSI	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RSI	1	0	0.50	0.50	0	0	1	0.50
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RSI	1	0	0	0	0	0	0	0.17
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RSI	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RSI	1	0	0.50	0.50	0	0	1	0.50
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RSI	1	0	0	0	0	0	0	0.17
SUB %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RSI	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RSI	1	0	0.50	0.50	0	0	1	0.50
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RSI	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RSI	1	0	1	0	0	0	3	1
MOV %RSI,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RSI,%RCX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RCX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RCX	1	0	0.50	0.50	0	0	1	0.50
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RAX	1	0	0.50	0.50	0	0	1	0.50
SUB %RAX,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	1	0.25
IMUL %RDI,%RCX	1	0	1	0	0	0	3	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
MUL %R8	2	0	2	0	0	0	3-4	1
MOV %RCX,%RAX	1	0	0	0	0	0	0	0.17
SUB %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x1,%RAX	1	0	0.50	0.50	0	0	1	0.50
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
SHR $0x3c,%RAX	1	0	0.50	0.50	0	0	1	0.50
MOV %RAX,%RDX	1	0	0	0	0	0	0	0.17
SAL $0x3d,%RDX	1	0	0.50	0.50	0	0	1	0.50
SUB %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
ADD %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	1	0.25
POP %RBP	1	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	1	0.50

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	1	0	1.5	0	0.75	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.06	0.02
2x2	4	1	2	2	0.03	0.02
2x4	8	1.5	6	4	0.03	0.02
2x8	16	0.75	6	8	0.01	0.01
2x16	32	1	1	16	0	0.01
2x32	64	1	1	32	0.01	0.01
2x64	122	1	1	64	0.01	0.01
2x96	155	1	1	96	0	0.01

Name	Coverage (%)	Time (s)
○mkSeed.A	0.02	0.06

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency