OV - - Function ljForce.extracted.27

	Function: ljForce.extracted.27	Module: exec	Source: ljForce.c:157-161 [...]	Coverage: 0.27%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 23 - 23

--------------------------------------------------------------------------------

23:    a[1] = 0.0;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 157 - 161

--------------------------------------------------------------------------------

157:    #pragma omp parallel for

158:    for (int ii=0; ii<fSize; ++ii)

159:    {

160:       zeroReal3(s->atoms->f[ii]);

161:       s->atoms->U[ii] = 0.;

0x411210 PUSH	%RBP

0x411211 MOV	%RSP,%RBP

0x411214 PUSH	%R14

0x411216 PUSH	%RBX

0x411217 SUB	$0x10,%RSP

0x41121b MOV	%RDX,%R14

0x41121e MOVL	$0,-0x20(%RBP)

0x411225 MOV	(%RDI),%EBX

0x411227 MOVL	$0,-0x18(%RBP)

0x41122e MOV	%R8D,-0x14(%RBP)

0x411232 MOVL	$0x1,-0x1c(%RBP)

0x411239 SUB	$0x8,%RSP

0x41123d LEA	-0x1c(%RBP),%RAX

0x411241 LEA	-0x20(%RBP),%RCX

0x411245 LEA	-0x18(%RBP),%R8

0x411249 LEA	-0x14(%RBP),%R9

0x41124d MOV	$0x438930,%EDI

0x411252 MOV	%EBX,%ESI

0x411254 MOV	$0x22,%EDX

0x411259 PUSH	$0x1

0x41125b PUSH	$0x1

0x41125d PUSH	%RAX

0x41125e CALL	405320 <__kmpc_for_static_init_4@plt>

0x411263 ADD	$0x20,%RSP

0x411267 MOV	-0x18(%RBP),%EAX

0x41126a MOV	-0x14(%RBP),%R8D

0x41126e CMP	%R8D,%EAX

0x411271 JA	411467

0x411277 MOV	0x20(%R14),%RCX

0x41127b MOV	0x28(%RCX),%RDX

0x41127f MOV	0x30(%RCX),%RCX

0x411283 MOV	%R8,%RSI

0x411286 SUB	%RAX,%RSI

0x411289 LEA	0x1(%RSI),%RDI

0x41128d CMP	$0xc,%RDI

0x411291 JBE	41135a

0x411297 MOV	%RDI,%R8

0x41129a SHR	$0x3,%R8

0x41129e LEA	(%RAX,%RAX,2),%R9

0x4112a2 LEA	(%RDX,%R9,8),%R9

0x4112a6 XORPS	%XMM0,%XMM0

0x4112a9 NOPL	(%RAX)

(147) 0x4112b0 MOVUPS	%XMM0,(%R9)

(147) 0x4112b4 MOVQ	$0,0x10(%R9)

(147) 0x4112bc MOVUPS	%XMM0,0x18(%R9)

(147) 0x4112c1 MOVQ	$0,0x28(%R9)

(147) 0x4112c9 MOVUPS	%XMM0,0x30(%R9)

(147) 0x4112ce MOVQ	$0,0x40(%R9)

(147) 0x4112d6 MOVUPS	%XMM0,0x48(%R9)

(147) 0x4112db MOVQ	$0,0x58(%R9)

(147) 0x4112e3 MOVUPS	%XMM0,0x60(%R9)

(147) 0x4112e8 MOVQ	$0,0x70(%R9)

(147) 0x4112f0 MOVUPS	%XMM0,0x78(%R9)

(147) 0x4112f5 MOVQ	$0,0x88(%R9)

(147) 0x411300 MOVUPS	%XMM0,0x90(%R9)

(147) 0x411308 MOVQ	$0,0xa0(%R9)

(147) 0x411313 MOVUPS	%XMM0,0xa8(%R9)

(147) 0x41131b MOVQ	$0,0xb8(%R9)

(147) 0x411326 ADD	$0xc0,%R9

(147) 0x41132d DEC	%R8

(147) 0x411330 JNE	4112b0

0x411336 AND	$-0x8,%RDI

0x41133a MOV	%RSI,%R8

0x41133d SUB	%RDI,%R8

0x411340 CMP	$0x6,%R8

0x411344 JA	411454

0x41134a JMP	0x42d050(,%R8,8)

0x411352 ADD	%RAX,%RDI

0x411355 JMP	411440

0x41135a INC	%R8

0x41135d LEA	(%RAX,%RAX,2),%RSI

0x411361 LEA	(%RDX,%RSI,8),%RDX

0x411365 XORPS	%XMM0,%XMM0

0x411368 NOPL	(%RAX,%RAX,1)

(146) 0x411370 MOVUPS	%XMM0,(%RDX)

(146) 0x411373 MOVQ	$0,0x10(%RDX)

(146) 0x41137b MOVQ	$0,(%RCX,%RAX,8)

(146) 0x411383 INC	%RAX

(146) 0x411386 ADD	$0x18,%RDX

(146) 0x41138a CMP	%RAX,%R8

(146) 0x41138d JNE	411370

0x41138f JMP	411467

0x411394 ADD	%RAX,%RDI

0x411397 JMP	41142a

0x41139c ADD	%RAX,%RDI

0x41139f JMP	411414

0x4113a1 ADD	%RAX,%RDI

0x4113a4 JMP	4113fe

0x4113a6 ADD	%RAX,%RDI

0x4113a9 JMP	4113e8

0x4113ab ADD	%RAX,%RDI

0x4113ae JMP	4113cf

0x4113b0 ADD	%RAX,%RDI

0x4113b3 LEA	(%RDI,%RDI,2),%R8

0x4113b7 XORPS	%XMM0,%XMM0

0x4113ba MOVUPS	%XMM0,0x90(%RDX,%R8,8)

0x4113c3 MOVQ	$0,0xa0(%RDX,%R8,8)

0x4113cf LEA	(%RDI,%RDI,2),%R8

0x4113d3 XORPS	%XMM0,%XMM0

0x4113d6 MOVUPS	%XMM0,0x78(%RDX,%R8,8)

0x4113dc MOVQ	$0,0x88(%RDX,%R8,8)

0x4113e8 LEA	(%RDI,%RDI,2),%R8

0x4113ec XORPS	%XMM0,%XMM0

0x4113ef MOVUPS	%XMM0,0x60(%RDX,%R8,8)

0x4113f5 MOVQ	$0,0x70(%RDX,%R8,8)

0x4113fe LEA	(%RDI,%RDI,2),%R8

0x411402 XORPS	%XMM0,%XMM0

0x411405 MOVUPS	%XMM0,0x48(%RDX,%R8,8)

0x41140b MOVQ	$0,0x58(%RDX,%R8,8)

0x411414 LEA	(%RDI,%RDI,2),%R8

0x411418 XORPS	%XMM0,%XMM0

0x41141b MOVUPS	%XMM0,0x30(%RDX,%R8,8)

0x411421 MOVQ	$0,0x40(%RDX,%R8,8)

0x41142a LEA	(%RDI,%RDI,2),%R8

0x41142e XORPS	%XMM0,%XMM0

0x411431 MOVUPS	%XMM0,0x18(%RDX,%R8,8)

0x411437 MOVQ	$0,0x28(%RDX,%R8,8)

0x411440 LEA	(%RDI,%RDI,2),%RDI

0x411444 XORPS	%XMM0,%XMM0

0x411447 MOVUPS	%XMM0,(%RDX,%RDI,8)

0x41144b MOVQ	$0,0x10(%RDX,%RDI,8)

0x411454 LEA	(%RCX,%RAX,8),%RDI

0x411458 LEA	0x8(,%RSI,8),%RDX

0x411460 XOR	%ESI,%ESI

0x411462 CALL	41c040 <_intel_fast_memset>

0x411467 MOV	$0x438950,%EDI

0x41146c MOV	%EBX,%ESI

0x41146e ADD	$0x10,%RSP

0x411472 POP	%RBX

0x411473 POP	%R14

0x411475 POP	%RBP

0x411476 JMP	405150

0x41147b NOPL	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.83 to 3.83 cycles (4.65x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 17.83 to 1.35 cycles (13.17x speedup).

Details

51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
38% of SSE/AVX stores are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_4@plt: 1 occurrences
_intel_fast_memset: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences

Vector unaligned load/store instructions

Detected 7 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 7 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	107
nb uops	107
loop length	459
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.83 cycles
front end	17.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.75	11.75	11.75	11.75	7.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	3.50	3.50
cycles	11.75	11.75	11.75	11.75	7.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.83
Dispatch	11.75
Overall L1	17.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	51%
load	0%
store	38%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Vector efficiency ratios

INT

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	16%
load	6%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.83 cycles. At this rate:

2% of peak load performance is reached (2.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.32 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.83 to 11.75 cycles (1.52x speedup).

ASM code

In the binary file, the address of the function is: 411210

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVL $0,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R8D,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVL $0x1,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x1c(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x20(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x18(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x14(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x438930,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 405320 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x18(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x14(%RBP),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 411467 <ljForce.extracted.27+0x257>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x20(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x28(%RCX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x30(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA 0x1(%RSI),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0xc,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JBE 41135a <ljForce.extracted.27+0x14a>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LEA (%RAX,%RAX,2),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDX,%R9,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x6,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 411454 <ljForce.extracted.27+0x244>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
JMP 0x42d050(,%R8,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 411440 <ljForce.extracted.27+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RAX,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDX,%RSI,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 411467 <ljForce.extracted.27+0x257>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 41142a <ljForce.extracted.27+0x21a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 411414 <ljForce.extracted.27+0x204>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4113fe <ljForce.extracted.27+0x1ee>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4113e8 <ljForce.extracted.27+0x1d8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4113cf <ljForce.extracted.27+0x1bf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x90(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0xa0(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x78(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x88(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x60(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x70(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x48(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x58(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x30(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x40(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x18(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x28(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,(%RDX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x10(%RDX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RCX,%RAX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA 0x8(,%RSI,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
CALL 41c040 <_intel_fast_memset>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV $0x438950,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 405150 <__kmpc_for_static_fini@plt>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	ljForce.c:157-161
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:23
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:157-161

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.83 to 3.83 cycles (4.65x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
38% of SSE/AVX stores are used in vector version.
75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_4@plt: 1 occurrences
_intel_fast_memset: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences

Vector unaligned load/store instructions

Detected 7 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 7 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 44 bytes. The binary function is storing 184 bytes.

General properties

nb instructions	107
nb uops	107
loop length	459
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.83 cycles
front end	17.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	11.75	11.75	11.75	11.75	7.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	3.50	3.50
cycles	11.75	11.75	11.75	11.75	7.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.83
Dispatch	11.75
Overall L1	17.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	51%
load	0%
store	38%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Vector efficiency ratios

INT

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	16%
load	6%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.83 cycles. At this rate:

2% of peak load performance is reached (2.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (10.32 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 411210

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVL $0,-0x20(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV (%RDI),%EBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVL $0,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %R8D,-0x14(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVL $0x1,-0x1c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
SUB $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x1c(%RBP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x20(%RBP),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x18(%RBP),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA -0x14(%RBP),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x438930,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x22,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
CALL 405320 <__kmpc_for_static_init_4@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
ADD $0x20,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV -0x18(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV -0x14(%RBP),%R8D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %R8D,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 411467 <ljForce.extracted.27+0x257>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x20(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x28(%RCX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x30(%RCX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA 0x1(%RSI),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0xc,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JBE 41135a <ljForce.extracted.27+0x14a>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%R8	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LEA (%RAX,%RAX,2),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDX,%R9,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
AND $-0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RDI,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x6,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 411454 <ljForce.extracted.27+0x244>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
JMP 0x42d050(,%R8,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 411440 <ljForce.extracted.27+0x230>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
INC %R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RAX,%RAX,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDX,%RSI,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
JMP 411467 <ljForce.extracted.27+0x257>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 41142a <ljForce.extracted.27+0x21a>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 411414 <ljForce.extracted.27+0x204>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4113fe <ljForce.extracted.27+0x1ee>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4113e8 <ljForce.extracted.27+0x1d8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4113cf <ljForce.extracted.27+0x1bf>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RAX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x90(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0xa0(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x78(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x88(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x60(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x70(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x48(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x58(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x30(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x40(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x18(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x28(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RDI,%RDI,2),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,(%RDX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVQ $0,0x10(%RDX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
LEA (%RCX,%RAX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA 0x8(,%RSI,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.25
CALL 41c040 <_intel_fast_memset>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV $0x438950,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 405150 <__kmpc_for_static_fini@plt>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.74	0.1	0.45	0.3	0.3	0.54	0.21	0.73	0.19	0.58	0.11	0.78	0.14	0.44

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.79	0.27
2x2	4	0.74	1.47	2	0.68	0.36
2x4	8	0.45	1.81	4	0.61	0.54
2x8	16	0.3	2.36	8	0.74	0.77
2x16	32	0.21	3.39	16	0.47	0.92
2x32	64	0.19	6	32	0.25	0.72
2x64	128	0.11	7.09	64	0.22	0.88
2x96	192	0.14	13	96	0.15	0.51

Name	Coverage (%)	Time (s)
▼ljForce.extracted.27–	0.27	0.78
○Loop 147 - ljForce.c:157-158 - exec	0.27	0.77
○Loop 146 - ljForce.c:158-161 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency