OV - - Function updateLinkCells.A

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 288 - 385

--------------------------------------------------------------------------------

288: {

289:    emptyHaloCells(boxes);

290:

291:    for (int iBox=0; iBox<boxes->nLocalBoxes; ++iBox)

292:    {

293:       int iOff = iBox*MAXATOMS;

294:       int ii=0;

295:       while (ii < boxes->nAtoms[iBox])

296:       {

297:          int jBox = getBoxFromCoord(boxes, atoms->r[iOff+ii]);

298:          if (jBox != iBox)

299:             moveAtom(boxes, atoms, ii, iBox, jBox);

300:          else

301:             ++ii;

302:       }

303:    }

304: }

[...]

352:    int ix = (int)(floor((rr[0] - localMin[0])*boxes->invBoxSize[0]));

353:    int iy = (int)(floor((rr[1] - localMin[1])*boxes->invBoxSize[1]));

354:    int iz = (int)(floor((rr[2] - localMin[2])*boxes->invBoxSize[2]));

355:

356:

357:    // For each axis, if we are inside the local domain, make sure we get

358:    // a local link cell.  Otherwise, make sure we get a halo link cell.

359:    if (rr[0] < localMax[0])

360:    {

361:       if (ix == gridSize[0]) ix = gridSize[0] - 1;

362:    }

363:    else

364:       ix = gridSize[0]; // assign to halo cell

365:    if (rr[1] < localMax[1])

[...]

371:    if (rr[2] < localMax[2])

[...]

378:    return getBoxFromTuple(boxes, ix, iy, iz);

[...]

384:    for (int ii=boxes->nLocalBoxes; ii<boxes->nTotalBoxes; ++ii)

385:       boxes->nAtoms[ii] = 0;

0x40f990 PUSH	%RBP

0x40f991 MOV	%RSP,%RBP

0x40f994 PUSH	%R15

0x40f996 PUSH	%R14

0x40f998 PUSH	%R13

0x40f99a PUSH	%R12

0x40f99c PUSH	%RBX

0x40f99d SUB	$0x48,%RSP

0x40f9a1 MOV	%RSI,%RBX

0x40f9a4 MOV	%RDI,%R14

0x40f9a7 MOV	0xc(%RDI),%EAX

0x40f9aa CMP	0x14(%RDI),%EAX

0x40f9ad JGE	40f9d7

0x40f9af CLTQ

0x40f9b1 MOV	0x78(%R14),%RCX

0x40f9b5 NOPW	%CS:(%RAX,%RAX,1)

(132) 0x40f9c0 MOVL	$0,(%RCX,%RAX,4)

(132) 0x40f9c7 INC	%RAX

(132) 0x40f9ca MOVSXD	0x14(%R14),%RDX

(132) 0x40f9ce CMP	%RDX,%RAX

(132) 0x40f9d1 JL	40f9c0

0x40f9d3 MOV	0xc(%R14),%EAX

0x40f9d7 TEST	%EAX,%EAX

0x40f9d9 JLE	40fb6c

0x40f9df MOV	0x78(%R14),%RCX

0x40f9e3 XOR	%R15D,%R15D

0x40f9e6 JMP	40fa03

0x40f9e8 NOPL	(%RAX,%RAX,1)

(130) 0x40f9f0 MOV	0xc(%R14),%EAX

(130) 0x40f9f4 INC	%R15

(130) 0x40f9f7 MOVSXD	%EAX,%RDX

(130) 0x40f9fa CMP	%RDX,%R15

(130) 0x40f9fd JGE	40fb6c

(130) 0x40fa03 CMPL	$0,(%RCX,%R15,4)

(130) 0x40fa08 JLE	40f9f4

(130) 0x40fa0a MOV	%R15D,%R13D

(130) 0x40fa0d SAL	$0x6,%R13D

(130) 0x40fa11 XOR	%R12D,%R12D

(130) 0x40fa14 JMP	40fa2d

0x40fa16 NOPW	%CS:(%RAX,%RAX,1)

  (131) 0x40fa20 INC	%R12D

  (131) 0x40fa23 MOV	0x78(%R14),%RCX

  (131) 0x40fa27 CMP	(%RCX,%R15,4),%R12D

  (131) 0x40fa2b JGE	40f9f0

  (131) 0x40fa2d MOV	0x18(%RBX),%RAX

  (131) 0x40fa31 LEA	(%R12,%R13,1),%ECX

  (131) 0x40fa35 MOVSXD	%ECX,%RCX

  (131) 0x40fa38 LEA	(%RCX,%RCX,2),%RCX

  (131) 0x40fa3c MOVSD	(%RAX,%RCX,8),%XMM0

  (131) 0x40fa41 MOVSD	%XMM0,-0x68(%RBP)

  (131) 0x40fa46 MOVUPD	0x8(%RAX,%RCX,8),%XMM2

  (131) 0x40fa4c MOVUPD	0x20(%R14),%XMM0

  (131) 0x40fa52 MOVUPD	0x68(%R14),%XMM1

  (131) 0x40fa58 MOVAPD	%XMM2,-0x60(%RBP)

  (131) 0x40fa5d SUBPD	%XMM0,%XMM2

  (131) 0x40fa61 MULPD	%XMM1,%XMM2

  (131) 0x40fa65 MOVAPD	%XMM2,-0x40(%RBP)

  (131) 0x40fa6a MOVAPD	%XMM2,%XMM0

  (131) 0x40fa6e CALL	418d00 <floor>

  (131) 0x40fa73 MOVAPD	%XMM0,-0x50(%RBP)

  (131) 0x40fa78 MOVAPD	-0x40(%RBP),%XMM0

  (131) 0x40fa7d UNPCKHPD	%XMM0,%XMM0

  (131) 0x40fa81 CALL	418d00 <floor>

  (131) 0x40fa86 MOVSD	-0x68(%RBP),%XMM1

  (131) 0x40fa8b UCOMISD	0x30(%R14),%XMM1

  (131) 0x40fa91 JAE	40fad0

  (131) 0x40fa93 MOVAPD	%XMM0,-0x40(%RBP)

  (131) 0x40fa98 SUBSD	0x18(%R14),%XMM1

  (131) 0x40fa9e MULSD	0x60(%R14),%XMM1

  (131) 0x40faa4 MOVAPD	%XMM1,%XMM0

  (131) 0x40faa8 CALL	418d00 <floor>

  (131) 0x40faad CVTTSD2SI	%XMM0,%ESI

  (131) 0x40fab1 MOV	(%R14),%EAX

  (131) 0x40fab4 CMP	%ESI,%EAX

  (131) 0x40fab6 JNE	40fabc

  (131) 0x40fab8 DEC	%EAX

  (131) 0x40faba MOV	%EAX,%ESI

  (131) 0x40fabc MOVAPD	-0x60(%RBP),%XMM2

  (131) 0x40fac1 MOVAPD	-0x50(%RBP),%XMM1

  (131) 0x40fac6 MOVAPD	-0x40(%RBP),%XMM0

  (131) 0x40facb JMP	40fadd

0x40facd NOPL	(%RAX)

  (131) 0x40fad0 MOV	(%R14),%ESI

  (131) 0x40fad3 MOVAPD	-0x60(%RBP),%XMM2

  (131) 0x40fad8 MOVAPD	-0x50(%RBP),%XMM1

  (131) 0x40fadd UNPCKLPD	%XMM0,%XMM1

  (131) 0x40fae1 CVTTPD2DQ	%XMM1,%XMM0

  (131) 0x40fae5 MOV	0x4(%R14),%RCX

  (131) 0x40fae9 MOVQ	%RCX,%XMM1

  (131) 0x40faee PCMPEQD	%XMM0,%XMM1

  (131) 0x40faf2 PSHUFD	$0x50,%XMM1,%XMM1

  (131) 0x40faf7 MOVMSKPD	%XMM1,%EAX

  (131) 0x40fafb TEST	$0x1,%AL

  (131) 0x40fafd JNE	40fb10

  (131) 0x40faff MOVD	%XMM0,%EDX

  (131) 0x40fb03 JMP	40fb13

0x40fb05 NOPW	%CS:(%RAX,%RAX,1)

  (131) 0x40fb10 LEA	-0x1(%RCX),%EDX

  (131) 0x40fb13 UCOMISD	0x38(%R14),%XMM2

  (131) 0x40fb19 CMOVAE	%ECX,%EDX

  (131) 0x40fb1c SHR	$0x20,%RCX

  (131) 0x40fb20 TEST	$0x2,%AL

  (131) 0x40fb22 JNE	40fb30

  (131) 0x40fb24 PSHUFD	$0x55,%XMM0,%XMM0

  (131) 0x40fb29 MOVD	%XMM0,%EAX

  (131) 0x40fb2d JMP	40fb33

0x40fb2f NOP

  (131) 0x40fb30 LEA	-0x1(%RCX),%EAX

  (131) 0x40fb33 UNPCKHPD	%XMM2,%XMM2

  (131) 0x40fb37 UCOMISD	0x40(%R14),%XMM2

  (131) 0x40fb3d CMOVB	%EAX,%ECX

  (131) 0x40fb40 MOV	%R14,%RDI

  (131) 0x40fb43 CALL	40f540 <getBoxFromTuple.A>

  (131) 0x40fb48 MOV	%EAX,%ECX

  (131) 0x40fb4a CMP	%RCX,%R15

  (131) 0x40fb4d JE	40fa20

  (131) 0x40fb53 MOV	%R14,%RDI

  (131) 0x40fb56 MOV	%RBX,%RSI

  (131) 0x40fb59 MOV	%R12D,%EDX

  (131) 0x40fb5c MOV	%R15D,%ECX

  (131) 0x40fb5f MOV	%EAX,%R8D

  (131) 0x40fb62 CALL	40f810 <moveAtom.A>

  (131) 0x40fb67 JMP	40fa23

0x40fb6c ADD	$0x48,%RSP

0x40fb70 POP	%RBX

0x40fb71 POP	%R12

0x40fb73 POP	%R13

0x40fb75 POP	%R14

0x40fb77 POP	%R15

0x40fb79 POP	%RBP

0x40fb7a RET

0x40fb7b NOPL	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	linkCells.c:288-385
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:288-304,352-365,371,378,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 4.67 to 0.32 cycles (14.77x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	36
nb uops	28
loop length	122
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.67 cycles
front end	4.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	1.50	1.25	1.25	2.00	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.00	1.50	1.25	1.25	2.00	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.67
Dispatch	2.00
Overall L1	4.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.67 cycles. At this rate:

6% of peak load performance is reached (6.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.67 to 2.00 cycles (2.33x speedup).

ASM code

In the binary file, the address of the function is: 40f990

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP 0x14(%RDI),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40f9d7 <updateLinkCells.A+0x47>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CLTQ
MOV 0x78(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 40fb6c <updateLinkCells.A+0x1dc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x78(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 40fa03 <updateLinkCells.A+0x73>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	linkCells.c:288-385
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:288-304,352-365,371,378,384-385.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 4.67 to 0.32 cycles (14.77x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes.

General properties

nb instructions	36
nb uops	28
loop length	122
used x86 registers	11
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.67 cycles
front end	4.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.00	1.50	1.25	1.25	2.00	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.00	1.50	1.25	1.25	2.00	1.67	1.67	1.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.67
Dispatch	2.00
Overall L1	4.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.67 cycles. At this rate:

6% of peak load performance is reached (6.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.67 to 2.00 cycles (2.33x speedup).

ASM code

In the binary file, the address of the function is: 40f990

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0xc(%RDI),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
CMP 0x14(%RDI),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JGE 40f9d7 <updateLinkCells.A+0x47>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CLTQ
MOV 0x78(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV 0xc(%R14),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 40fb6c <updateLinkCells.A+0x1dc>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV 0x78(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 40fa03 <updateLinkCells.A+0x73>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x48,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.81	0.19	0.66	0.38	0.74	0.25	0.76	0.2	0.63	0.24	0.76	0.1	0.63	0.13

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	2.42	0.83
2x2	2	0.81	1.61	2	3.57	1
2x4	2	0.66	2.66	4	4.24	1.14
2x8	2	0.74	5.9	8	3.58	0.94
2x16	2	0.76	12.1	16	3.56	0.8
2x32	2	0.63	20.17	32	4.44	0.66
2x64	2	0.76	48.4	64	3.62	0.43
2x96	2	0.63	60.5	96	4.1	0.35

Name	Coverage (%)	Time (s)
▼updateLinkCells.A–	0.83	2.42
○Loop 132 - linkCells.c:384-385 - exec	0	0
▼Loop 130 - linkCells.c:291-378 - exec–	0	0.01
○Loop 131 - linkCells.c:295-378 - exec	0.83	2.41

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency