OV - - Function moveAtom.A

	Function: moveAtom.A	Module: exec	Source: linkCells.c:257-334 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c: 257 - 334

--------------------------------------------------------------------------------

257: {

258:    int nj = boxes->nAtoms[jBox];

259:    copyAtom(boxes, atoms, iId, iBox, nj, jBox);

260:    boxes->nAtoms[jBox]++;

261:

262:    assert(boxes->nAtoms[jBox] < MAXATOMS);

263:

264:    boxes->nAtoms[iBox]--;

265:    int ni = boxes->nAtoms[iBox];

266:    if (ni) copyAtom(boxes, atoms, ni, iBox, iId, iBox);

267:

268:    if (jBox > boxes->nLocalBoxes)

269:       --atoms->nLocal;

270:

271:    return;

272: }

[...]

327:    const int iOff = MAXATOMS*iBox+iAtom;

328:    const int jOff = MAXATOMS*jBox+jAtom;

329:    atoms->gid[jOff] = atoms->gid[iOff];

330:    atoms->iSpecies[jOff] = atoms->iSpecies[iOff];

331:    memcpy(atoms->r[jOff], atoms->r[iOff], sizeof(real3));

332:    memcpy(atoms->p[jOff], atoms->p[iOff], sizeof(real3));

333:    memcpy(atoms->f[jOff], atoms->f[iOff], sizeof(real3));

334:    memcpy(atoms->U+jOff,  atoms->U+iOff,  sizeof(real_t));

0x40f810 PUSH	%RBP

0x40f811 MOV	%RSP,%RBP

0x40f814 PUSH	%R15

0x40f816 PUSH	%R14

0x40f818 PUSH	%RBX

0x40f819 PUSH	%RAX

0x40f81a MOV	0x78(%RDI),%RAX

0x40f81e MOVSXD	%R8D,%R11

0x40f821 MOVSXD	(%RAX,%R11,4),%RAX

0x40f825 MOVSXD	%ECX,%R10

0x40f828 MOV	%R10,%R9

0x40f82b SAL	$0x6,%R9

0x40f82f ADD	%R9D,%EDX

0x40f832 MOV	%R11,%RBX

0x40f835 SAL	$0x6,%RBX

0x40f839 ADD	%RAX,%RBX

0x40f83c MOV	0x8(%RSI),%RCX

0x40f840 MOVSXD	%EDX,%RAX

0x40f843 MOV	(%RCX,%RAX,4),%EDX

0x40f846 MOV	%EDX,(%RCX,%RBX,4)

0x40f849 MOV	0x10(%RSI),%RCX

0x40f84d MOV	(%RCX,%RAX,4),%EDX

0x40f850 MOV	%EDX,(%RCX,%RBX,4)

0x40f853 MOV	0x18(%RSI),%RDX

0x40f857 LEA	(,%RBX,8),%RCX

0x40f85f LEA	(%RCX,%RCX,2),%R14

0x40f863 LEA	(,%RAX,8),%RCX

0x40f86b LEA	(%RCX,%RCX,2),%RCX

0x40f86f MOV	0x10(%RDX,%RCX,1),%R15

0x40f874 MOV	%R15,0x10(%RDX,%R14,1)

0x40f879 MOVUPS	(%RDX,%RCX,1),%XMM0

0x40f87d MOVUPS	%XMM0,(%RDX,%R14,1)

0x40f882 MOV	0x20(%RSI),%RDX

0x40f886 MOV	0x10(%RDX,%RCX,1),%R15

0x40f88b MOV	%R15,0x10(%RDX,%R14,1)

0x40f890 MOVUPS	(%RDX,%RCX,1),%XMM0

0x40f894 MOVUPS	%XMM0,(%RDX,%R14,1)

0x40f899 MOV	0x28(%RSI),%RDX

0x40f89d MOV	0x10(%RDX,%RCX,1),%R15

0x40f8a2 MOV	%R15,0x10(%RDX,%R14,1)

0x40f8a7 MOVUPS	(%RDX,%RCX,1),%XMM0

0x40f8ab MOVUPS	%XMM0,(%RDX,%R14,1)

0x40f8b0 MOV	0x30(%RSI),%RDX

0x40f8b4 MOV	(%RDX,%RAX,8),%R14

0x40f8b8 MOV	%R14,(%RDX,%RBX,8)

0x40f8bc MOV	0x78(%RDI),%RBX

0x40f8c0 MOV	(%RBX,%R11,4),%EDX

0x40f8c4 LEA	0x1(%RDX),%R14D

0x40f8c8 MOV	%R14D,(%RBX,%R11,4)

0x40f8cc CMP	$0x3f,%EDX

0x40f8cf JGE	40f972

0x40f8d5 MOVSXD	(%RBX,%R10,4),%RDX

0x40f8d9 DEC	%RDX

0x40f8dc MOV	%EDX,(%RBX,%R10,4)

0x40f8e0 TEST	%EDX,%EDX

0x40f8e2 JE	40f95f

0x40f8e4 ADD	%R9,%RDX

0x40f8e7 MOV	0x8(%RSI),%R9

0x40f8eb MOV	(%R9,%RDX,4),%R10D

0x40f8ef MOV	%R10D,(%R9,%RAX,4)

0x40f8f3 MOV	0x10(%RSI),%R9

0x40f8f7 MOV	(%R9,%RDX,4),%R10D

0x40f8fb MOV	%R10D,(%R9,%RAX,4)

0x40f8ff MOV	0x18(%RSI),%R9

0x40f903 LEA	(,%RDX,8),%R10

0x40f90b LEA	(%R10,%R10,2),%R10

0x40f90f MOV	0x10(%R9,%R10,1),%R11

0x40f914 MOV	%R11,0x10(%R9,%RCX,1)

0x40f919 MOVUPS	(%R9,%R10,1),%XMM0

0x40f91e MOVUPS	%XMM0,(%R9,%RCX,1)

0x40f923 MOV	0x20(%RSI),%R9

0x40f927 MOV	0x10(%R9,%R10,1),%R11

0x40f92c MOV	%R11,0x10(%R9,%RCX,1)

0x40f931 MOVUPS	(%R9,%R10,1),%XMM0

0x40f936 MOVUPS	%XMM0,(%R9,%RCX,1)

0x40f93b MOV	0x28(%RSI),%R9

0x40f93f MOV	0x10(%R9,%R10,1),%R11

0x40f944 MOV	%R11,0x10(%R9,%RCX,1)

0x40f949 MOVUPS	(%R9,%R10,1),%XMM0

0x40f94e MOVUPS	%XMM0,(%R9,%RCX,1)

0x40f953 MOV	0x30(%RSI),%RCX

0x40f957 MOV	(%RCX,%RDX,8),%RDX

0x40f95b MOV	%RDX,(%RCX,%RAX,8)

0x40f95f CMP	%R8D,0xc(%RDI)

0x40f963 JGE	40f967

0x40f965 DECL	(%RSI)

0x40f967 ADD	$0x8,%RSP

0x40f96b POP	%RBX

0x40f96c POP	%R14

0x40f96e POP	%R15

0x40f970 POP	%RBP

0x40f971 RET

0x40f972 MOV	$0x42cfbe,%EDI

0x40f977 MOV	$0x42ce87,%ESI

0x40f97c MOV	$0x42cfdd,%ECX

0x40f981 MOV	$0x106,%EDX

0x40f986 CALL	405100 <__assert_fail@plt>

0x40f98b NOPL	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	linkCells.c:257-334
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:257-272,327-334.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This function has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.33 to 4.67 cycles (4.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 19.33 to 4.25 cycles (4.55x speedup).

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

54% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 19.33 to 16.50 cycles (1.17x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__assert_fail@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences

Vector unaligned load/store instructions

Detected 12 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 12 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 308 bytes. The binary function is storing 188 bytes.

General properties

nb instructions	98
nb uops	99
loop length	384
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.50	7.50	7.25	7.25	2.50	19.33	19.33	19.33	0.00	0.00	0.00	0.00	3.00	3.00
cycles	7.50	7.50	7.25	7.25	2.50	19.33	19.33	19.33	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.50
Dispatch	19.33
Overall L1	19.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	35%
load	54%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	18%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.33 cycles. At this rate:

16% of peak load performance is reached (15.93 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (9.72 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40f810

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x78(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSXD %R8D,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD (%RAX,%R11,4),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOVSXD %ECX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD %R9D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R11,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x8(%RSI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSXD %EDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%RCX,%RAX,4),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %EDX,(%RCX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x10(%RSI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RCX,%RAX,4),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %EDX,(%RCX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x18(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (,%RBX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RCX,2),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (,%RAX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x10(%RDX,%RCX,1),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,0x10(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%RDX,%RCX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x20(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RDX,%RCX,1),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,0x10(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%RDX,%RCX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x28(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RDX,%RCX,1),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,0x10(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%RDX,%RCX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x30(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDX,%RAX,8),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R14,(%RDX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x78(%RDI),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RBX,%R11,4),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA 0x1(%RDX),%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R14D,(%RBX,%R11,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP $0x3f,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JGE 40f972 <moveAtom.A+0x162>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOVSXD (%RBX,%R10,4),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
DEC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EDX,(%RBX,%R10,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 40f95f <moveAtom.A+0x14f>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x8(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%R9,%RDX,4),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10D,(%R9,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x10(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%R9,%RDX,4),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10D,(%R9,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x18(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (,%RDX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%R10,%R10,2),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x10(%R9,%R10,1),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R11,0x10(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%R9,%R10,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x20(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%R9,%R10,1),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R11,0x10(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%R9,%R10,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x28(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%R9,%R10,1),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R11,0x10(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%R9,%R10,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x30(%RSI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RCX,%RDX,8),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RDX,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP %R8D,0xc(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JGE 40f967 <moveAtom.A+0x157>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
DECL (%RSI)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
MOV $0x42cfbe,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x42ce87,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x42cfdd,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x106,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 405100 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	linkCells.c:257-334
Module	exec

The function is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/linkCells.c:257-272,327-334.

Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.33 to 4.67 cycles (4.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

35% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

54% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 19.33 to 16.50 cycles (1.17x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

__assert_fail@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DEC: 1 occurrences

Vector unaligned load/store instructions

Detected 12 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 12 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 308 bytes. The binary function is storing 188 bytes.

General properties

nb instructions	98
nb uops	99
loop length	384
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	7.50	7.50	7.25	7.25	2.50	19.33	19.33	19.33	0.00	0.00	0.00	0.00	3.00	3.00
cycles	7.50	7.50	7.25	7.25	2.50	19.33	19.33	19.33	0.00	0.00	0.00	0.00	3.00	3.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.50
Dispatch	19.33
Overall L1	19.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	35%
load	54%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	10%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	15%
load	18%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.33 cycles. At this rate:

16% of peak load performance is reached (15.93 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (9.72 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 40f810

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV 0x78(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSXD %R8D,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD (%RAX,%R11,4),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOVSXD %ECX,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD %R9D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R11,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAL $0x6,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD %RAX,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x8(%RSI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOVSXD %EDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%RCX,%RAX,4),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %EDX,(%RCX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x10(%RSI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RCX,%RAX,4),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %EDX,(%RCX,%RBX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x18(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (,%RBX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RCX,2),%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (,%RAX,8),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RCX,%RCX,2),%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x10(%RDX,%RCX,1),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,0x10(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%RDX,%RCX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x20(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RDX,%RCX,1),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,0x10(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%RDX,%RCX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x28(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RDX,%RCX,1),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,0x10(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%RDX,%RCX,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%RDX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x30(%RSI),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RDX,%RAX,8),%R14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R14,(%RDX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x78(%RDI),%RBX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RBX,%R11,4),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA 0x1(%RDX),%R14D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R14D,(%RBX,%R11,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP $0x3f,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JGE 40f972 <moveAtom.A+0x162>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOVSXD (%RBX,%R10,4),%RDX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
DEC %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EDX,(%RBX,%R10,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
TEST %EDX,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 40f95f <moveAtom.A+0x14f>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x8(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%R9,%RDX,4),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10D,(%R9,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x10(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%R9,%RDX,4),%R10D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R10D,(%R9,%RAX,4)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x18(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (,%RDX,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%R10,%R10,2),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x10(%R9,%R10,1),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R11,0x10(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%R9,%R10,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x20(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%R9,%R10,1),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R11,0x10(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%R9,%R10,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x28(%RSI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%R9,%R10,1),%R11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R11,0x10(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVUPS (%R9,%R10,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,(%R9,%RCX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOV 0x30(%RSI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV (%RCX,%RDX,8),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %RDX,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP %R8D,0xc(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JGE 40f967 <moveAtom.A+0x157>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
DECL (%RSI)	2	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.50
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
MOV $0x42cfbe,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x42ce87,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x42cfdd,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x106,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 405100 <__assert_fail@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/icx_6/oneview_run_1708509234I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spreadOMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x4	OMP_NUM_THREADS: 4I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x8	OMP_NUM_THREADS: 8I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x16	OMP_NUM_THREADS: 16I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x32	OMP_NUM_THREADS: 32I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x64	OMP_NUM_THREADS: 64I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread
Run 2x96	OMP_NUM_THREADS: 96I_MPI_PIN_DOMAIN: auto:scatterOMP_PLACES: threadsOMP_PROC_BIND: spread

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	2	0	1	0	1	0	1	0	1	0	1	0	1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	0.05	0.01
2x2	2	2	4	2	0.02	0.01
2x4	2	1	4	4	0.05	0.01
2x8	2	1	1	8	0.04	0.01
2x16	2	1	1	16	0.02	0.01
2x32	2	1	1	32	0.03	0
2x64	2	1	1	64	0.04	0
2x96	2	1	1	96	0.05	0

Name	Coverage (%)	Time (s)
○moveAtom.A	0.01	0.04

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency