OV - - Loop 82

	Loop Id: 82	Module: exec	Source: ljForce.c:161-161 [...]	Coverage: 0.37%

0x40b968 MOVQ	$0,(%RBX)    [3]

0x40b96f ADD	$0x40,%RCX

0x40b973 ADD	$0xc0,%RBX

0x40b97a MOVQ	$0,-0xb8(%RBX)    [2]

0x40b985 MOVQ	$0,-0xb0(%RBX)    [2]

0x40b990 MOVQ	$0,-0x40(%RCX)    [1]

0x40b998 MOVQ	$0,-0xa8(%RBX)    [2]

0x40b9a3 MOVQ	$0,-0xa0(%RBX)    [2]

0x40b9ae MOVQ	$0,-0x98(%RBX)    [2]

0x40b9b9 MOVQ	$0,-0x38(%RCX)    [1]

0x40b9c1 MOVQ	$0,-0x90(%RBX)    [2]

0x40b9cc MOVQ	$0,-0x88(%RBX)    [2]

0x40b9d7 MOVQ	$0,-0x80(%RBX)    [2]

0x40b9df MOVQ	$0,-0x30(%RCX)    [1]

0x40b9e7 MOVQ	$0,-0x78(%RBX)    [2]

0x40b9ef MOVQ	$0,-0x70(%RBX)    [2]

0x40b9f7 MOVQ	$0,-0x68(%RBX)    [2]

0x40b9ff MOVQ	$0,-0x28(%RCX)    [1]

0x40ba07 MOVQ	$0,-0x60(%RBX)    [2]

0x40ba0f MOVQ	$0,-0x58(%RBX)    [2]

0x40ba17 MOVQ	$0,-0x50(%RBX)    [2]

0x40ba1f MOVQ	$0,-0x20(%RCX)    [1]

0x40ba27 MOVQ	$0,-0x48(%RBX)    [2]

0x40ba2f MOVQ	$0,-0x40(%RBX)    [2]

0x40ba37 MOVQ	$0,-0x38(%RBX)    [2]

0x40ba3f MOVQ	$0,-0x18(%RCX)    [1]

0x40ba47 MOVQ	$0,-0x30(%RBX)    [2]

0x40ba4f MOVQ	$0,-0x28(%RBX)    [2]

0x40ba57 MOVQ	$0,-0x20(%RBX)    [2]

0x40ba5f MOVQ	$0,-0x10(%RCX)    [1]

0x40ba67 MOVQ	$0,-0x18(%RBX)    [2]

0x40ba6f MOVQ	$0,-0x10(%RBX)    [2]

0x40ba77 MOVQ	$0,-0x8(%RBX)    [2]

0x40ba7f MOVQ	$0,-0x8(%RCX)    [1]

0x40ba87 CMP	%RDX,%RCX

0x40ba8a JNE	40b968

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h: 22 - 24

--------------------------------------------------------------------------------

22:    a[0] = 0.0;

23:    a[1] = 0.0;

24:    a[2] = 0.0;

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 161 - 161

--------------------------------------------------------------------------------

161:       s->atoms->U[ii] = 0.;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.83
Bottlenecks	P5, P6, P7,
Function	ljForce._omp_fn.0
Source	mytype.h:22-24,ljForce.c:161-161
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	0.67
Front-end cycles	5.83
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	0.00
Nb stores	32.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.83
Bottlenecks	P5, P6, P7,
Function	ljForce._omp_fn.0
Source	mytype.h:22-24,ljForce.c:161-161
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	0.67
Front-end cycles	5.83
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	0.00
Nb stores	32.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ljForce._omp_fn.0
Source file and lines	ljForce.c:161-161
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 10.67 to 0.67 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.67 to 5.83 cycles (1.83x speedup).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	36
nb uops	35
loop length	296
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.83
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

37% of peak store performance is reached (24.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b968

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0xc0,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVQ $0,-0xb8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0xb0(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x40(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0xa8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0xa0(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x98(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x38(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x90(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x88(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x80(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x30(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x78(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x70(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x68(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x28(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x60(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x58(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x50(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x20(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x48(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x40(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x38(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x18(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x30(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x28(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x20(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x18(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JNE 40b968 <ljForce._omp_fn.0+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

Function	ljForce._omp_fn.0
Source file and lines	ljForce.c:161-161
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/mytype.h:22-24
/beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c:161

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 256 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	36
nb uops	35
loop length	296
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	10.67	10.67	10.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.83
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles. At this rate:

37% of peak store performance is reached (24.00 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40b968

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOVQ $0,(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
ADD $0x40,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0xc0,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVQ $0,-0xb8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0xb0(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x40(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0xa8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0xa0(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x98(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x38(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x90(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x88(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x80(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x30(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x78(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x70(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x68(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x28(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x60(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x58(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x50(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x20(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x48(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x40(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x38(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x18(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x30(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x28(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x20(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x10(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x18(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x10(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x8(%RBX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
MOVQ $0,-0x8(%RCX)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMP %RDX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JNE 40b968 <ljForce._omp_fn.0+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

▶Scalability Runs Description

Run 2x1	Number processes: 1Number nodes: 1Run Command: <executable> -x 100 -y 100 -z 100 --xproc=2 --yproc=1 --zproc=1MPI Command: mpirun -np 2Dataset: Run Directory: /beegfs/hackathon/users/eoseret/qaas_runs/170-850-7424/intel/CoMD/run/oneview_runs/compilers/gcc_4/oneview_run_1708509263OMP_NUM_THREADS: 1
Run 2x2	OMP_NUM_THREADS: 2
Run 2x4	OMP_NUM_THREADS: 4
Run 2x8	OMP_NUM_THREADS: 8
Run 2x16	OMP_NUM_THREADS: 16
Run 2x32	OMP_NUM_THREADS: 32
Run 2x64	OMP_NUM_THREADS: 64
Run 2x96	OMP_NUM_THREADS: 96

(2x1) Efficiency	(2x1) Potential Speed-Up (%)	(2x2) Efficiency	(2x2) Potential Speed-Up (%)	(2x4) Efficiency	(2x4) Potential Speed-Up (%)	(2x8) Efficiency	(2x8) Potential Speed-Up (%)	(2x16) Efficiency	(2x16) Potential Speed-Up (%)	(2x32) Efficiency	(2x32) Potential Speed-Up (%)	(2x64) Efficiency	(2x64) Potential Speed-Up (%)	(2x96) Efficiency	(2x96) Potential Speed-Up (%)
1	0	0.74	0.13	0.55	0.29	0.25	0.96	0.14	1.63	0.09	2.26	0.03	4	0.03	3.52

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
2x1	2	1	1	1	1.06	0.37
2x2	4	0.74	1.48	2	0.72	0.49
2x4	8	0.55	2.19	4	0.61	0.64
2x8	16	0.25	2.02	8	0.77	1.28
2x16	32	0.14	2.28	16	1.1	1.9
2x32	64	0.09	2.76	32	0.58	2.47
2x64	128	0.03	2.1	64	0.59	4.14
2x96	192	0.03	2.5	96	0.35	3.61

Report Configuration

Vectorization

Details

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Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

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General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Colums Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency